CN110429030B - Preparation method of nano gate and nano gate device - Google Patents
Preparation method of nano gate and nano gate device Download PDFInfo
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- CN110429030B CN110429030B CN201910696974.0A CN201910696974A CN110429030B CN 110429030 B CN110429030 B CN 110429030B CN 201910696974 A CN201910696974 A CN 201910696974A CN 110429030 B CN110429030 B CN 110429030B
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
Abstract
The invention is suitable for the technical field of semiconductor devices, and provides a preparation method of a nano gate, which comprises the following steps: according to a photoresist pattern on the first photoresist deposited on the surface of the first dielectric layer, performing first etching on the region except the photoresist pattern on the surface of the first dielectric layer, removing the first photoresist deposited on the surface of the first dielectric layer after the first etching, and obtaining a step structure formed by the substrate and the first dielectric layer after the first etching; depositing a metal layer on the horizontal surface and the vertical side wall of the step structure, and growing a second dielectric layer on the surface of the metal layer; performing second etching on the metal layer and the second dielectric layer; and growing a third dielectric layer on the step structure after the second etching, and polishing the surface of the third dielectric layer to enable the upper surface of the third dielectric layer to be flush and expose the metal corresponding to the metal layer, thereby obtaining the nano gate. The invention uses the metal layer of the vertical side wall of the step as the nano-gate, can accurately control the size of the nano-gate and reduce the manufacturing difficulty of the nano-gate.
Description
Technical Field
The invention belongs to the technical field of semiconductor devices, and particularly relates to a nano gate and a preparation method of the nano gate device.
Background
In the field of integrated circuits, in order to improve the performance and integration of semiconductor chips, the feature sizes of transistors based on silicon materials have been shrinking for decades and are approaching their physical limits.
The gate is the control terminal of the transistor, the size of which has a significant impact on the performance of the electronic device. At present, the processing of nanoscale gate length dimensions for devices becomes increasingly difficult. When an electronic device is prepared by using the existing photoetching technology, the gate length of the electronic device not only depends on the resolution of photoetching equipment, but also depends on various influence factors such as photoresist types, baking temperature, exposure dose, developing temperature and time in the photoetching process. This results in devices with gate length dimensions that are not easily controlled precisely, especially with gates of nanometer scale that are difficult to fabricate. In order to maintain the continuous development of the integrated circuit industry, a new preparation method needs to be developed, so that the preparation of a gate with a nanoscale can be simplified, the long dimension of the gate can be accurately controlled, the preparation of a nano-gate device can be realized, and the performance of an electronic device can be further improved.
Disclosure of Invention
In view of this, the embodiment of the present invention provides a method for manufacturing a nano gate, so as to solve the problems that the length and the size of a device gate are not easily controlled precisely due to various influencing factors in the existing photolithography process, and especially, the nano-scale gate is difficult to manufacture.
A first aspect of an embodiment of the present invention provides a method for manufacturing a nanogate, including:
according to a photoresist pattern on a first photoresist deposited on the surface of a first dielectric layer grown on a substrate, carrying out first etching on the area of the surface of the first dielectric layer except the photoresist pattern, removing the first photoresist deposited on the surface of the first dielectric layer after the first etching, and obtaining a step structure formed by the substrate and the first dielectric layer after the first etching;
depositing a metal layer on the horizontal surface and the vertical side wall of the step structure, and growing a second dielectric layer on the surface of the metal layer;
performing second etching on the metal layer and the second dielectric layer;
and growing a third dielectric layer on the step structure after the second etching, and polishing the surface of the third dielectric layer to enable the upper surface of the third dielectric layer to be flush and expose the metal corresponding to the metal layer, thereby obtaining the nano gate.
Optionally, the substrate is a semi-insulating substrate or a high-resistance substrate.
Optionally, the semi-insulating substrate is made of any one of silicon, silicon carbide, sapphire and diamond;
the material of the high-resistance substrate is any one of glass, flexible polyester film, flexible polyimide film, mica or ceramic.
Optionally, the first dielectric layer, the second dielectric layer, and the third dielectric layer are grown by using an atomic layer deposition ALD apparatus or a plasma enhanced chemical vapor deposition PECVD apparatus.
Optionally, the first dielectric layer, the second dielectric layer, and the third dielectric layer are made of one or a combination of silicon dioxide, aluminum oxide, hafnium oxide, titanium oxide, silicon nitride, and aluminum nitride.
Optionally, the thickness of the first dielectric layer is 100 nm;
the thickness of the second dielectric layer is 10 nm;
the thickness of the third dielectric layer is 120 nm.
Optionally, the first etching is dry etching of the region outside the photoresist pattern on the surface of the first dielectric layer by using an inductively coupled plasma ICP etching apparatus.
Optionally, the thickness of the metal layer is 1nm-500 nm.
Optionally, the depositing a metal layer on the horizontal surface and the vertical sidewall of the step structure includes:
depositing a metal layer with the thickness of 10nm on the horizontal deposition surface and the vertical side wall of the step structure by adopting electron beam evaporation equipment;
the metal layer is made of one or more of gold, silver, copper, aluminum, zinc, molybdenum, iridium, tungsten, cobalt, cadmium, nickel, iron, platinum, chromium, titanium, palladium, germanium, lead and beryllium.
A second aspect of an embodiment of the present invention provides a method for manufacturing a nano-gate device, including: after the nano-gate is manufactured by adopting the method for manufacturing the nano-gate in any embodiment, a gate dielectric layer grows on the upper surface of the polished third dielectric layer;
preparing a semiconductor material on the gate dielectric layer;
according to the photoresist pattern on the second photoresist deposited on the semiconductor material, carrying out third etching on the gate dielectric layer and the semiconductor material corresponding to the region except the photoresist pattern on the second photoresist until the metal corresponding to the metal layer is exposed;
and preparing a grid electrode of the nano-grid device on the nano-grid, and preparing a source electrode and a drain electrode of the nano-grid device on a conductive channel region which is not formed by the grid dielectric layer and the semiconductor material etched by the third etching.
According to the embodiment of the invention, the step structure is formed by the substrate and the etched first dielectric layer, the metal layer on the horizontal surface of the step structure is deposited and removed, the metal layer on the vertical side wall of the step structure is reserved, the nano gate is prepared by utilizing the metal layer on the vertical side wall of the step structure, the nano gate is manufactured by the step structure instead of depositing multi-layer photoresist for photoetching, the manufacturing difficulty of the nano gate is reduced, the size of the nano gate can be accurately controlled by setting the thickness of the metal layer, and the high-precision nano gate is obtained.
By using the nano-gate prepared by the embodiment of the invention to prepare the nano-gate device, the embodiment of the invention can obtain the high-precision nano-gate, so that the nano-gate device with the high-precision gate length can be obtained, and the performance of the nano-gate device is further improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the embodiments or the prior art descriptions will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise.
Fig. 1 is a schematic flow chart of a method for manufacturing a nanogate according to an embodiment of the invention;
FIG. 2(1) is a schematic structural diagram of a first dielectric layer grown on a substrate according to an embodiment of the present invention;
fig. 2(2) is a schematic structural diagram of forming a photoresist pattern on a first photoresist according to an embodiment of the present invention;
fig. 2(3) is a schematic structural diagram after the first etching is performed according to an embodiment of the present invention;
fig. 2(4) is a schematic structural diagram of a deposited metal layer and a grown second dielectric layer according to an embodiment of the present invention;
fig. 2(5) is a schematic structural diagram of the metal layer and the second dielectric layer after the second etching according to the embodiment of the present invention;
fig. 2(6) is a schematic structural diagram illustrating a third dielectric layer grown on the step structure after the second etching according to an embodiment of the present invention;
fig. 2(7) is a schematic structural diagram of a nano-gate obtained by polishing a surface of a third dielectric layer according to an embodiment of the present invention;
fig. 3(1) is a schematic structural diagram of growing a gate dielectric layer and a semiconductor material on a nano gate according to an embodiment of the present invention;
fig. 3(2) is a schematic structural diagram after a third etching is performed on the gate dielectric layer and the semiconductor material according to the embodiment of the present invention;
fig. 3(3) is a schematic structural diagram of a nano-gate device according to an embodiment of the present invention.
In the figure: 1-a substrate; 2-a first dielectric layer; 3-photoresist pattern on the first photoresist; 4-a metal layer; 5-a second dielectric layer; 6-a third dielectric layer; 7-a gate dielectric layer; 8-a semiconductor material; 9-a grid; 10-a source electrode; 11-drain electrode.
Detailed Description
In the following description, for purposes of explanation and not limitation, specific details are set forth, such as particular system structures, techniques, etc. in order to provide a thorough understanding of the embodiments of the invention. It will be apparent, however, to one skilled in the art that the present invention may be practiced in other embodiments that depart from these specific details. In other instances, detailed descriptions of well-known systems, devices, circuits, and methods are omitted so as not to obscure the description of the present invention with unnecessary detail.
In order to explain the technical means of the present invention, the following description will be given by way of specific examples.
Referring to fig. 1 and 2(1) to 2(7), a method for manufacturing a nano-gate according to an embodiment of the present invention includes:
step S101, according to a photoresist pattern 3 on a first photoresist deposited on the surface of a first dielectric layer 2 grown on a substrate 1, performing first etching on the area of the surface of the first dielectric layer except the photoresist pattern 3, and removing the first photoresist deposited on the surface of the first dielectric layer after the first etching to obtain a step structure formed by the substrate 1 and the first dielectric layer 2 after the first etching.
Referring to fig. 2(1), a first dielectric layer 2 is grown on a substrate 1.
As shown in fig. 2(2), the photoresist pattern 3 on the first photoresist covers a portion of the first dielectric layer, a first etching is performed on a region not covered by the photoresist pattern 3 on the first photoresist, and the photoresist represented by the photoresist pattern 3 on the first photoresist is removed, so as to obtain a step structure formed by the substrate 1 and the first etched first dielectric layer 2 in fig. 2 (3).
Optionally, the substrate 1 is a semi-insulating substrate or a high-resistance substrate.
Optionally, the semi-insulating substrate is made of any one of silicon, silicon carbide, sapphire and diamond; the material of the high-resistance substrate is any one of glass, flexible polyester film, flexible polyimide film, mica or ceramic.
The flexible polyester film (PET) is a PET film for short, and is a colorless transparent glossy film which is usually prepared by taking Polyethylene terephthalate as a raw material, preparing a thick sheet by an extrusion method, and stretching in two directions. The oil resistance, the air tightness and the aroma retention are good, and the composite film is one of commonly used permeability-resistant composite film substrates.
The flexible Polyimide Film (PI) is called PI Film for short, is a Film type insulating material with the best performance in the world, and is formed by performing polycondensation and casting on pyromellitic dianhydride and diaminodiphenyl ether in a strong polar solvent to form a Film and then performing imidization.
The PI film is yellow and transparent, the relative density is 1.39-1.45, the PI film has excellent high and low temperature resistance, electrical insulation, cohesiveness, radiation resistance and medium resistance, can be used for a long time within the temperature range of-269-280 ℃, and can reach the high temperature of 400 ℃ in a short time. The glass transition temperatures of the PI membranes of the conventional manufacturers were 280 ℃ (Upilex R), 385 ℃ (Kapton) and above 500 ℃ (Upilex S), respectively. The tensile strength of the PI film at 20 ℃ is 200MPa, and the tensile strength of the PI film at 200 ℃ is more than 100MPa, so that the PI film is particularly suitable for being used as a base material of a flexible printed circuit board and insulating materials of various high-temperature-resistant motors and electrical appliances.
Illustratively, on a semi-insulating silicon carbide substrate 1, an alumina first dielectric Layer 2 is grown by using an Atomic Layer Deposition (ALD) device, and the thickness is 100 nm; and coating a first photoresist on the surface of the first alumina dielectric layer 2, and forming a photoresist pattern 3 on the first photoresist after exposure and development.
Illustratively, a first dielectric layer 2 of silicon dioxide is grown on a high-resistance silicon substrate 1 by using a Plasma Enhanced Chemical Vapor Deposition (PECVD) device, and the thickness is 100 nm; and coating a first photoresist on the surface of the silicon dioxide first dielectric layer 2, and forming a photoresist pattern 3 on the first photoresist after exposure and development.
In the embodiment of the present invention, the thickness of the first dielectric layer is not limited, and the thickness of the first dielectric layer is 100nm, which is a specific embodiment of the substrate in the embodiment of the present invention.
The ALD apparatus is a technique for plating a substrate surface with a substance in the form of a single atomic film layer by using an atomic layer deposition method, wherein a chemical reaction of a new atomic film layer is directly related to a previous atomic film layer in the atomic layer deposition process, and only one atomic layer is deposited in each reaction.
Due to the high controllability (thickness, components and structure) of deposition parameters and the excellent deposition uniformity and consistency, the atomic layer deposition technology has wide application potential in the fields of wiener electronics, nano materials and the like, such as the fields of transistor gate dielectric layers (high-k) and metal gate electrodes.
In the PECVD apparatus, a gas containing atoms constituting a thin film is locally formed into a plasma by means of microwave or radio frequency, etc., and the plasma has a strong chemical activity and is easily reacted to deposit a desired thin film on a substrate. The PECVD equipment is utilized to grow the dielectric layer, and the method has the advantages of high deposition rate, good film forming quality, fewer pinholes and difficult cracking.
Optionally, an Inductively Coupled Plasma (ICP) etching device is used to perform dry etching on the region outside the photoresist pattern 3 on the surface of the first dielectric layer.
The dry etching has the characteristic of anisotropy, a steep and smooth side wall structure can be etched, and after all the area which is not covered by the photoresist pattern 3 on the first photoresist is etched, the first photoresist is removed to form a step structure with a steep and straight side wall.
The etching is to remove the part of the lower layer material which is not masked by the upper layer masking material by a physical and/or chemical method, so as to obtain a pattern completely corresponding to the pattern of the masking film on the lower layer material, the etching is divided into dry etching and wet etching, the dry etching is to use a radio frequency power supply to enable reaction gas to generate ions and electrons with high reaction activity, and to carry out physical bombardment and chemical reaction on the part to be etched, so as to selectively remove the area to be removed.
The ICP etching technology is one of dry etching, the device for performing dry etching by utilizing the ICP etching technology is called ICP equipment for short, the ICP etching technology has the advantages of high etching speed, high selectivity ratio, high anisotropy, small etching damage, good large-area uniformity, high controllability of an etching section profile, flat and smooth etching surface and the like, and the ICP etching technology is widely applied to etching of materials such as silicon, silicon dioxide, III-V compounds and the like and has a good etching effect.
Step S102, depositing a metal layer 4 on the horizontal surface and the vertical side wall of the step structure, and growing a second dielectric layer 5 on the surface of the metal layer 4.
Optionally, the material of the metal layer 4 is one or a combination of more of gold, silver, copper, aluminum, zinc, molybdenum, iridium, tungsten, cobalt, cadmium, nickel, iron, platinum, chromium, titanium, palladium, germanium, lead, and beryllium.
Optionally, the thickness of the metal layer 4 is 1nm to 500 nm.
Illustratively, referring to fig. 2(4), a 10nm gold layer 4 is deposited on the outer surface of the step (including horizontal surfaces and vertical sidewalls) by using an electron beam evaporation apparatus, and then a 10nm thick silicon dioxide or aluminum oxide second dielectric layer 5 is grown on the surface of the gold layer 4 by using a PECVD apparatus or an ALD apparatus.
Step S103, carrying out second etching on the metal layer 4 and the second dielectric layer 5.
Illustratively, the second dielectric layer of aluminum oxide on the horizontal surface of the step structure is etched first by using an ICP apparatus, the second dielectric layer of aluminum oxide on the vertical sidewall is remained, and then the gold layer on the horizontal surface of the step structure is etched by using an ICP apparatus, and the gold layer on the vertical sidewall is remained.
Illustratively, the silicon dioxide second dielectric layer on the horizontal surface of the step structure is etched first by using an ICP apparatus, the silicon dioxide second dielectric layer on the vertical sidewall is remained, and then the gold layer on the horizontal surface of the step structure is etched by using the ICP apparatus, and the gold layer on the vertical sidewall is remained.
Referring to fig. 2(5), the metal layer 4 and the second dielectric layer 5 remain on the vertical sidewall of the step structure.
The second dielectric layer 5 on the vertical sidewall has the function of protecting the metal layer 4, so that when the metal layer 4 is etched, the metal layer on the vertical sidewall is not etched, and the thickness of the metal layer is always kept unchanged.
And because the ICP device is etched from top to bottom, the second dielectric layer and the metal layer on the vertical side wall can be reserved.
And step S104, growing a third dielectric layer 6 on the step structure after the second etching, and polishing the surface of the third dielectric layer 6 to enable the upper surface of the third dielectric layer 6 to be flush and expose the metal corresponding to the metal layer 4, so as to obtain the nano gate.
Illustratively, by using an ALD device, an alumina third dielectric layer with a thickness of 120nm is grown on the surface of the step structure after the second etching, a planarization polishing process is performed on the surface of the alumina third dielectric layer, the step structure after the alumina third dielectric layer is grown is polished flat, the upper surface of the alumina third dielectric layer is leveled, and a gold layer with a thickness of 10nm is exposed, so that a flat and smooth surface is obtained.
Optionally, the third dielectric layer may also be a 120nm thick silicon dioxide third dielectric layer.
The thickness of the third dielectric layer is not limited in the embodiment of the present invention, the thickness of the third dielectric layer is 120nm, which is a specific embodiment of the substrate in the embodiment of the present invention, and the specific thickness of the third dielectric layer is determined according to an actual situation.
Fig. 2(6) is a schematic structural diagram of growing a third dielectric layer 6 on the step structure after the second layer is etched, and fig. 2(7) is a schematic structural diagram of a nano-gate obtained after polishing the surface of the third dielectric layer 6.
The metal layer forms a nano-grid structure, the size of the nano-grid is accurately controlled when the thickness of the metal layer is evaporated by the electron beam evaporation equipment, and the metal layer with the thickness as low as 1nm can be obtained by the electron beam evaporation equipment.
Optionally, the materials of the first dielectric layer 2, the second dielectric layer 5, and the third dielectric layer 6 are all one or a combination of multiple of silicon dioxide, aluminum oxide, hafnium oxide, titanium oxide, silicon nitride, and aluminum nitride.
As another embodiment of the present invention, after the nano-gate is fabricated by using the method for fabricating a nano-gate described in any of the above embodiments, a gate dielectric layer 7 is grown on the polished surface of the third dielectric layer 6.
A semiconductor material 8 is prepared on the gate dielectric layer 7.
Referring to fig. 3(1), a gate dielectric layer 7 is grown on the polished surface of the third dielectric layer 6, and a semiconductor material 8 is prepared on the gate dielectric layer 7.
Referring to fig. 3(2), according to a photoresist pattern on the second photoresist deposited on the semiconductor material 8, the gate dielectric layer 7 and the semiconductor material 8 corresponding to a region outside the photoresist pattern on the second photoresist are etched for the third time until the metal corresponding to the metal layer is exposed.
Referring to fig. 3(3), a gate electrode of the nano-gate device is prepared on the nano-gate, and a source electrode and a drain electrode of the nano-gate device are prepared on a conductive channel region formed by the gate dielectric layer and the semiconductor material which are not etched by the third etching.
Illustratively, an alumina gate dielectric layer 7 with a thickness of 10nm is grown on the polished third dielectric layer 6 by using an ALD apparatus, and then graphene prepared by a Chemical Vapor Deposition (CVD) method is transferred onto the alumina gate dielectric layer 7 to form a semiconductor material 8 required for preparing a nano-gate device.
And coating a second photoresist on the semiconductor material 8, forming a photoresist pattern on the second photoresist after exposure and development, performing third etching on the region except the photoresist pattern on the second photoresist by using an ICP (inductively coupled plasma) device, and etching the semiconductor material 8 and the gate dielectric layer 7 until the metal corresponding to the metal layer 4 is exposed.
The aluminum oxide gate dielectric layer 7 with the thickness of 10nm is a specific embodiment in the embodiments of the present invention, and the thickness of the gate dielectric layer is not limited in the present invention.
The metal corresponding to the metal layer is the nano-gate manufactured by the method for manufacturing the nano-gate according to any one of the embodiments.
And forming a conductive channel region by using the gate dielectric layer 7 and the semiconductor material 8 protected by the photoresist pattern on the second photoresist, forming a gate on the nano gate, and forming a source and a drain on the conductive channel region to form the graphene-based nano gate device.
Illustratively, a silicon dioxide gate dielectric layer 7 with the thickness of 10nm is grown on the polished third dielectric layer 6 by using PECVD equipment, and then molybdenum disulfide is transferred onto the silicon dioxide gate dielectric layer 7 to form a semiconductor material 8 required for preparing a nano gate device.
And coating a second photoresist on the semiconductor material 8, forming a photoresist pattern on the second photoresist after exposure and development, performing third etching on the region except the photoresist pattern on the second photoresist by using an ICP (inductively coupled plasma) device, and etching the semiconductor material 8 and the gate dielectric layer 7 until the metal corresponding to the metal layer 4 is exposed.
The silicon dioxide gate dielectric layer 7 with the thickness of 10nm is a specific embodiment in the embodiments of the present invention, and the thickness of the gate dielectric layer is not limited in the present invention.
The metal corresponding to the metal layer is the nano-gate manufactured by the method for manufacturing the nano-gate according to any one of the embodiments.
And forming a conductive channel region by using the gate dielectric layer 7 and the semiconductor material 8 protected by the photoresist pattern on the second photoresist, forming a gate on the nano gate, and forming a source electrode and a drain electrode on the conductive channel region to form the molybdenum disulfide-based nano gate device.
Optionally, the material of the gate dielectric layer 7 is the same as the material of the first dielectric layer 2, the second dielectric layer 5, and the third dielectric layer 6, and may be one or a combination of silicon dioxide, aluminum oxide, hafnium oxide, titanium oxide, silicon nitride, and aluminum nitride.
Optionally, the semiconductor material 8 is one or more of graphene, two-dimensional transition metal chalcogenide, black scale, diamond, silicon, gallium oxide, gallium nitride, indium phosphide, silicon carbide, and an organic semiconductor material.
According to the nano-gate device in the embodiment of the invention, the high-precision nano-gate prepared in the embodiment of the invention is utilized, so that the nano-gate device with the high-precision gate length can be obtained, and the performance of the nano-gate device is improved.
The above-mentioned embodiments are only used for illustrating the technical solutions of the present invention, and not for limiting the same; although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not substantially depart from the spirit and scope of the embodiments of the present invention, and are intended to be included within the scope of the present invention.
Claims (8)
1. A method for preparing a nano-gate device is characterized by comprising the following steps:
according to a photoresist pattern on a first photoresist deposited on the surface of a first dielectric layer grown on a substrate, carrying out first etching on the area of the surface of the first dielectric layer except the photoresist pattern, removing the first photoresist deposited on the surface of the first dielectric layer after the first etching, and obtaining a step structure formed by the substrate and the first dielectric layer after the first etching;
depositing a metal layer on the horizontal surface and the vertical side wall of the step structure, and growing a second dielectric layer on the surface of the metal layer; the thickness of the metal layer is 1nm-500 nm;
performing second etching on the metal layer and the second dielectric layer, so that the metal layer and the second dielectric layer on the horizontal surface of the step structure are etched after the second etching;
growing a third dielectric layer on the step structure after the second etching, and polishing the surface of the third dielectric layer to enable the upper surface of the third dielectric layer to be flush and expose the metal corresponding to the metal layer, so as to obtain a nano gate;
growing a gate dielectric layer on the upper surface of the polished third dielectric layer;
preparing a semiconductor material on the gate dielectric layer;
according to the photoresist pattern on the second photoresist deposited on the semiconductor material, carrying out third etching on the gate dielectric layer and the semiconductor material corresponding to the region except the photoresist pattern on the second photoresist until the metal corresponding to the metal layer is exposed;
and preparing a grid electrode of the nano-grid device on the nano-grid, and preparing a source electrode and a drain electrode of the nano-grid device on a conductive channel region which is not formed by the grid dielectric layer and the semiconductor material etched by the third etching.
2. The method of fabricating a nanogate device as defined in claim 1,
the substrate is a semi-insulating substrate or a high-resistance substrate.
3. The method of fabricating a nanogate device as defined in claim 2,
the semi-insulating substrate is made of any one of silicon, silicon carbide, sapphire or diamond;
the material of the high-resistance substrate is any one of glass, flexible polyester film, flexible polyimide film, mica or ceramic.
4. The method of fabricating a nanogate device as defined in claim 1,
the first dielectric layer, the second dielectric layer and the third dielectric layer are grown by adopting Atomic Layer Deposition (ALD) equipment or Plasma Enhanced Chemical Vapor Deposition (PECVD) equipment.
5. The method of fabricating a nanogate device as defined in claim 1,
the first dielectric layer, the second dielectric layer and the third dielectric layer are made of one or a combination of silicon dioxide, aluminum oxide, hafnium oxide, titanium oxide, silicon nitride and aluminum nitride.
6. The method of fabricating a nanogate device as defined in any one of claims 1 to 5,
the thickness of the first dielectric layer is 100 nm;
the thickness of the second dielectric layer is 10 nm;
the thickness of the third dielectric layer is 120 nm.
7. The method for preparing a nano-gate device according to claim 1, wherein the first etching is dry etching of the region outside the photoresist pattern on the surface of the first dielectric layer by using Inductively Coupled Plasma (ICP) etching equipment.
8. The method of claim 1, wherein depositing a metal layer on horizontal surfaces and vertical sidewalls of the step structure comprises:
depositing a metal layer with the thickness of 10nm on the horizontal deposition surface and the vertical side wall of the step structure by adopting electron beam evaporation equipment;
the metal layer is made of one or more of gold, silver, copper, aluminum, zinc, molybdenum, iridium, tungsten, cobalt, cadmium, nickel, iron, platinum, chromium, titanium, palladium, germanium, lead and beryllium.
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| US4313782A (en) * | 1979-11-14 | 1982-02-02 | Rca Corporation | Method of manufacturing submicron channel transistors |
| US4430791A (en) * | 1981-12-30 | 1984-02-14 | International Business Machines Corporation | Sub-micrometer channel length field effect transistor process |
| JPH10189764A (en) * | 1996-12-20 | 1998-07-21 | Texas Instr Inc <Ti> | Vertical soi device |
| US8461647B2 (en) * | 2010-03-10 | 2013-06-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device having multi-thickness gate dielectric |
| CN101807597B (en) * | 2010-04-02 | 2012-12-05 | 中国电子科技集团公司第五十五研究所 | Autoregistration submicron gate structure and manufacturing method thereof |
| US20140231914A1 (en) * | 2013-02-19 | 2014-08-21 | Applied Materials, Inc. | Fin field effect transistor fabricated with hollow replacement channel |
| US9683957B2 (en) * | 2013-05-29 | 2017-06-20 | Csir | Field effect transistor and a gas detector including a plurality of field effect transistors |
| CN105405893B (en) * | 2015-12-21 | 2018-09-14 | 华南理工大学 | A kind of planar split dual gate thin film transistor (TFT) and preparation method thereof |
| CN109728086A (en) * | 2017-10-31 | 2019-05-07 | 中国工程物理研究院电子工程研究所 | The preparation method of side wall grid high mobility transistor |
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