CN110411577B - Asynchronous reading circuit of SPAD detector array and asynchronous reading method thereof - Google Patents

Asynchronous reading circuit of SPAD detector array and asynchronous reading method thereof Download PDF

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CN110411577B
CN110411577B CN201910665805.0A CN201910665805A CN110411577B CN 110411577 B CN110411577 B CN 110411577B CN 201910665805 A CN201910665805 A CN 201910665805A CN 110411577 B CN110411577 B CN 110411577B
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李玉
张钰
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Shanghai Qinzhi Technology Development Co.,Ltd.
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Hangzhou Dianzi University
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Abstract

The invention discloses an asynchronous reading circuit of an SPAD detector array and an asynchronous reading method thereof. The prior asynchronous mode has incomplete priority mechanism, and can not relieve the reading conflict of photons with similar arrival time, thereby causing the omission of partial effective photons. The asynchronous readout circuit of the SPAD detector array comprises a counting trigger OR gate, an external counter, an external comparison module, a controller and m pixel internal modules. The pixel internal module comprises a TDC circuit, a quenching circuit, a stay trigger and a comparison counter. The comparison counter comprises a 1 st feedback circuit, a 2 nd feedback circuit, … …, an n-1 st feedback circuit, a front-end circuit and n counting units. The invention matches the corresponding address value according to the output sequence of the array, reduces the output of redundant information, thereby improving the output efficiency, simultaneously solving the output conflict problem of pixels and avoiding the omission of effective pixel information.

Description

Asynchronous reading circuit of SPAD detector array and asynchronous reading method thereof
Technical Field
The invention belongs to the technical field of image sensor reading circuits, and particularly relates to an asynchronous reading circuit structure of an SPAD detector array and an asynchronous reading method thereof.
Background
With the development of scientific technology and the progress of device technology, the photoelectric imaging technology is widely applied in different fields in daily life of people. In recent years, a Single Photon Avalanche Diode (SPAD) detector attracts the attention of researchers in all countries around the world by virtue of the advantages of high self-sensitivity, strong integration, high detection speed, low power consumption, capability of detecting extremely weak optical signals and the like, rapidly occupies a place in the field of photoelectric detection, and is widely applied to the fields of biological research, fluorescence lifetime measurement, laser imaging radar and the like. The read-out circuit designed by matching with the SPAD detector array can record and output the time of each pixel photon detected in application so as to complete imaging, and is of great importance to the performance of the detector.
The read-out circuit (ROIC) can be divided into two major categories, analog and digital, and has become a mainstream application because the digital ROIC has the advantages of better noise suppression, detection sensitivity, convenience in integration, and the like. The digital ROIC can be divided into a synchronous mode and an asynchronous mode, in the synchronous mode, the read-out circuit needs to wait for the detection of all pixels of the array to be finished to perform unified operation on the array, and the pixels are output one by one according to the sequence of rows and columns, so that the dead time of the array is longer, and meanwhile, because not every pixel of the array receives photons in a weak light environment, the output of the array is completely output, so that a large amount of redundant information exists in output data, and the output rate is slowed down. In an asynchronous mode, each pixel in the array can work independently, photon detection and reading of different pixels are allowed to be carried out simultaneously, photon detection efficiency is effectively improved, and the requirement for output bandwidth is reduced. However, the prior asynchronous mode has a poor priority mechanism, and cannot relieve the read-out collision of photons with close arrival time, so that part of effective photons are missed.
Disclosure of Invention
The invention aims to provide an asynchronous reading circuit structure of a SPAD detector array and an asynchronous reading method thereof.
The asynchronous reading circuit of the SPAD detector array comprises a counting trigger OR gate, an external counter, an external comparison module, a controller and m pixel internal modules, wherein m is the number of pixels of the SPAD detector array. The m pixels of the SPAD detector array are arranged in a row and a column. The external comparison module provides output enable signals EN for the m pixel internal modules respectively.
The pixel internal module comprises a TDC circuit, a quenching circuit, a stay trigger and a comparison counter. And an input pin of the quenching circuit is connected with an output pin of the single photon avalanche diode in the corresponding pixel. And an input pin of the TDC circuit is connected with an output pin of the quenching circuit. And an output enable pin of the TDC circuit is connected with an output enable signal EN corresponding to the pixel internal module.
And m input ends of the counting trigger OR gate are respectively connected with output pins of the quenching circuits in the m pixel internal modules. The counting enable end of the external counter is connected with the output end of the counting trigger OR gate. The external counter has an n-bit output.
The controller has c row signal input interfaces and d column signal input interfaces, 2c≥a+1，2dB +1 is not less than. The output ends of d TDC circuits in the p-th row of pixels of the SPAD detector array are connected with the signal input interfaces of each row in the p-th row signal connection combination. The p-th row signal connection combination comprises 1 or 2 or … … or c row signal input interfaces. The a row signal connection combinations connected with the a row pixels are different from each other; p is 1,2, … …, a.
The output ends of c TDC circuits in the q-th row of pixels of the SPAD detector array are connected with the signal input interfaces of all rows in the q-th row signal connection combination. The q column signal connection combination comprises 1 or 2 or … … or d column signal input interfaces. The b row signal combinations connected to the b columns of pixels are completely different from each other, q is 1,2, … …, b.
The stay trigger comprises a set D trigger and a set AND gate. The first input end of the set AND gate is connected with the inverse signal of the output enable signal EN corresponding to the pixel internal module, and the second input end of the set AND gate is connected with the output pin of the corresponding quenching circuit. And the output end of the SET AND gate is connected with the SET pin of the SET D flip-flop. The CE pin and the D pin of the set D trigger are both grounded, the RST pin is connected with the output enabling signal EN of the corresponding pixel point, and the CP pin is connected with the clock signal CLK. The Q output end of the set D flip-flop is the output end of the stay flip-flop.
The comparison counter comprises a 1 st feedback circuit, a 2 nd feedback circuit, … …, an n-1 st feedback circuit, a front-end circuit and n counting units.
The front-end circuit comprises CTThe signal D trigger, a preposed AND gate, a preposed OR gate, a first data selector and a second data selector. The first input end of the preposed OR gate is connected with the output end of the counting trigger OR gate through a phase inverter, and the second input end of the preposed OR gate is connected with the output end of the corresponding stay trigger. The first input end of the preposed AND gate is connected with the output end of the counting trigger OR gate, and the second input end of the preposed AND gate is connected with the output end of the corresponding stay trigger through a phase inverter. The output ends of the prepositive OR gate and the prepositive AND gate are respectively connected with the first data input ends of the first data selector and the second data selector. The second data input ends of the first data selector and the second data selector are respectively connected with the high level and the ground wire, the control ends are respectively connected with the output enable signal EN of the corresponding pixel point, and the output end is connected with the CTThe RST pin and the SET pin of the signal D trigger are respectively connected. The CP pin of the D trigger is connected with a clock signal CLK, and the CE pin and the D pin are both grounded. The Q output of the D flip-flop is used as the output of the pre-circuit, i.e. the control signal C of the comparison counterT。
The counting unit comprises a first input AND gate, a second input AND gate, a third input AND gate, an input OR gate and a comparison D trigger. The output ends of the first input AND gate, the second input AND gate and the third input AND gate are respectively connected with the three input ends of the input OR gate. The output end of the input OR gate is connected with a D pin of the comparison D trigger.
The four input ends of the first input AND gate in the 1 st counting unit are connected with the inverse signal of the zero clearing signal CR, the inverse signal of the setting signal LD and the control signal CTThe inverse signal of the 1 st counting unit and the Q output end of the comparison D trigger of the 1 st counting unit are respectively connected. Three input ends of the second input AND gate, an inverse signal of the zero clearing signal CR, a setting signal LD and d of the external counter0The output ends are respectively connected. The four input ends of the third input AND gate, the inverse signal of the zero clearing signal CR, the inverse signal of the setting signal LD and the control signal CTAnd the Q' output ends of the comparison D triggers of the 1 st counting unit are respectively connected.
The input ends of the first input and gate, the second input and gate and the third input and gate in the ith counting unit are connected in a mode that i is 2,3, …, n. The four input ends of the first input AND gate in the ith counting unit are connected with the inverse signal of the zero clearing signal CR, the inverse signal of the setting signal LD and the control signal CTAnd the output ends of the (n-1) th feedback circuits are respectively connected. Three input ends of the second input AND gate, an inverse signal of the zero clearing signal CR, a setting signal LD and d of the external counteri-1The output ends are respectively connected. The four input ends of the third input AND gate, the inverse signal of the zero clearing signal CR, the inverse signal of the setting signal LD and the control signal CTThe inverse signal of the counter unit and the Q output end of the comparison D trigger of the ith counting unit are respectively connected.
The j-th feedback circuit comprises j +1 feedback AND gates and one feedback OR gate, wherein j is 1,2, …, n-1. The first feedback AND gate has j +1 input ends, and the Q output end of the D trigger for comparison from the 1 st counting unit to the j th counting unit and the Q' output end Q of the D trigger for comparison from the j +1 th counting unitj' separately connected. The second feedback AND gate to the (j + 1) th feedback AND gate all have two input ends. The first input ends from the second feedback AND gate to the (j + 1) th feedback AND gate are respectively connected with the (j + 1) th counting unitQ output Q of element comparison D triggerjAnd the second input end is respectively connected with the Q' output ends of the comparison D triggers from the 1 st counting unit to the j counting unit. The output ends of the j +1 feedback AND gates are respectively connected with the j +1 input ends of the feedback OR gate; the output end of the feedback or gate is the output end of the jth feedback circuit.
The Q output ends of comparison D triggers in n comparison counting units in one comparison counter are combined to form a digital signal output interface of the comparison counter.
The external comparison module comprises a minimum comparator and m comparison AND gates. The minimum comparator is provided with m digital signal input interfaces and m minimum signal output pins. The m digital signal input interfaces, the m minimum signal output pins, the m comparison AND gates and the m pixel internal modules are in one-to-one correspondence. Each digital signal input interface on the minimum comparator consists of n signal input pins. And m digital signal input interfaces on the minimum comparator are respectively connected with digital signal output interfaces of comparison counters in the m pixel internal modules. The first input ends of the m comparison AND gates are respectively connected with the m minimum signal output pins of the minimum comparator, and the second input ends of the m comparison AND gates are respectively connected with the output ends of the corresponding stay triggers in the pixel internal modules. The signals output by the output ends of the m comparison and gates are output enable signals EN of the m pixels.
Preferably, the clear signal CR is derived from a trigger signal of the laser source. The setting signal LD is from the output enable signal EN of the corresponding pixel point.
Preferably, the minimum signal output pin corresponding to the digital signal input interface with the minimum input value in the minimum comparator outputs 1, and the rest minimum signal output interfaces all output 0.
Preferably, the minimum comparator is obtained by simulating through an FPGA.
Preferably, m is 64, a is 8, and b is 8.
The asynchronous readout method of the asynchronous readout circuit of the SPAD detector array comprises a comparison counter part and a selection output part.
The comparison counter part is specifically as follows:
the laser source sends out laser pulse, and the zero clearing signal CR of the comparison counter is input to be set to be 1; the TDC circuitry within each pixel internal module begins timing. When a single photon avalanche diode in one pixel point of the SPAD detector array receives photons, the single photon avalanche diode generates avalanche, and a corresponding quenching circuit outputs a high level signal stop. The high level signal stop output by the quenching circuit increases the value recorded by the external counter by 1, the output end of the corresponding stay trigger is set to be 1, and the control signal C of the corresponding comparison counter is inputTSetting to be 0, and keeping an output interface of the corresponding comparison counter unchanged; control signal C of the remaining m-1 comparison counters is inputTAll are set to 1, so the values recorded by the remaining m-1 comparison counters are increased by 1.
The selection output part is specifically as follows:
step one, the minimum comparator compares the recorded values of the m comparison counters, and the minimum signal output pin corresponding to the digital signal input interface with the minimum input value in the minimum comparator outputs 1, so that the output enable signal EN corresponding to the pixel internal module which receives photons earliest in the m pixel internal modules which do not output data is set to be 1.
Step two, outputting a time signal of receiving the photon to the controller by a TDC circuit in the pixel internal module with the output enable signal EN set to be 1; the output end of a stay trigger in the pixel internal module is cleared to be 0, a setting signal LD of a comparison counter is set to be 1, and the value recorded by the comparison counter is the value recorded by an external counter.
The invention has the beneficial effects that:
the invention introduces comparison arbitration, only reads out the information of the pixels receiving photons in the array, distributes the output priority of the hit pixels according to the sequence of arrival of the photons in the array, and simultaneously matches the corresponding address values according to the output sequence of the array, thereby reducing the output of redundant information, improving the output efficiency, solving the problem of output conflict of the pixels and avoiding the omission of effective pixel information.
Drawings
FIG. 1 is a schematic view of the overall structure of the present invention;
FIG. 2 is a schematic circuit diagram of a stay flip-flop of the present invention;
FIG. 3 is a schematic circuit diagram of a comparison counter according to the present invention;
FIG. 4 is a circuit schematic of an external comparison module of the present invention;
FIG. 5 is a schematic diagram of the connection between c row signal input interfaces of the controller and the pixels in each row according to the present invention;
FIG. 6 is a schematic diagram of the connection of d row signal input interfaces of the controller to the pixels in each column according to the present invention;
FIG. 7 is a comparison diagram of the read conditions of the present invention and a conventional asynchronous read circuit;
fig. 8 is a graph comparing the read number of the present invention with that of a conventional asynchronous read circuit.
Detailed Description
The invention is further described below with reference to the accompanying drawings.
As shown in fig. 1, the asynchronous readout circuit of the SPAD detector array includes a count trigger or gate, an external counter current, an external comparison module 1, a controller 2, and m pixel internal modules 3, where m is the number of pixels of the SPAD detector array. The m pixels of the SPAD detector array are arranged in a row and a column, wherein m is 64, a is 8, and b is 8. The external comparison module 1 provides the output enable signal EN for the m pixel internal modules 3, respectively.
The pixel internal module 3 includes a TDC circuit (time-to-digital converter), A Quench Circuit (AQC), a stay flip-flop, and a comparison counter. The TDC circuit and the quenching circuit respectively employ a time-to-digital converter and a quenching circuit in the prior art, which are not described herein. And an input pin of the quenching circuit is connected with an output pin of the single photon avalanche diode in the corresponding pixel. And an input pin of the TDC circuit is connected with an output pin of the quenching circuit. The TDC circuit is used for recording the time when the single photon avalanche diode receives the photon. An output enable pin of the TDC circuit is connected to an output enable signal EN corresponding to the pixel internal block 3.
M input ends of the counting trigger or gate are respectively connected with output pins of the quenching circuits in the m pixel internal modules 3. The counting enable end of the external counter current is connected with the output end of the counting trigger OR gate. The external counter current has n-bit outputs (d respectively)0Output terminal, d1Output terminal … …, dn-1Output terminal), n is 5.
As shown in fig. 2 and 3, the controller has c row signal input interfaces and d column signal input interfaces, 2c≥a+1，2dB +1 is more than or equal to; in the embodiment, c is 4, and d is 4. According to the rule of binary arrangement, the c line signal input interfaces can form 2c-1 mutually different row-signalling combinations. 2c-1 row signal connection combination and 2c1 row address values (1B, 10B, 11B, … …, 1111B; B is a binary symbol) correspond, respectively; d column signal input interfaces can form 2d-1 column signal connection combination. 2d-1 column signal connection combination and 2d-1 mutually different column address values correspond respectively.
The output ends of d TDC circuits in the p-th row of pixels of the SPAD detector array are connected with the signal input interfaces of each row in the p-th row signal connection combination. The p-th row signal connection combination comprises 1 or 2 or … … or c row signal input interfaces. The a row signal connection combinations connected with the a row pixels are different from each other; p is 1,2, … …, a.
The output ends of c TDC circuits in the q-th row of pixels of the SPAD detector array are connected with the signal input interfaces of all rows in the q-th row signal connection combination. The q column signal connection combination comprises 1 or 2 or … … or d column signal input interfaces. The b row signal combinations connected to the b columns of pixels are completely different from each other, q is 1,2, … …, b.
Thus, each pixel corresponds to a row address value and a column address value; when a TDC circuit in a pixel outputs a time signal to a controller, all interfaces in a row signal connection combination and a row signal connection combination corresponding to the TDC circuit on the controller receive the time signal; the controller determines a row address value and a column address value corresponding to a TDC circuit outputting the time signal according to the row signal input interface serial number and the column signal input interface serial number of the received time signal, thereby realizing address matching. The address matching mode makes the pixels in the row a share one row address bus and the pixels in the column b share one column address bus, but the access modes of the address control lines in each row and each column are different. The address bus pulls up a 1 when no pixel is output. Because the pixels in the array are output in the order of arrival of photons, only one pixel is output to the data bus each time, when the pixel obtains an output enable signal, the row selection column line corresponding to the pixel internal module 3 pulls down the corresponding address bus, and for the row encoder and the column encoder, a determined and unique code can be obtained, namely, the address value matched with the pixel.
As shown in fig. 4, the stay flip-flop includes a set D flip-flop U1 and a set and gate. The first input end of the set AND gate is connected with the inverse signal (obtained by an inverter) of the output enable signal EN corresponding to the pixel internal module 3, and the second input end of the set AND gate is connected with the output pin of the corresponding quenching circuit. The output enable signal EN comes from the external comparison module 1. And the output end of the SET AND gate is connected with the SET pin of the SET D flip-flop. The CE and D pins of the set D trigger U1 are grounded, the RST pin is connected with the output enable signal EN of the corresponding pixel point, and the CP pin is connected with the clock signal CLK. The Q output of the set D flip-flop U1 is the output of the stay flip-flop. When the output enable signal EN is 0 and the quenching circuit outputs 1, the output terminal of the stay flip-flop is set to 1, and the output terminal of the stay flip-flop is kept 1 before the output enable signal EN is 1.
As shown in fig. 5, the comparison counter includes a 1 st feedback circuit, a 2 nd feedback circuit, … …, an n-1 st feedback circuit, one pre-circuit, and n counting units.
The front-end circuit comprises CTSignal D flip-flop U3, a pre-and gate, a pre-or gate, first data selector U4, and second data selector U5. The first input end of the preposed OR gate is connected with the output end of the counting trigger OR gate through a phase inverter, and the second input end of the preposed OR gate is connected with the output end of the corresponding stay trigger. The first input end of the prepositive AND gate is connected with the output end of the counting trigger OR gate, and the second input end is connected with the corresponding stay triggerAre connected by an inverter. The output ends of the pre-OR gate and the pre-AND gate are respectively connected with the first data input ends of the first data selector U4 and the second data selector U5. The second data input ends of the first data selector U4 and the second data selector U5 are respectively connected with a high level and a ground wire, the control ends are respectively connected with the output enable signal EN of the corresponding pixel point, and the output end is connected with the CTThe RST pin and the SET pin of the signal D flip-flop U3 are connected, respectively. The CP pin of the D flip-flop U3 is connected with a clock signal CLK, and the CE pin and the D pin are both connected with the ground. The Q output end of the D flip-flop U3 is used as the output end C of the front-end circuitT。
When all quench circuits output 0; the output end of the front OR gate is set to be 1, the front AND gate is cleared, the first data selector U4 outputs 1, the second data selector U5 outputs 0, and the output end C of the front circuit is enabled to be connected with the output end C of the front circuitTAnd (6) clearing.
When one quenching circuit outputs 1 and the prepositive circuit corresponds to the output 0 of the stay trigger, the output end of the prepositive OR gate is cleared; the pre AND gate 1, the first data selector U4 output 0, the second data selector U5 output 1, so that the output C of the pre circuitTIs set to 1.
When the output of the front-end circuit corresponds to the output 0 of the stay trigger, the output end of the front-end OR gate is set to be 1, the front-end AND gate is cleared, the first data selector U4 outputs 1, and the second data selector U5 outputs 0, so that the output end C of the front-end circuit is enabled to be CTAnd (6) clearing.
When the output enable signal EN corresponding to the pixel inner module 3 is set to 1, the first data selector U4 outputs 1, and the second data selector U5 outputs 0, so that the output end C of the front-end circuitTAnd (6) clearing.
The comparison counter needs to input a zero clearing signal CR, a setting signal LD and a control signal CT. The clear signal CR is derived from a trigger signal START of the laser source (when the signal is set to a high level, the laser source emits laser light, and the comparison counter is cleared). The setting signal LD is from the output enable signal EN and control signal C of the corresponding pixelTFrom the output of the pre-circuit.
The counting unit comprises a first input AND gate, a second input AND gate, a third input AND gate, an input OR gate and a comparison D flip-flop U2. The output ends of the first input AND gate, the second input AND gate and the third input AND gate are respectively connected with the three input ends of the input OR gate. The output of the input or gate is connected to the D pin of a comparison D flip-flop U2.
The four input ends of the first input AND gate in the 1 st counting unit are connected with the inverse signal of the zero clearing signal CR, the inverse signal of the setting signal LD and the control signal CTThe inverse signal of (1) th counting unit and the Q output terminal Q0 of the comparison D flip-flop are connected respectively. Three input ends of the second input AND gate, the inverse signal of the zero clearing signal CR, the setting signal LD and the d of the external counter current0The output ends are respectively connected. The four input ends of the third input AND gate, the inverse signal of the zero clearing signal CR, the inverse signal of the setting signal LD and the control signal CTQ' output end Q of comparison D trigger of 1 st counting unit0' separately connected. The signal output by the Q' output end in the D trigger is the inverse signal of the Q output end.
The input ends of the first input and gate, the second input and gate and the third input and gate in the ith counting unit are connected in a mode that i is 2,3, …, n. The four input ends of the first input AND gate in the ith counting unit are connected with the inverse signal of the zero clearing signal CR, the inverse signal of the setting signal LD and the control signal CTAnd the output ends of the (n-1) th feedback circuits are respectively connected. Three input ends of the second input AND gate, the inverse signal of the zero clearing signal CR, the setting signal LD and the d of the external counter currenti-1The output ends are respectively connected. The four input ends of the third input AND gate, the inverse signal of the zero clearing signal CR, the inverse signal of the setting signal LD and the control signal CTInverse signal of (1), Q output end Q of comparison D flip-flop of ith counting uniti-1Are respectively connected.
The connection relationship from the 1 st feedback circuit to the n-1 st feedback circuit is as follows:
the j-th feedback circuit comprises j +1 feedback AND gates and one feedback OR gate, wherein j is 1,2, …, n-1. The first feedback AND gate has j +1 input ends, and the Q output end of the D trigger for comparison from the 1 st counting unit to the j th counting unit and the Q' output end Q of the D trigger for comparison from the j +1 th counting unitj' separately connected. The second feedback AND gate to the (j + 1) th feedback AND gate all have two input ends. The first input ends of the second feedback AND gate to the (j + 1) th feedback AND gate are compared with the Q output end Q of the D trigger of the (j + 1) th counting unitjAnd the second input end is respectively connected with the Q' output ends of the comparison D triggers from the 1 st counting unit to the j counting unit. The output ends of the j +1 feedback AND gates are respectively connected with the j +1 input ends of the feedback OR gate; the output end of the feedback or gate is the output end of the jth feedback circuit.
Therefore, the output value Q of the D flip-flop U2 at the time of the next clock cycle can be compared in the ith counting uniti Second order stateThe expression of (a) is as follows:
Figure BDA0002140078940000081
from this, the truth table of the comparison counter is as follows:
Figure BDA0002140078940000082
it can be seen that, after the laser source emits laser light, the clear signal CR is set to 1, so that Q is set toi Second order stateAnd clearing, and then resetting the clear signal CR. When the control signal CTZero clearing, Qi Second order stateIs constant equal to original QiI.e. QiNo further changes occur. When the setting signal LD is set to 1, Qi Second order stateUpdating to d with an external counteriThe output terminals are equal.
The Q output ends of comparison D triggers in n comparison counting units in one comparison counter are combined to form a digital signal output interface of the comparison counter. The values output by the n Q output ends are sequentially arranged to obtain a value which is the output signal of the comparison counter.
The external comparison module 1 comprises a minimum comparator U6 and m comparison and gates. The minimum comparator U6 is provided with m digital signal input interfaces and m minimum signal output pins min. The minimum signal output pin min corresponding to the digital signal input interface with the minimum input value in the minimum comparator U6 outputs 1, and the other minimum signal output interfaces all output 0. The minimum comparator U6 is obtained by simulation through an FPGA (Field-Programmable Gate Array). The m digital signal input interfaces, the m minimum signal output pins, the m comparison AND gates and the m pixel internal modules 3 are in one-to-one correspondence. Each digital signal input interface on the minimum comparator U6 consists of n signal input pins. The m digital signal input interfaces of the minimum comparator U6 are respectively connected with the digital signal output interfaces of the comparison counters in the m pixel internal modules 3. The first input ends of the m comparison and gates are respectively connected with the m minimum signal output pins of the minimum comparator U6, and the second input ends of the m comparison and gates are respectively connected with the output ends of the corresponding stay flip-flops in the pixel internal module 3. The signals output by the output ends of the m comparison and gates are output enable signals EN of the m pixels.
The asynchronous readout method of the asynchronous readout circuit of the SPAD detector array comprises a comparison counter part and a selection output part.
The comparison counter part is specifically as follows:
the laser source sends out laser pulse, and the zero clearing signal CR of the comparison counter is input to be set to be 1; the TDC circuitry within each pixel internal block 3 starts timing. When a single photon avalanche diode in one pixel point of the SPAD detector array receives photons, the single photon avalanche diode generates avalanche, and a corresponding quenching circuit outputs a high level signal stop. The high level signal stop output by the quenching circuit increases the value recorded by the current of the external counter by 1, the output end of the corresponding stay trigger is set to be 1, and the control signal C of the corresponding comparison counter is inputTSetting to be 0, and keeping an output interface of the corresponding comparison counter unchanged; control signal C of the remaining m-1 comparison counters is inputTAll are set to 1, so the values recorded by the remaining m-1 comparison counters are increased by 1.
The selection output part is specifically as follows:
step one, the minimum comparator U6 compares the values recorded by the m comparison counters, and the minimum signal output pin corresponding to the digital signal input interface with the minimum input value in the minimum comparator U6 outputs 1, so that the output enable signal EN corresponding to the pixel internal module 3 which receives the photon earliest in the m pixel internal modules 3 which do not output data is set to 1.
Step two, outputting a time signal of receiving the photon to the controller 2 by the TDC circuit in the pixel internal module 3 with the output enable signal EN set to 1; the output end of a stay trigger in the pixel internal module 3 is reset to 0, a setting signal LD of a comparison counter is set to 1, and the value recorded by the comparison counter is set to the value recorded by the external counter current.
Therefore, the function that the internal modules 3 of each pixel sequentially output time signals according to the arrival sequence of photons is realized. The controller judges the position of the pixel of the output signal by judging the serial number of the row signal input interface and the serial number of the column signal input interface of the output signal.
Fig. 7 is a comparison graph of the read results of the asynchronous read circuit of the present invention and the conventional asynchronous read circuit, in order to verify the experimental results, behavior simulation is performed in vivado software, and under the same photon arrival condition, the photon detection and read behavior of a part of pixels are compared, the upper part of fig. 7 is the read result of the present invention, and the lower part is the read result of the conventional design, and the simulation graph shows: the asynchronous reading circuit can sequentially read related pixels without omission according to the arrival sequence of photons, the traditional asynchronous reading circuit has the omission of partial pixel information under the condition that the photons arrive at the same time or the arrival time is close because of the imperfect collision mechanism, and three signals circled in the figure are omitted in the traditional asynchronous reading circuit.
FIG. 8 is a graph comparing the read rates of the asynchronous read circuit of the present invention and a conventional asynchronous read circuit. Compared with the traditional asynchronous circuit, under the condition that the number of array detection photons is continuously increased, the photon reading quantity of the invention is obviously greater than that of other designs, and the reading rate of effective information is improved.
In this embodiment, the asynchronous circuit of the present invention removes redundant data from the source, reduces the data transmission amount, optimizes the priority mechanism of asynchronous output, greatly improves the photon reading rate, and reduces the loss of effective information.

Claims (6)

  1. The asynchronous reading circuit of the SPAD detector array comprises a counting trigger OR gate, an external counter, a controller and m pixel internal modules, wherein m is the number of pixels of the SPAD detector array; the method is characterized in that: the device also comprises an external comparison module; the m pixels of the SPAD detector array are arranged in a row and a column; the external comparison module respectively provides output enabling signals EN for the m pixel internal modules;
    the pixel internal module comprises a TDC circuit, a quenching circuit, a stay trigger and a comparison counter; the TDC circuit is a time-to-digital converter; an input pin of the quenching circuit is connected with an output pin of the single-photon avalanche diode in the corresponding pixel; an input pin of the TDC circuit is connected with an output pin of the quenching circuit; an output enable pin of the TDC circuit is connected with an output enable signal EN corresponding to the pixel internal module;
    m input ends of the counting trigger OR gate are respectively connected with output pins of the quenching circuits in the m pixel internal modules; the counting enabling end of the external counter is connected with the output end of the counting trigger OR gate; the external counter has an n-bit output;
    the controller has c row signal input interfaces and d column signal input interfaces, 2c≥a+1，2dB +1 is more than or equal to; d TDC circuit output ends in the p row of pixels of the SPAD detector array are connected with signal input interfaces of each row in the p row signal connection combination; the p row signal connection combination comprises 1 or 2 or … … or c row signal input interfaces; the a row signal connection combinations connected with the a row pixels are different from each other; p ═ 1,2, … …, a;
    c TDC circuit output ends in a q-th row of pixels of the SPAD detector array are connected with signal input interfaces of all rows in a q-th row signal connection combination; the q column signal connection combination comprises 1 or 2 or … … or d column signal input interfaces; the b row signal connection combinations connected with the b columns of pixels are different from each other, and q is 1,2, … …, b;
    the stay trigger comprises a set D trigger and a set AND gate; the first input end of the set AND gate is connected with the inverse signal of the output enable signal EN corresponding to the pixel internal module, and the second input end of the set AND gate is connected with the output pin of the corresponding quenching circuit; the output end of the SET AND gate is connected with the SET pin of the SET D trigger; setting the CE and D pins of the D trigger to be grounded, connecting the RST pin with an output enable signal EN of a corresponding pixel point, and connecting the CP pin with a clock signal CLK; setting the Q output end of the D trigger as the output end of a stay trigger;
    the comparison counter comprises a 1 st feedback circuit, a 2 nd feedback circuit, … …, an n-1 st feedback circuit, a front-end circuit and n counting units;
    the front-end circuit comprises CTThe device comprises a signal D trigger, a preposed AND gate, a preposed OR gate, a first data selector and a second data selector; the first input end of the preposed OR gate is connected with the output end of the counting trigger OR gate through a phase inverter, and the second input end of the preposed OR gate is connected with the output end of the corresponding stay trigger; the first input end of the preposed AND gate is connected with the output end of the counting trigger OR gate, and the second input end of the preposed AND gate is connected with the output end of the corresponding stay trigger through a phase inverter; the output ends of the pre-OR gate and the pre-AND gate are respectively connected with the first data input ends of the first data selector and the second data selector; the second data input ends of the first data selector and the second data selector are respectively connected with the high level and the ground wire, the control ends are respectively connected with the output enable signal EN of the corresponding pixel point, and the output end is connected with the CTThe RST pin and the SET pin of the signal D trigger are respectively connected; the CP pin of the D trigger is connected with a clock signal CLK, and the CE pin and the D pin are both grounded; the Q output of the D flip-flop is used as the output of the pre-circuit, i.e. the control signal C of the comparison counterT；
    The counting unit comprises a first input AND gate, a second input AND gate, a third input AND gate, an input OR gate and a comparison D trigger; the output ends of the first input AND gate, the second input AND gate and the third input AND gate are respectively connected with the three input ends of the input OR gate; the output end of the input OR gate is connected with a D pin of the comparison D trigger;
    the four input ends of the first input AND gate in the 1 st counting unit are connected with the inverse signal of the zero clearing signal CR, the inverse signal of the setting signal LD and the control signal CTThe inverse signal of the 1 st counting unit and the Q output end of the comparison D trigger of the 1 st counting unit are respectively connected; three input ends of the second input AND gate, an inverse signal of the zero clearing signal CR, a setting signal LD and d of the external counter0The output ends are respectively connected; the four input ends of the third input AND gate, the inverse signal of the zero clearing signal CR, the inverse signal of the setting signal LD and the control signal CTThe Q' output ends of the comparison D triggers of the 1 st counting unit are respectively connected;
    the input ends of a first input AND gate, a second input AND gate and a third input AND gate in the ith counting unit are connected in a mode that i is 2,3, …, n; the four input ends of the first input AND gate in the ith counting unit are connected with the inverse signal of the zero clearing signal CR, the inverse signal of the setting signal LD and the control signal CTThe output ends of the (n-1) th feedback circuits are respectively connected; three input ends of the second input AND gate, an inverse signal of the zero clearing signal CR, a setting signal LD and d of the external counteri-1The output ends are respectively connected; the four input ends of the third input AND gate, the inverse signal of the zero clearing signal CR, the inverse signal of the setting signal LD and the control signal CTThe inverse signal of the counter unit is respectively connected with the Q output end of the comparison D trigger of the ith counting unit;
    the jth feedback circuit comprises j +1 feedback AND gates and one feedback OR gate, wherein j is 1,2, …, n-1; wherein, the first feedback AND gate has j +1 input terminals, and the Q output terminal of the D flip-flop compared with the 1 st to j th counting units and the Q ' output terminal Q ' of the D flip-flop compared with the j +1 th counting unit 'jAre respectively connected; the second feedback AND gate to the (j + 1) th feedback AND gate are provided with two input ends; the first input ends of the second feedback AND gate to the (j + 1) th feedback AND gate are compared with the Q output end Q of the D trigger of the (j + 1) th counting unitjThe second input end is respectively connected with the Q' output ends of the comparison D triggers from the 1 st counting unit to the jth counting unit; the output ends of the j +1 feedback AND gates are respectively connected with the j +1 input ends of the feedback OR gate; the output of the feedback OR gate isj the output terminal of the feedback circuit;
    the Q output ends of comparison D triggers in n comparison counting units in one comparison counter are combined to form a digital signal output interface of the comparison counter;
    the external comparison module comprises a minimum comparator and m comparison AND gates; the minimum comparator is provided with m digital signal input interfaces and m minimum signal output interfaces; the m digital signal input interfaces, the m minimum signal output interfaces, the m comparison AND gates and the m pixel internal modules are in one-to-one correspondence; each digital signal input interface on the minimum comparator consists of n signal input pins; the m digital signal input interfaces on the minimum comparator are respectively connected with the digital signal output interfaces of the comparison counters in the m pixel internal modules; the first input ends of the m comparison AND gates are respectively connected with the m minimum signal output interfaces of the minimum comparator, and the second input ends of the m comparison AND gates are respectively connected with the output ends of the corresponding stay triggers in the pixel internal modules; the signals output by the output ends of the m comparison and gates are output enable signals EN of the m pixels.
  2. 2. The asynchronous readout circuit of a SPAD detector array of claim 1, wherein: the zero clearing signal CR is from a trigger signal of a laser source; the setting signal LD is from the output enable signal EN of the corresponding pixel point.
  3. 3. The asynchronous readout circuit of a SPAD detector array of claim 1, wherein: the minimum signal output interface corresponding to the digital signal input interface with the minimum input value in the minimum comparator outputs 1, and the other minimum signal output interfaces all output 0.
  4. 4. The asynchronous readout circuit of a SPAD detector array of claim 1, wherein: and the minimum comparator is obtained by simulating through the FPGA.
  5. 5. The asynchronous readout circuit of a SPAD detector array of claim 1, wherein: m is 64, a is 8 and b is 8.
  6. 6. The asynchronous readout method of the asynchronous readout circuitry of the SPAD detector array of claim 1, wherein: comprises a comparison counter part and a selection output part;
    the comparison counter part is specifically as follows:
    the laser source sends out laser pulse, and the zero clearing signal CR of the comparison counter is input to be set to be 1; starting timing by a TDC circuit in each pixel internal module; when a single photon avalanche diode in one pixel point of the SPAD detector array receives photons, the single photon avalanche diode generates avalanche, and a corresponding quenching circuit outputs a high level signal stop; the high level signal stop output by the quenching circuit increases the value recorded by the external counter by 1, the output end of the corresponding stay trigger is set to be 1, and the control signal C of the corresponding comparison counter is inputTSetting to be 0, and keeping an output interface of the corresponding comparison counter unchanged; control signal C of the remaining m-1 comparison counters is inputTAll are set to 1, so the numerical values recorded by the other m-1 comparison counters are increased by 1;
    the selection output part is specifically as follows:
    step one, a minimum comparator compares the recorded values of m comparison counters, and the minimum signal output interface corresponding to the digital signal input interface with the minimum input value in the minimum comparator outputs 1, so that the output enable signal EN corresponding to the pixel internal module which receives photons earliest in m pixel internal modules which do not output data is set to be 1;
    step two, outputting a time signal of receiving the photon to the controller by a TDC circuit in the pixel internal module with the output enable signal EN set to be 1; the output end of a stay trigger in the pixel internal module is cleared, a setting signal LD of a comparison counter is set to be 1, and the value recorded by the comparison counter is the value recorded by an external counter.
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