WO2023206352A1

WO2023206352A1 - Apparatus for light detection and ranging

Info

Publication number: WO2023206352A1
Application number: PCT/CN2022/090254
Authority: WO
Inventors: Varol Mutlu; Chuang YAN; Bei Yu; Chengzhi XIE; Yudong Xu
Original assignee: Huawei Technologies Co., Ltd.
Priority date: 2022-04-29
Filing date: 2022-04-29
Publication date: 2023-11-02

Abstract

An apparatus (102) for light detection and ranging (LiDAR) includes a light detector with a pixel array (106) configured to detect photons from incident light. Further, the apparatus (102) includes a time-measuring circuit (108) that is disposed outside the pixel array (106). The time-measuring circuit (108) is configured to store a single timestamp value when any pixel in the pixel array (106) is hit by a photon at a given time. Further, the apparatus (102) includes a plurality of shift registers that are configured to store timestamp addressing data for each pixel that is hit by a photon and a processing unit (112) to co-relate the timestamp value with the timestamp addressing data for each pixel for distance measurement or object detection. Therefore, the apparatus (102) is beneficial to improve the reliability, resolution, and performance of the LiDAR systems with reduced power consumption.

Description

APPARATUS FOR LIGHT DETECTION AND RANGING

TECHNICAL FIELD

The present disclosure relates generally to the field of light detection and ranging (LiDAR) sensors and more specifically, to an apparatus for light detection and ranging.

BACKGROUND

LiDAR systems are used to analyze the environment and detect objects by an infrared laser, which is transmitted through a light source and received by a light detector (or a sensor) after striking an object. The light source converts electric current to light photons, and the light detector converts the light photons back to electric current. The light detector is often built as a two-dimensional array of light-sensitive pixels and detector, and a read-out-integrated-circuit (ROIC) . Further, a high-speed time-measuring circuit (HS-TMC) is used with the ROIC to measure the time between two subsequent events. The LiDAR systems are generally used in different application areas, such as consumer appliances, industrial applications, space applications, or automotive applications. Further, the LiDAR systems are used to detect the object based on various parameters, such as distance, geometry, size, moving speed, or direction. Moreover, the LiDAR systems are configured to use different parameters to provide the access to a mobile phone for face-recognition, precise docking of a space capsule, or autonomous driving of vehicles in road traffic. However, the conventional LiDAR systems are not very reliable for autonomous driving in harsh environmental conditions, such as for reliable detection of the object from a long distance.

Currently, certain attempts have been made to improve the performance of the conventional LiDAR systems, such as by utilizing a smaller number of light-sensitive pixels to reduce the number of HS-TMC. However, in such attempts, the issue of circuit complexity was partially resolved, which further makes the emission and scanning of the light more complicated and less reliable due to moving parts. Another attempt was made to achieve higher resolutions by using multiple HS-TMCs. However, in such attempts, the circuit complexity is again increased that further affects the reliability of the LiDAR systems. Furthermore, a high-resolution image of the field-of-view is required to achieve the accurate detection of the objects from a long distance, and the conventional attempts do not provide a high-resolution image of the field-of-view. As a result, there exists a technical problem of how to improve the reliability, resolution, and performance of the LiDAR systems for distance measurement and object detection with a reduced power consumption of the LiDAR systems.

Therefore, in light of the foregoing discussion, there exists a need to overcome the aforementioned drawbacks associated with the conventional LiDAR systems.

SUMMARY

The present disclosure provides an apparatus for light detection and ranging. The present disclosure provides a solution to the existing problem of how to improve the reliability, resolution, and performance of light detection and ranging (LiDAR) systems for distance measurement and object detection with a reduced power consumption of the LiDAR systems. An aim of the present disclosure is to provide a solution that overcomes at least partially the problem encountered in the prior art and provides an improved apparatus for light detection and ranging with timestamp-addressing pixels for LiDAR automotive applications.

One or more objectives of the present disclosure are achieved by the solutions provided in the enclosed independent claims. Advantageous implementations of the present disclosure are further defined in the dependent claims.

In one aspect, the present disclosure provides an apparatus for light detection and ranging. The system includes a light detector with a pixel array configured to detect photons from incident light. Further, the system includes a time-measuring circuit that is disposed outside the pixel array and is configured to store a single timestamp value when any pixel in the pixel array is hit by a photon at a given time. Further, the system includes a plurality of shift registers configured to store timestamp addressing data for each pixel that is hit by a photon and a processing unit to co-relate the timestamp value with the timestamp addressing data for each pixel for distance measurement or object detection.

The apparatus is used for light detection and ranging. The apparatus includes the light detector to detect the photons from the incident light. Further, the apparatus includes the time-measuring circuit that is disposed outside the pixel array and stores the single timestamp value when any pixel in the pixel array is hit by the photon. The time-measuring circuit is beneficial to reduce the complexity and the power consumption of the apparatus. Further, the apparatus includes the plurality of shift registers to store timestamp addressing data for each pixel that is hit by the photon. Moreover, the processing unit is used by the apparatus to co-relate the timestamp value with the timestamp addressing data for each pixel that is beneficial for an accurate distance measurement or object detection. Therefore. the apparatus is beneficial to improve the reliability, resolution, and the performance of the light detection and ranging systems.

In an implementation form, the time-measuring circuit includes a digital counter and a memory unit.

The digital counter and the memory unit of the time-measuring circuit are beneficial to reduce the circuit complexity and the processing speed for distance measurement with reduced power consumption.

In a further implementation form, the apparatus further includes a plurality of event detectors configured to detect a trigger signal, generated when a pixel is hit by a photon in the light detector.

In such an implementation form, the detection of the trigger signal is beneficial to store the timestamp values for each detected triggered signal in the memory unit.

In a further implementation form, the apparatus further includes an event collector that is configured to collect all the event trigger signals and generate an output signal to increment an address counter after the storage of the timestamp value.

Beneficially, the collection of all the event trigger signals and further generation of the output signal to increment the address counter enables the apparatus to count the number of generated output signals after the storage of the timestamp value.

In a further implementation form, each of the plurality of event detectors is configured to generate a short pulse signal to act as an input to the event collector and a long pulse signal to act as input to the corresponding shift register.

The short pulse signal is used by the event collector to collect all the event trigger signals and the long pulse signal is used by the corresponding shift register to store the timestamp addressing data for each pixel that is hit by the photon.

In a further implementation form, the address counter is configured to store the timestamp value in the memory unit of the time-measuring circuit and increment the memory address for storing the next timestamp value.

In such an implementation form, the address counter includes the information related to the number of timestamp values that are stored in the memory unit that further reduces the readout process of the apparatus, which is beneficial to improve the performance of the apparatus.

In an implementation form, the apparatus further includes a plurality of analog front-end circuits configured to convert the current from a photon detected by the light detector into a voltage and then to the trigger signal for the event detector.

In such implementation form, each analog front-end circuit from the plurality of analog front-end circuits is beneficial to provide the interfacing between the light detector and the corresponding event detector from the plurality of the event detectors, such as to provide the digital input signal to the corresponding event detector from the plurality of the event detectors.

In a further implementation form, the digital counter is a binary counter or a gray-code counter.

The binary counter or the grey-code counter is beneficial to provide an interactive and less complex structure. In a further implementation form, the digital counter is configured to have a parallel output with a pre-defined bit-width.

The parallel output with the pre-defined bit-width increases the processing speed of the digital counter that further improves the performance of the apparatus.

In a further implementation form, the memory unit is configured to have parallel input/output ports connected to the parallel output of the digital counter with the pre-defined bit-width.

Beneficially, the parallel input/output ports that are connected to the parallel output of the digital counter with the pre-defined bit-width enable the apparatus to perform multiple operations.

In a further implementation form, each of the plurality of shift registers includes a plurality of digital D-Flip-Flops.

In such an implementation form, each digital D-flip flop from the plurality of digital D-flip flops is beneficial to store the timestamp addressing data for each pixel that is hit by a photon.

It is to be appreciated that all the aforementioned implementation forms can be combined.

It has to be noted that all devices, elements, circuitry, units, and means described in the present application could be implemented in the software or hardware elements or any kind of combination thereof. All steps which are performed by the various entities described in the present application, as well as the functionalities described to be performed by the various entities, are intended to mean that the respective entity is adapted to or configured to perform the respective steps and functionalities. Even if, in the following description of specific embodiments, a specific functionality or step to be performed by external entities is not reflected in the description of a specific detailed element of that entity that performs that specific step or functionality, it should be clear for a skilled person that these methods and functionalities can be implemented in respective software or hardware elements, or any kind of combination thereof. It will be appreciated that features of the present disclosure are susceptible to being combined in various combinations without departing from the scope of the present disclosure as defined by the appended claims.

Additional aspects, advantages, features, and objects of the present disclosure would be made apparent from the drawings and the detailed description of the illustrative implementations construed in conjunction with the appended claims that follow.

BRIEF DESCRIPTION OF THE DRAWINGS

The summary above, as well as the following detailed description of illustrative embodiments, is better understood when read in conjunction with the appended drawings. For the purpose of illustrating the present disclosure, exemplary constructions of the disclosure are shown in the drawings. However, the present disclosure is not limited to specific methods and instrumentalities disclosed herein. Moreover, those in the art will understand that the drawings are not to scale. Wherever possible, like elements have been indicated by identical numbers.

Embodiments of the present disclosure will now be described, by way of example only, with reference to the following diagrams wherein:

FIG. 1A is a block diagram of an apparatus for light detection and ranging, in accordance with an embodiment of the present disclosure;

FIG. 1B depicts a block diagram of an apparatus with timestamp-addressing-pixel for light detection and ranging, in accordance with another embodiment of the present disclosure;

FIG. 2 is an illustration that depicts an event detector of a pixel unit cell, in accordance with an embodiment of the present disclosure;

FIG. 3 is an illustration that depicts an event collector of an apparatus, in accordance with an embodiment of the present disclosure;

FIG. 4 is an illustration that depicts an interconnection of a pixel unit cell and an address incrementor, in accordance with an embodiment of the present disclosure; and

FIG. 5 is a graphical representation that illustrates clock cycles of timestamp addressing data for a pixel array, in accordance with an embodiment of the present disclosure.

In the accompanying drawings, an underlined number is employed to represent an item over which the underlined number is positioned or an item to which the underlined number is adjacent. A non-underlined number relates to an item identified by a line linking the non-underlined number to the item. When a number is non-underlined and accompanied by an associated arrow, the non-underlined number is used to identify a general item at which the arrow is pointing.

DETAILED DESCRIPTION OF EMBODIMENTS

The following detailed description illustrates embodiments of the present disclosure and ways in which they can be implemented. Although some modes of carrying out the present disclosure have been disclosed, those skilled in the art would recognize that other embodiments for carrying out or practising the present disclosure are also possible.

FIG. 1A is a block diagram of an apparatus for light detection and ranging, in accordance with an embodiment of the present disclosure. With reference to FIG. 1A, there is shown a block diagram 100A that depicts an apparatus 102, a light detector 104, a time-measuring circuit 108, a plurality of shift registers 110, a plurality of analog front-end circuits 124, a plurality of event detectors 118, an event collector 120, an address counter 122, and a processing unit 112. The light detector 104 includes a pixel array 106. The time-measuring circuit 108 includes a digital counter 114 and a memory unit 116. Moreover, the plurality of shift registers 110 includes a plurality of digital D-flip -flops 128. Further, the memory unit 116 includes parallel input/output ports 126.

The apparatus 102 includes suitable logic, circuitry, interfaces, and/or code that are used for light detection and ranging. The apparatus 102 includes the light detector 104 that detects the photons from an incident light and the apparatus 102 further stores a timestamp value for each pixel in the time-measuring circuit 108.

The light detector 104 is configured to detect photons from the incident light. In an example, the light detector 104 is referred to as a light sensor (or a photon detector) that is used to provide information related to distance from the scene (or object) by receiving a pulse of light that is reflected after striking a scene. In an implementation, the light detector 104 is configured to receive the reflected light. Examples of the light detector 104 include but are not limited to a single-photon avalanche diode (SPAD) sensor, a silicon photomultiplier (SiPM) , an avalanche photodiode (APD) sensor, a positive-intrinsic-negative (PIN) diode, and the like. In an example, the SPAD sensor is a single-pixel or combined into an array of pixels, that detect a photon. In an implementation, the SPAD sensor is often used as the light detector 104.

The time-measuring circuit 108 includes suitable logic, circuitry, interfaces, and/or code that is configured to store a single timestamp value when any pixel in the pixel array is hit by a photon at a given time. In an implementation, the time-measuring circuit 108 refers to a single high-speed time-measuring circuit (HS-TMC) that is a pixel-independent circuit and configured to store the timestamp value when any pixel in the pixel array 106 is hit by the photon. The time-measuring circuit 108 includes the digital counter 114 and the memory unit 116. In an implementation, the digital counter 114 is a high-speed counter. Examples of implementation of the digital counter 114 may include but are not limited to a binary counter, a gray-code counter, and the like.

The memory unit 116 may include suitable logic, circuitry, interfaces, or code that is configured to store the timestamp values. In an implementation, the memory unit 116 corresponds to a local memory, such as an Electrically Erasable Programmable Read-Only Memory (EEPROM) , Random Access Memory (RAM) , Read-Only Memory (ROM) , a central processing unit (CPU) cache memory, and the like. In another implementation, the memory unit 116 corresponds to disc storage memory, such as a Hard Disk Drive (HDD) , Flash memory, Solid-State Drive (SSD) , and the like. The memory unit 116 further includes the parallel input/output ports 126. In an example, the parallel input/output ports 126 are used to receive an input signal during a write-mode to store the timestamp values of the pixels from the pixel array 106. In another example, the parallel input/output ports 126 are used to provide an output signal during a read-mode, such as to read the timestamp values of the pixels from the pixel array 106.

The processing unit 112 includes suitable logic, circuitry, interfaces, and/or code that is configured to co-relate the timestamp value with the timestamp addressing data for each pixel for distance measurement or object detection. Examples of implementation of the processing unit 112 may include but are not limited to a central data processing device, a microprocessor, a microcontroller, a complex instruction set computing (CISC) processor, an application-specific integrated circuit (ASIC) processor, a reduced instruction set (RISC) processor, a very long instruction word (VLIW) processor, a state machine, and other processors or control circuitry.

The plurality of event detectors 118 may include suitable logic, circuitry, interfaces, or code that are configured to detect an event trigger signal to provide a small pulse signal to the event collector 120 and a long pulse signal to the plurality of shift registers 110.

The event collector 120 may include suitable logic, circuitry, interfaces, or code that is configured to collect all the event trigger signals and generate an output signal. Similarly, the address counter 122 may include suitable logic, circuitry, interfaces, or code that is configured to increment the memory address for storing the next timestamp value in the memory unit 116 of the time-measuring circuit 108.

Each analog front-end circuit converts the photon-detector current to a voltage. Moreover, each shift register from the plurality of shift registers 110 may include suitable logic, circuitry, interfaces, or code that are configured to store timestamp addressing data for each pixel. Further, each shift register from the plurality of shift registers 110 includes the plurality of digital D-flip-flops 128. In an example, each digital D-flip-flop from the plurality of digital D-flip-flops 128 corresponds to a digital electronic (or logical) circuit is used to store one bit.

There is provided the apparatus 102 for light detection and ranging. The apparatus 102 provides timestamp addressing pixels for LiDAR automotive applications. The apparatus 102 is beneficial to improve the reliability of the light detection and ranging systems with reduced processing time and reduced power consumption.

The apparatus 102 includes the light detector 104 with the pixel array 106 that is configured to detect photons from the incident light. In other words, the light detector 104 is configured to detect the photons from the incident light that is received from a light source. The light detector 104 is used to improve the performance of the apparatus 102 for light detection and ranging. In accordance with an embodiment, the apparatus 102 further includes the plurality of analog front-end circuits 124, and each analog front-end circuit is configured to convert the current from the photon detected by the light detector 104 into a voltage and then to the trigger signal for the event detector. Firstly, the photon is detected from the light detector 104. Thereafter, the plurality of analog front-end circuits 124 converts the current from the photon detected by the light detector 104 into the voltage. Finally, each analog front-end circuit from the plurality of analog front-end circuits 124 converts the voltage into the trigger signals for the corresponding event detector. Therefore, each analog front-end circuit from the plurality of analog front-end circuits 124 is beneficial to provide the interfacing between the light detector 104 and the plurality of the event detectors 118, such as to provide the trigger signals to the corresponding event detector from the plurality of the event detectors 118.

In accordance with an embodiment, the apparatus 102 includes the plurality of event detectors 118 that is configured to detect a trigger signal, which is generated when a pixel is hit by the photon in the light detector 104. In an implementation, each event detector from the plurality of event detectors 118 detects the event trigger signal generated by the photon-hit in the light detector 104 as further described in FIG. 1B and FIG. 2. In another implementation, each event detector from the plurality of the event detectors 118 detects the event trigger signal generated by the photon-hit in the light detector 104 through the corresponding analog front-end circuit from the plurality of analog front-end circuits 124. The detection of the trigger signal is beneficial to store the timestamp values in the memory unit 116. In such embodiments, each of the plurality of event detectors 118 is configured to generate a short pulse signal to act as an input to the event collector 120 and a long pulse signal to act as input to the corresponding shift register. In an implementation, the long pulse signal is generated using a standard logic cell (e.g., logical gates) as further shown and described in FIG. 1B and FIG. 2. In another implementation, the short pulse signal is generated using the standard logic cells as further shown and described in FIG. 1B and FIG. 2. The short pulse signal is used by the event collector 120 to collect all the event trigger signals. Moreover, the plurality of event detectors 118 are configured to produce a plurality of short pulse signals for the event collector 120. In addition, the long pulse signal is used by the corresponding shift register to store the timestamp addressing data for each pixel that is hit by the photon.

The apparatus 102 further includes the plurality of shift registers 110 that are configured to store timestamp addressing data for each pixel that is hit by the photon. In other words, the timestamp addressing data is realized by the plurality of shift registers 110. Moreover, an individual shift register is required to store the timestamp addressing data for each individual pixel that is hit by the photon. In an example, each shift register from the plurality of shift registers 110 is photon-event driven to store the timestamp addressing data. Moreover, each shift register from the plurality of shift registers is beneficial to reduce the processing speed of the apparatus 102. Further, reducing the processing speed results in less power-consumption, which is beneficial for the apparatus 102. In addition, the timestamp addressing data stored in the plurality of shift registers 110 reduces the circuit complexity of the pixel array 106. In accordance with an embodiment, each shift register from the plurality of shift registers 110 includes the plurality of digital D-flip-flops 128. In an example, each shift register from the plurality of shift registers 110 includes a series combination of the plurality of digital D-flip-flops 128. Moreover, an input signal is applied to a first D-flip-flop and an output is received from a last digital D-flip-flop from the plurality of digital D-flip-flops 128. Therefore, the input of the first digital D-flip-flop acts as an input of a corresponding shift register, and the output of the last digital D-flip-flop acts as an output of the corresponding shift register.

In accordance with an embodiment, the apparatus 102 further includes the event collector 120 that is configured to collect all the event trigger signals and generate an output signal to increment the address counter 122 after the storage of the timestamp value. In an implementation, the event collector 120 includes an array of cascaded digital OR-Gate with “n” number of input ports to collect all the event trigger signals, as further shown and described in FIG. 3. Moreover, the event collector 120 includes one output port (e.g., with an OR-logic) that is configured to generate the output signal to increment the address counter 122 after the storage of the timestamp value in the memory unit 116. Beneficially, the collection of all the event trigger signals and further generation of the output signal to increment the address counter 122 enables the apparatus 102 to count the number of generated output signals after the storage of the timestamp value. In accordance with an embodiment, the address counter 122 is configured to store the timestamp value in the memory unit 116 of the time-measuring circuit 108 and increment the memory address for storing the next timestamp value. In an implementation, the address counter 122 is triggered by the output signal of the event collector 120 as further described in FIG. 1B. In an example, the address counter 122 is configured to store a first timestamp value in the memory unit 116 of the time-measuring circuit 108 and increment the memory address, such as to store a second timestamp value. In addition, the address counter 122 includes the information related to the number of timestamps that are stored in the memory unit 116 that further reduces the readout process of the apparatus 102, which is beneficial to improve the performance of the apparatus 102.

The apparatus 102 further includes the time-measuring circuit 108 that is disposed outside the pixel array 106 and is configured to store a single timestamp value when any pixel in the pixel array 106 is hit by a photon at a given time. The light detector 104 triggers the timestamp value that is stored in the memory unit 116 of the time-measuring circuit 108. The time-measuring circuit 108 disposed outside the pixel array 106 is used to reduce the complexity and the power consumption of the apparatus 102. In accordance with an embodiment, the time-measuring circuit 108 includes the digital counter 114 and the memory unit 116. In an implementation, a digital counter value of the digital counter 114 is increased at every clock cycle that is received from a clock, as further shown, and described in FIG. 1B. Further, the number of pixels from the pixel array 106 hit by photons at the same clock-cycle generates the same timestamp values that are stored in the memory unit 116. The digital counter 114 (i.e., a high-speed counter) and the memory unit 116 of the time-measuring circuit 108 are beneficial to reduce the circuit complexity and processing speed for distance measurement with reduced power consumption. In such embodiments, the digital counter 114 is a binary counter or a gray-code counter. In an implementation, the digital counter 114 is the binary counter, and the digital counter value is increased at every clock cycle. In another implementation, the digital counter 114 is the grey code counter, and the digital counter value is changed at a time with every clock cycle. The binary counter or the grey-code counter is beneficial to provide an interactive and less complex structure for the apparatus 102. In such embodiments, the digital counter 114 is configured to have a parallel output with a pre-defined bit-width. In an implementation, the parallel output with the pre-defined bit-width depends on the requirement of the light detection and ranging (or LiDAR system) . Examples of such requirements include but are not limited to a distance to an obstacle to be measured, the accuracy of the distance measurement, clock frequency, and the like. In addition, the parallel output with the predefined bit-width represents the timestamp value that is stored in the memory unit 116. Beneficially as compared to the conventional approach, the parallel output with the pre-defined bit-width increases the processing speed of the digital counter 114 that further improves the performance of the apparatus 102.

In such embodiments, the memory unit 116 of the time-measuring circuit 108 is configured to have the parallel input/output ports 126 connected to the parallel output of the digital counter 114 with the pre-defined bit-width. In an example, each input/output port from the parallel input/output ports 126 acts as an input port during write-mode operation. In another example, each input/output port from the parallel input/output ports 126 acts as an output port during read-mode operation. Therefore, the parallel input/output ports 126 that are connected to the parallel output of the digital counter 114 with the pre-defined bit-width enable the apparatus 102 to perform multiple operations.

The apparatus 102 further includes the processing unit 112 to co-relate the timestamp value with the timestamp addressing data for each pixel for distance measurement or object detection. The processing unit 112 co-relates the timestamp value that is stored in the memory unit 116 of the time-measuring circuit 108 with the timestamp addressing data that is stored in the plurality of the shift registers 110. For example, the processing unit 112 co-relates a first timestamp value with a corresponding first timestamp addressing data. Similarly, the processing unit 112 co-related the subsequent timestamp values with the subsequent timestamp addressing data. Hence, the processing unit 112 enables the apparatus 102 to accurately co-relate the timestamp values with the associated timestamp addressing data for the accurate detection of the object and accurate measurement of the distance. Moreover, by virtue of co-relating the timestamp value with the timestamp addressing data, the processing unit 112 is able to identify which timestamp value belongs to which pixels.

The apparatus 102 is used for the light detection and ranging. The apparatus 102 includes the light detector 104 to detect the photons from the incident light. Further, the apparatus 102 includes the time-measuring circuit 108 that is disposed outside the pixel array 106 and stores the single timestamp value when any pixel in the pixel array 106 is hit by the photon. The time-measuring circuit 108 is beneficial to reduce the complexity and the power consumption of the apparatus 102. Further, the apparatus 102 includes the plurality of shift registers 110 to store timestamp addressing data for each pixel that is hit by the photon. Moreover, the processing unit 112 is used by the apparatus 102 to co-relate the timestamp value with the timestamp addressing data for each pixel that is beneficial for an accurate distance measurement or object detection. Therefore. the apparatus 102 is beneficial to improve the reliability, resolution, and the performance of the light detection and ranging systems.

FIG. 1B depicts a block diagram of an apparatus with timestamp-addressing-pixel for light detection and ranging, in accordance with an embodiment of the present disclosure. FIG. 1B is described in conjunction with elements from FIG. 1A. With reference to FIG. 1B there is shown a block diagram 100B of the apparatus 102 for light detection and ranging. The apparatus 102 includes an acquisition and a frame controller 130, a light source 132, a clock 134, timestamp values 136A to 136N, and a pixel unit cell 138. The apparatus 102 further includes the pixel array 106 that further includes a plurality of analog front-end circuits 124, such as from an analog front-end circuit 124A to an analog front-end (AFE) circuit 124N. The pixel array 106 further includes the plurality of event detectors 118, such as from an event detector 118A to an event detector 118N. The pixel array 106 further the plurality of shift registers 110, such as from a shift register 110A to a shift register 110N. There is further shown the time-measuring circuit 108, the digital counter 114, the memory unit 116, the event collector 120, and the address counter 122.

The acquisition and frame controller 130 may include suitable logic, circuitry, interfaces, or code that is configured to control the light source 132, and the clock 134. In an implementation, the acquisition and frame controller 130 is configured to control the light source 132 through a start-trigger (or fire) signal and control the clock 134 through a start clock signal or a stop clock signal. In an implementation, the acquisition and frame controller 130 correspond to the processing unit 112 of FIG. 1A.

The pixel unit cell 138 corresponds to a unit cell of the pixel array 106. The pixel unit cell 138 includes the analog front-end (AFE) circuit 124N, the event detector 118N, and the shift register 110N. Similarly, each pixel unit cell of the pixel array includes an analog front-end circuit, an event detector, and a shift register. For example, a first pixel unit cell includes the analog front-end circuit 124A, the event detector 118A, and the shift register 110A. Similarly, a second pixel unit cell includes an analog front-end circuit 124B, an event detector 118B, a shift register 110B, and the like.

Each timestamp value from the timestamp value 136A to the timestamp value 136N corresponds to a given time when any pixel in the pixel array 106 is hit by a photon at the given time. In an example, the timestamp value 136A corresponds to “time 0” when a pixel in the pixel array 106 is hit by the photon at zero time. In another example, a timestamp value 136B corresponds to “time 1” when another pixel in the pixel array 106 is hit by another photon at first time. Similarly, a timestamp value 136N corresponds to “time stamp xy” when yet another pixel in the pixel array 106 is hit by yet another photon at xy time.

The clock 134 may include suitable logic, circuitry, interfaces, or code that is configured to provide a clock signal to the digital counter 114 of the time-measuring circuit 108. The light source 132 is used in the apparatus 102 for emitting laser light and to release photons that strike the object and reflect. The light source 132 used in the apparatus 102 includes multiple light sources such as lasers with different sizes of aperture.

There is provided the acquisition and frame controller 130 that is configured to control the light source 132, and the clock 134. In addition, the light source 132 is configured to produce photons of light, and the light detector 104 with the pixel array 106 is configured to detect the photons from incident light. The pixel array 106 of the light detector 104 includes a plurality of pixel unit cells, such as the pixel unit cell 138, as shown in FIG. 1B. Therefore, the photons from the incident light are detected by each pixel unit cell of the pixel array 106. For example, the pixel unit cell 138 is configured to detect the photons from the incident light, and the AFE circuit 124N is configured to convert the current from the photon detected by the light detector 104 into the voltage and then to the trigger signal for the event detector 118N. Thereafter, the event detector 118N is configured to detect a trigger signal, which is generated when the pixel is hit by the photon in the light detector 104. The event detector 118N further generates a long pulse signal to act as input for the shift register 110N. Thereafter, the shift register 110N is configured to store the timestamp addressing data for each pixel that is hit by the photon. In addition, the analog front-end circuit 124A, the analog front-end circuit 124B, the event detector 118A, the event detector 118B, the shift register 110A, and the shift register 110B perform collectively in a similar way.

In an implementation, each event detector is configured to generate a short pulse signal to act as an input to the event collector 120. For example, the event detector 118A is configured to generate a short pulse signal to act as an input to the event collector 120, and similarly, N number of short pulse signals are generated for the event collector 120. Thereafter, the event collector 120 is configured to collect all the event trigger signals and generate an output signal to increment the address counter 122 after the storage of the timestamp values in the memory unit 116. In an example, the output signal is also received by the pixel array 106. Thereafter, the address counter 122 is configured to store the timestamp value in the memory unit 116 of the time-measuring circuit 108 and increment the memory address for storing the next timestamp value. In addition, the digital counter 114 of the time-measuring circuit 108 is configured to receive the signal from the clock 134. Thereafter, the parallel output with a pre-defined bit-width of the digital counter 114 is also received by the memory unit 116 of the time-measuring circuit 108 that is disposed outside the pixel array 106. The time-measuring circuit 108 is configured to store the single timestamp value when any pixel in the pixel array 106 is hit by the photon at a given time. In an implementation, the time-measuring circuit 108 is referred to as a single high-speed time-measuring circuit (HS-TMC) that is a pixel-independent circuit.

In an implementation, the apparatus 102 includes the timestamp-addressing pixels (TAP) because a plurality of pixels from the pixel array 106 generates the same timestamp values when photons hit the pixels at the same clock-cycle, such as the timestamp values 136A to 136N. Moreover, the time-measuring circuit 108 is realized with the digital counter 114 (i.e., high-speed counter) , and the memory unit 116 that is used to reduce the complexity and power consumption significantly. Further, the apparatus 102 utilizes dead-time values, a physical weakness of photon-detectors to reduce the processing speed of the light detection ranging. In an example, the dead-time values correspond to a time, where the light detector 104 (or photon-detector element) is blind and cannot detect further photons after a photon hit the light detector 104. In an implementation, single-photon-avalanche-diodes (SPADs) are often used as the light detector 104. Moreover, the dead-time values for the SPADs are in the range of 5 to 50 nanoseconds (ns) and the dead-time values depend on the size and parasitic capacitance of the SPAD. By virtue of considering the dead-time of the light detector 104, the processing speed of the apparatus 102 for the light detection ranging is significantly reduced, which results in an improved reliability and less power consumption.

In an embodiment, the time-measuring circuit 108 is configured to store two different timestamp values when the time interval between the two subsequent photons hitting two different pixels (or pixel unit cell) is greater than the clock period of the time-measuring circuit 108. In an implementation, if, the photon hits the first pixel unit cell, then the event detector 118A of the first pixel unit cell detects and generates two trigger signals, such as the short pulse signal and the long pulse signal. In an example, the short pulse signal is provided as a data input to the event collector 120, and the long pulse signal is provided as a data input to the shift register 110A. The long pulse signal further shifts the shift register 110A in the first pixel unit cell by one, such as with a logic “1” through the data input received from the long pulse signal of the event detector 118A. In an example, the logic “1” refers to the corresponding timestamp value stored in the memory unit 116. Finally, the output of the event collector 120 triggers the memory unit 116 to store the timestamp value in the memory unit 116 of the time-measuring circuit 108 and increments the address counter 122. In another implementation, if the photon hits the second pixel unit cell, then, the shift register 110B of the first pixel unit cell shifts with the logical “0” through the data input as there is no event from the first pixel unit cell. Similarly, the shift register 110B of the second pixel unit cell shifts by the logic “1” and further stores the next timestamp value in the memory unit 116 of the time-measuring circuit 108.

In an implementation, the memory size of the memory unit 116, the depth of each shift register from the plurality of the shift registers 110, and the bit-width of the timestamp values are dependent on the target use-case and on the requirements of the LiDAR system. In an implementation, if the photons hit different pixels at the same time, then, each pixel unit cell generates the photon-events and stores one timestamp value in the memory unit 116 of the time-measuring circuit 108. Further, the corresponding pixel unit cell shifts the shift register by the logic “1” . Similarly, if the two subsequent photon events are generated when two subsequent photons hit the two different pixel unit cells, then the storage of the timestamp value is dependent on the resolution (i.e., the clock frequency) of the time-measuring circuit 108. However, if the time between the two subsequent photon events is smaller than the clock period, then only one timestamp value is stored and if the time between the two subsequent photon events is higher than the clock period, then both timestamp values will be stored in the memory unit 116 of the time-measuring circuit 108.

FIG. 2 is an illustration that depicts an event detector of a pixel unit cell, in accordance with an embodiment of the present disclosure. FIG. 2 is shown in conjunction with elements from FIG. 1A, and FIG. 1B. With reference to FIG. 2, there is shown an illustration 200 that depicts the event detector 118N of the pixel unit cell 138. The pixel unit cell 138 includes the analog front-end (AFE) circuit 124N from the plurality of the analog front-end circuits 124. The pixel unit cell 138 further includes the event detector 118N from the plurality of the plurality of event detectors 118. There is further shown the shift register 110N from the plurality of shift registers 110. There is further shown the event detector 118N from the plurality of the event detectors118. The event detector 118N further includes a delay logic 202, an exclusively-OR (XOR) logic 204, AND logic 206, and a buffer (BUF) logic 208.

In an implementation, the event detector 118N in the pixel unit cell 138 receives the input signal (e.g., voltage) from the AFE circuit 124N. Further, the input signal received from the AFE circuit 124N is provided to the delay logic 202 of the event detector 118N. In an example, the delay logic 202 is configured to produce a delay in the input signal received from the AFE circuit 124N. Furthermore, the input signal received from the AFE circuit 124N is provided to the XOR logic 204 and the output of the delay logic 202 is also provided to the XOR logic 204. In an example, the XOR logic 204 is configured to perform a logical operation. Thereafter, the input received from the AFE circuit 124N is also provided to the AND logic 206, and the output of the XOR logic 204 is also provided to the AND logic 206. In addition, the BUF logic 208 also receives the input from the AFE circuit 124N. Thereafter, the event detector 118N is configured to generate a short pulse signal to act as an input to the event collector 120 and a long pulse signal to act as input to the corresponding shift register. In an implementation, the BUF logic 208 generates the short pulse signal to act as an input to the event collector 120 and the AND logic 206 generates the long pulse signal to act as input to the shift register 110N. In another implementation, the AND logic 206 generates the short pulse signal to act as an input to the event collector 120 and the BUF logic 208 generates the long pulse signal to act as input to the shift register 110N. In addition, each event detector from the plurality of event detectors 118 is configured to perform in a similar way to produce N-number of short pulse signals that are further received by the event collector 120, as further shown and described in FIG. 3.

FIG. 3 is an illustration that depicts an event collector of an apparatus, in accordance with an embodiment of the present disclosure. FIG. 3 is shown in conjunction with elements from FIG. 1, FIG. 1B, and FIG. 2. With reference to FIG. 3, there is shown an illustration 300 that depicts the event collector 120 of the apparatus 102. There is further shown the address counter 122, and the pixel unit cell 138. Further, the event collector 120 includes a plurality of OR logic, such as a first OR logic 302, a second OR logic 304, a third OR logic 306, and the like. Moreover, the pixel unit cell 138 includes the analog front-end (AFE) circuit 124N from the plurality of analog front-end circuits 124. Further, the pixel unit cell 138 includes the event detector 118N from the plurality of the event detectors 118. There is further shown the shift register 110N from the plurality of shift registers 110.

In an implementation, each event detector from the plurality of event detectors 118 is configured to produce N-number of short pulse signals that are further received by the event collector 120. For example, the N-number of short pulse signals, such as a first short pulse signal (or “input 1) , a second short pulse signal (or “input 2) , and up to an N-1 _th short pulse signal (or “input N-1” ) , and N _th short pulse signal (or “input N) are received by the event collector 120, as shown in FIG. 3. In an example, the first short pulse signal and the second short pulse signal are received by the first OR logic 302. Similarly, other short pulse signals are received by the subsequent OR logic, such as the N-1 _th short pulse signal, and the N _th short pulse signal are received by the second OR logic 304. Thereafter, the output of each OR logic is received by the third OR logic 306.

Finally, the output of the event collector 120 is generated by the third OR logic 306 that triggers the memory unit 116 to store the timestamp value in the memory unit 116 of the time-measuring circuit 108 and increments the address counter 122. In an implementation, the output of the event collector 120 is also provided to the pixel unit cell 138.

FIG. 4 is an illustration that depicts an interconnection of a pixel unit cell and an address incrementor, in accordance with an embodiment of the present disclosure. FIG. 4 is shown in conjunction with elements from FIG. 1, FIG. 1B, FIG. 2, and FIG. 3. With reference to FIG. 4, there is shown an illustration 400 that depicts a single-photon-avalanche-diodes (SPAD) event 402, a first pixel unit cell (PUC) 404, a second PUC 406, a third PUC 408, a fourth PUC 410, and an address incrementer 412.

In an implementation, the first PUC 404, the second PUC 406, the third PUC 408, and the fourth PUC 410 are included by the pixel array 106 of the light detector 104. Moreover, each of the first PUC 404, the second PUC 406, the third PUC 408, and the fourth PUC 410 is configured to detect the photons from incident light. Thereafter, an output signal from each of the first PUC 404, the second PUC 406, the third PUC 408, and the fourth PUC 410 is received by the SPAD event 402. In an example, the SPAD event 402 is used by the apparatus 102 to detect a trigger signal, which is generated when a pixel is hit by the photon in the light detector 104. Moreover, the output of the SPAD event 402 is provided as input to the address incrementer 412. In an example, the address incrementer 412 corresponds to the address counter 122 of FIG. 1A. Furthermore, the output of the address incrementer 412 is provided to the plurality of pixel unit cells such as the first PUC 404, the second PUC 406, the third PUC 408, and the fourth PUC 410. The address incrementer 412 is used by the apparatus 102 to count the number of generated output signals after the storage of the timestamp value.

FIG. 5 is a graphical representation that illustrates clock cycles of timestamp addressing data for a pixel array, in accordance with an embodiment of the present disclosure. FIG. 5 is shown in conjunction with elements from FIG. 1, FIG. 1B, FIG. 2, FIG. 3, and FIG. 4. With reference to FIG. 5, there is shown a graphical representation 500 that illustrates timestamp pixel data for the pixel array 106. The graphical representation 500 illustrates different clock cycles, such as an incident light clock cycle 502, an acquisition phase clock cycle 504, a first pixel event clock cycle 506, a second pixel event clock cycle 508, a third pixel event clock cycle 510, Nth pixel event clock cycle 512, a timestamp data clock cycle 514, an address increment clock cycle 516.

The first line in the graph represents the incident light clock cycle 502 that is detected by the pixel array 106 of the light detector 104 after reflecting from an object. Further, the incident light clock cycle 502 is used for the acquisition phase clock cycle 504 based on the photons detection. In an example, the acquisition phase clock cycle 504 is referred to as a photon detection phase. In an implementation, the acquisition and frame controller 130 is used to produce the acquisition phase clock cycle 504. In addition, a plurality of pixel event clock cycles are generated, such as the first pixel event clock cycle 506, the second pixel event clock cycle 508, the third pixel event clock cycle 510 to the Nth pixel event clock cycle 512. In an implementation, after the acquisition phase clock cycle 504, the timestamp values are stored in the memory unit 116, as shown by the timestamp data clock cycle 514. Thereafter, the address counter 122 is needed to increment the memory address after storing the timestamp value in the memory unit 116, as shown by the address increment clock cycle 516. In an example, the address increment clock cycle 516 is used to increment the address counter that is beneficial to improve the performance of the apparatus 102.

Modifications to embodiments of the present disclosure described in the foregoing are possible without departing from the scope of the present disclosure as defined by the accompanying claims. Expressions such as "including" , "comprising" , "incorporating" , "have" , "is" used to describe and claim the present disclosure are intended to be construed in a non-exclusive manner, namely allowing for items, components or elements not explicitly described also to be present. Reference to the singular is also to be construed to relate to the plural. The word "exemplary" is used herein to mean "serving as an example, instance or illustration" . Any embodiment described as “exemplary” is not necessarily to be construed as preferred or advantageous over other embodiments or to exclude the incorporation of features from other embodiments. The word "optionally" is used herein to mean "is provided in some embodiments and not provided in other embodiments" . It is appreciated that certain features of the present disclosure, which are, for clarity, described in the context of separate embodiments, may also be provided in combination in a single embodiment. Conversely, various features of the invention, which are, for brevity, described in the context of a single embodiment, may also be provided separately or in any suitable combination or as suitable in any other described embodiment of the disclosure.

Claims

An apparatus (102) for light detection and ranging comprising:

a light detector (104) with a pixel array (106) configured to detect photons from incident light;

a time-measuring circuit (108) , disposed outside the pixel array (106) , configured to store a single timestamp value when any pixel in the pixel array (106) is hit by a photon at a given time;

a plurality of shift registers (110) configured to store timestamp addressing data for each pixel that is hit by a photon; and

a processing unit (112) to co-relate the timestamp value with the timestamp addressing data for each pixel for distance measurement or object detection.
The apparatus (102) of claim 1, wherein the time-measuring circuit (108) comprises a digital counter (114) and a memory unit (116) .
The apparatus (102) of claim 2, further comprising a plurality of event detectors (118) configured to detect a trigger signal, generated when a pixel is hit by a photon in the light detector (104) .
The apparatus (102) of claim 3, further comprising an event collector (120) configured to collect all the event trigger signals and generate an output signal to increment an address counter (122) after the storage of the timestamp value.
The apparatus (102) of claim 4, wherein each of the plurality of event detectors (118) is configured to generate a short pulse signal to act as an input to the event collector (120) and a long pulse signal to act as input to the corresponding shift register.
The apparatus (102) of claim 4 or 5, wherein the address counter (122) is configured to store the timestamp value in the memory unit (116) of the time-measuring circuit (108) and increment the memory address for storing the next timestamp value.
The apparatus (102) of any of claims 3 to 6, further comprising a plurality of analog front-end circuits (124) configured to convert the current from a photon detected by the light detector (104) into a voltage and then to the trigger signal for the event detector.
The apparatus (102) of any preceding claim, wherein the time-measuring circuit (108) is configured to store two different timestamp values when the time interval between the two subsequent photons hitting two different pixels is greater than the clock period of the time-measuring circuit (108) .
The apparatus (102) of any of claims 2 to 8, wherein the digital counter (114) is a binary counter or a gray-code counter.
The apparatus (102) of any of claims 2 to 9, wherein the digital counter (114) is configured to have a parallel output with a pre-defined bit-width.
The apparatus (102) of claim 10, wherein the memory unit (116) is configured to have parallel input/output ports (126) connected to the parallel output of the digital counter (114) with the pre-defined bit-width.
The apparatus (102) of any of preceding claims, wherein each of the plurality of shift registers (110) comprises a plurality of digital D-Flip-Flops (128) .