CN110401453B - Low delay LDPC decoder and decoding method thereof - Google Patents
Low delay LDPC decoder and decoding method thereof Download PDFInfo
- Publication number
- CN110401453B CN110401453B CN201810374178.0A CN201810374178A CN110401453B CN 110401453 B CN110401453 B CN 110401453B CN 201810374178 A CN201810374178 A CN 201810374178A CN 110401453 B CN110401453 B CN 110401453B
- Authority
- CN
- China
- Prior art keywords
- variable node
- variable
- node memory
- memory
- ldpc
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 238000000034 method Methods 0.000 title claims abstract description 67
- 238000012795 verification Methods 0.000 claims abstract description 32
- 238000004364 calculation method Methods 0.000 claims description 90
- 239000011159 matrix material Substances 0.000 claims description 76
- 230000005540 biological transmission Effects 0.000 claims description 10
- 230000009977 dual effect Effects 0.000 claims description 7
- 230000008569 process Effects 0.000 abstract description 39
- 238000012545 processing Methods 0.000 description 10
- 238000010586 diagram Methods 0.000 description 8
- 238000012546 transfer Methods 0.000 description 7
- 238000012937 correction Methods 0.000 description 6
- 230000004044 response Effects 0.000 description 6
- 239000000470 constituent Substances 0.000 description 3
- 239000007787 solid Substances 0.000 description 3
- 230000008901 benefit Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000009471 action Effects 0.000 description 1
- 230000003044 adaptive effect Effects 0.000 description 1
- 238000007792 addition Methods 0.000 description 1
- 238000012217 deletion Methods 0.000 description 1
- 230000037430 deletion Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
- 238000005457 optimization Methods 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
- H03M13/1111—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
Landscapes
- Physics & Mathematics (AREA)
- Probability & Statistics with Applications (AREA)
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Mathematical Physics (AREA)
- Error Detection And Correction (AREA)
Abstract
The application relates to a low density parity check code (Low Density Parity Check Code, LDPC) decoding method, comprising: transmitting the variable node stored in the first variable node memory to a computing unit to generate a new value of the variable node; transmitting the variable nodes stored in the second variable node memory to a verification unit to verify the legitimacy of the LDPC code words formed by the variable nodes; ending iterative decoding if the formed LDPC code word is legal; if the formed LDPC code word is illegal, the variable node new value generated by the calculating unit updates the first variable node memory and the second variable node memory. Since the process of reading out the data for checking whether the legal LDPC codeword is obtained from the second variable node memory is performed simultaneously with the process of reading out the data for updating the variable nodes for iterative decoding from the first variable node memory, the delay of LDPC decoding is reduced.
Description
Technical Field
The present application relates to a low density parity check code (Low Density Parity Check Code, LDPC) decoding method, and more particularly, to optimization of a minimum sum algorithm-based LDPC decoding process.
Background
The LDPC code is an error correction code, and compared with other error correction codes, the LDPC code has the characteristics of strong error correction capability and fast convergence speed under the same code rate, so that the LDPC code is the optimal error correction code in the field of SSD (solid state drive ) controllers in the present stage.
The LDPC code is a binary block code, and an ultra-sparse matrix is adopted as a check matrix. Non-zero elements in each row (column) of the check matrix are rare. For any legitimate codeword V, the product of codeword V and the check matrix H is zero. LDPC codes are described in the prior art by Tanner graphs. The Tanner graph is composed of two types of nodes, one is a variable node and the other is a check node. Each variable node corresponds to a bit of the codeword and each check node corresponds to a row of the check matrix H. The connection between the variable node and the check node corresponds to a "1" in the check matrix. Fig. 1 is a Tanner graph of an LDPC code. In the iterative decoding process, the decoder performs iterative decoding by using the constraint relation between the check nodes and the variable nodes. The input of each variable node is the log-likelihood ratio corresponding to the received sequence and the output of the last iteration of the check node; the output of the variable node is then sent to the corresponding check node via the "link" and decoded using the constraint relationship of the check node. In this process, the output of one node becomes the input of the other node, and the "connection" corresponding to the non-zero element in the matrix becomes the channel for the two nodes to exchange information. A decoding method for LDPC codes is provided in chinese patent application 2016108617916 (patent name LDPC decoding method and apparatus), which is incorporated herein by reference in its entirety.
Common LDPC decoding algorithms include: belief propagation algorithms (Belief Propagation, BP), minimum Sum algorithms (Min-Sum) and Bit inversion algorithms (Bit Flip), etc. And the minimum sum algorithm and the improved algorithm based on the minimum sum algorithm are widely adopted in the SSD controller field due to the fact that the hardware time is simple and the error correction performance is good enough.
The min-sum algorithm includes a number of major steps. Firstly, initializing a variable node and a check node, wherein the initial value of the variable node is, for example, a value read from a storage medium, and the initial value of the check node is obtained according to a check matrix used. In one round of LDPC iterative decoding, check nodes and variable nodes are updated. The updated variable nodes and check nodes will be used in the next round of decoding. A check is also performed on the variable nodes to identify if they are correct codewords. If the correct code word is obtained, stopping the decoding process.
The AN-MS (Adaptive Normalize Min-Sum algorism) Algorithm is AN iterative decoding Algorithm based on a minimum Sum Algorithm improvement. The LDPC decoding algorithm has strong error correction capability and is easier to realize by hardware. The core decoding process of AN-MS algorithm includes two parts: variable node processing and check node processing. Variable node processing and check node processing need to be completed in one iteration. If the decoding result is correct after iteration, the decoding is finished, otherwise, the next iteration is started until the decoding is successful or the preset maximum iteration number is exceeded.
For a detailed description of the AN-MS algorithm, see "Wu X, song Y, cui L, et al adaptive-normalized min-sum algorithm [ C ],2010 2nd International Conference on Future Computer and Communication.2010 ], which is incorporated herein by reference in its entirety.
The LDPC decoder implements an LDPC decoding algorithm. Fig. 2 shows a block diagram of a prior art LDPC decoder.
The controller 210 controls the LDPC decoding process, controls cooperation among the components of the decoder, including loading of a check matrix, writing and reading of data of each memory cell, controls the iterative decoding process, identifies decoding termination conditions, and the like.
The calculating unit 220 is used for processing the calculation in the decoding process, and calculating new values of the variable nodes and the check nodes according to the operation indicated by the decoding algorithm. The calculation unit 220 has a plurality of calculation units to calculate in parallel. A variable node memory 230 for storing variable node information; check node memory 240 for storing check nodes and temporary variable memory 250 for storing temporary information, such as symbols, minimums, etc., generated during calculation by the calculation unit. The checking unit 260 is used for checking whether the variable node is a legal LDPC codeword.
Fig. 3 shows a decoding flow of an LDPC decoder of the prior art.
After decoding of the codeword is started, variable node memory 230 is initialized with the codeword to be decoded and check node memory 240 is initialized with the check matrix under the direction of controller 210 (310). Variable nodes are acquired from the variable node memory 230 (320), and the check unit 260 checks whether the acquired variable nodes constitute a legal LDPC codeword (330). If the variable nodes constitute legal LDPC codewords (340), decoding is finished, and the variable nodes are output as decoding results of the LDPC decoder (360). If the variable nodes do not already constitute a legal LDPC codeword (340), the calculation unit 220 provides the variable nodes and the check nodes to the calculation unit 220 for one iteration decoding (350). In one iterative decoding process, the calculation unit 220 generates new values of the variable node and the check node, and the new values are used to update the variable node memory and the check node memory. And the verification unit 260 acquires the variable nodes in the variable node memory again and performs verification.
Fig. 4 shows a timing diagram of a decoding process of the prior art LDPC decoder.
In fig. 4, the rightward direction is the time lapse direction. The example of 2 rows of check matrix is illustrated in fig. 4. In one iterative decoding process, for each row of the check matrix, variable nodes corresponding to the row of the check matrix are acquired from the variable node memory 230 and calculated by the calculation unit 220. Fig. 4 is presented around access to variable node memory 230.
In the initialization phase (see also fig. 3, 310), variable nodes are stored to variable node memory 230 (410). Next, the variable node is read out from the variable node memory 230 (420) and supplied to the verification unit 260. Optionally, the transfer of variable nodes from variable node memory 230 to check unit 260 (420) occurs before initialization of variable node memory 230 is complete to reduce the delay of LDPC decoding. For example, the variable nodes include 4096, and after a part of the variable nodes is stored in the variable node memory 230, data transfer from the variable node memory 230 to the check unit 260 is started to transfer a part of the variable nodes that have been written to the variable node memory 230.
The check unit 260 checks the variable nodes (422), reads out the variable nodes again from the variable node memory 230 in response to the check result (failure), and transfers the variable nodes corresponding to the first row of the check matrix to the calculation unit 220 (430). The computing unit generates updated variable nodes corresponding to the first row of the check matrix and writes back to the variable node memory 230 (432). The process (432) of writing the updated variable nodes to the variable node memory 230 thus occurs after the variable nodes of the same check matrix are transmitted to the calculation unit 220 (430).
After transmitting the variable nodes corresponding to the first row of the check matrix to the computing unit 220 (430), the variable nodes corresponding to the second row of the check matrix are also transmitted to the computing unit 220 (440), and the computing unit 220 generates updated variable nodes corresponding to the second row of the check matrix and writes back to the variable node memory 230 (442). The first iteration decoding is completed.
The variable nodes are then transmitted to a verification unit 260 (450) to identify whether the variable nodes constitute a legitimate LDPC codeword. If the variable node is still not a legal LDPC codeword, the controller 210 starts the second round of iterative decoding.
The second round of iterative decoding is the same as the first round of iterative decoding. Variable nodes corresponding to a first row of the check matrix are provided from variable node memory 230 to calculation unit 220 (460), and variable nodes corresponding to a second row of the check matrix are provided to calculation unit 220 (470). Upon receiving variable nodes corresponding to the first row of the check matrix, the computing unit 220 updates the variable nodes and writes the updated variable nodes back to the variable node memory 230 (462); upon receiving the variable nodes corresponding to the second row of the check matrix, the computing unit 220 updates the variable nodes and writes the updated variable nodes back to the variable node memory 230 (472). By way of example, the check matrix includes 2 rows, and thus the further round of iterative decoding ends.
The variable nodes are then transmitted to the verification unit 260 (480) to identify whether the variable nodes constitute a legal LDPC codeword.
Disclosure of Invention
The present application is directed to an LDPC decoding method or an LDPC decoder to further reduce delay introduced by the LDPC decoder.
According to a first aspect of the present application, there is provided a first LDPC decoding method according to the first aspect of the present application, comprising: transmitting the variable node stored in the first variable node memory to a computing unit to generate a new value of the variable node; transmitting the variable nodes stored in the second variable node memory to a verification unit to verify the legitimacy of the LDPC code words formed by the variable nodes; ending iterative decoding if the formed LDPC code word is legal; if the formed LDPC code word is illegal, the variable node new value generated by the calculating unit updates the first variable node memory and the second variable node memory.
According to the first LDPC decoding method of the first aspect of the present application, the variable nodes stored in the first variable node memory are transmitted to the calculation unit and the variable nodes stored in the second variable node memory are transmitted to the verification unit simultaneously.
According to the first LDPC decoding method of the first aspect of the present application, in the initialization phase, the first variable node memory and the second variable node memory are initialized with the codeword to be decoded, and the check node memory is initialized with the check matrix.
A third LDPC decoding method according to the first aspect of the present application includes: and transmitting the check nodes stored in the check node memory to a computing unit, and generating a new value of the variable node and a new value of the check node by iterative decoding according to the check nodes and the variable node.
According to one of the first to fourth LDPC decoding methods of the first aspect of the present application, in response to the constructed LDPC codeword being legal, updating of the first variable node memory and the second variable node memory with the variable node new value is prevented.
According to one of the first to fifth LDPC decoding methods of the first aspect of the present application, in response to the constituent LDPC codeword being legal, if the calculation unit is decoding calculation at this time, the decoding calculation is terminated, and the already obtained decoding result is discarded.
According to the third or fourth LDPC decoding method of the first aspect of the present application, in a first sub-stage of one round of iterative decoding, variable nodes of a first row associated with a check matrix stored in a first variable node memory are transmitted to a calculation unit, and new values of the variable nodes of the first row are generated; and if the check unit verifies that the formed LDPC code word is illegal, updating the first variable node memory and the second variable node memory through the new variable node value of the first row.
The seventh LDPC decoding method according to the first aspect of the present application, wherein the variable nodes provided to the check unit are all variable nodes of the codeword to be decoded.
According to the seventh LDPC decoding method of the first aspect of the present application, the transmission of the variable nodes stored in the first variable node memory in association with the first row of the check matrix to the calculation unit and the transmission of the variable nodes stored in the second variable node memory to the check unit are performed simultaneously.
According to the seventh LDPC decoding method of the first aspect of the present application, in the second sub-stage of one round of iterative decoding, variable nodes of the second row associated with the check matrix stored in the first variable node memory are transmitted to the calculation unit, and new values of the variable nodes of the second row are generated; updating the first variable node memory and the second variable node memory by the new variable node value of the second row; until all the variable nodes associated with all the rows of the check matrix generate corresponding new variable node values, and after the first variable node memory and the second variable node memory are updated by the corresponding new variable node values, the iterative decoding is finished.
According to a tenth LDPC decoding method according to the first aspect of the present application, wherein after the variable nodes associated with the first row of the check matrix are transferred completely from the first variable node memory to the calculation unit in the first sub-stage, the reading out of the variable nodes associated with the second row of the check matrix from the first variable node memory in the second sub-stage is started to be transferred to the calculation unit.
According to the tenth LDPC decoding method of the first aspect of the present application, wherein the new values of the first row variable nodes associated with the check matrix are written into the first variable node memory by the calculation unit and the second row variable nodes associated with the check matrix are read out from the first variable node memory and transmitted to the calculation unit for parallel processing.
According to the tenth LDPC decoding method of the first aspect of the present application, as the part of the new value of the variable node associated with the last row of the check matrix is written into the first variable node memory, the updated variable node transmission from the second variable node memory to the check unit in the next iteration decoding is started.
According to the thirteenth LDPC decoding method of the first aspect of the present application, new values of variable nodes associated with the last row of the check matrix are all written into the first variable node memory, and updated variable nodes stored in the second variable node memory are all transferred to the check unit in the next iteration decoding.
According to the tenth LDPC decoding method of the first aspect of the present application, as the part of the new value of the variable node associated with the last row of the check matrix is written into the first variable node memory, the updated variable node transmission from the first variable node memory to the calculation unit in the next iteration decoding is started.
According to a second aspect of the present application, there is provided a first LDPC decoder according to the second aspect of the present application, comprising: the system comprises a first variable node memory, a second variable node memory, a calculation unit, a verification unit and a controller; the controller instructs to acquire variable nodes from the first variable node memory and transmit the variable nodes to the computing unit to generate new values of the variable nodes, and instructs to acquire variable nodes from the second variable node memory and transmit the variable nodes to the checking unit to check the legitimacy of the variable nodes forming the LDPC codeword; if the formed LDPC code word is legal, the controller indicates that iterative decoding is finished; if the formed LDPC code word is illegal, the controller instructs the calculation unit to write the new value of the generated variable node into the first variable node memory and the second variable node memory.
According to the first LDPC decoder of the second aspect of the present application, the controller instructs the transmission of the variable node stored in the first variable node memory to the calculation unit and the transmission of the variable node stored in the second variable node memory to the verification unit to be performed simultaneously.
The first LDPC decoder according to the second aspect of the present application further includes: and the controller instructs to acquire the check node from the check node memory and transmit the check node to the computing unit, and the computing unit generates a new value of the variable node and a new value of the check node according to iterative decoding of the check node and the variable node.
According to the third LDPC decoder of the second aspect of the present application, in the initialization phase, the controller controls the first variable node memory and the second variable node memory to be initialized with the codeword to be decoded, and the check node memory to be initialized with the check matrix.
According to one of the first to fourth LDPC decoders of the second aspect of the present application, the plurality of the calculation units are plural, and the plurality of the calculation units calculate in parallel.
One of the first to fourth LDPC decoders according to the second aspect of the present application, wherein the first variable node memory is a dual port memory having a read port coupled to the computation unit to provide the variable node to the computation unit; the write port of which is coupled to the calculation unit to write the variable node new value generated by the calculation unit to the first variable node memory.
A sixth LDPC decoder according to the second aspect of the present application, wherein the read port and the write port of the first variable node memory may simultaneously transmit data.
According to one of the first to fourth LDPC decoders of the second aspect of the present application, the check node memory is a dual port memory.
One of the first to fourth LDPC decoders according to the second aspect of the present application, wherein the LDPC decoder further comprises: a temporary variable memory for storing temporary information generated during the calculation of the calculation unit, the temporary variable memory being coupled to the calculation unit.
According to one of the first to fourth LDPC decoders of the second aspect of the present application, the LDPC decoder, wherein the second variable node memory is a dual port memory, a read port of which is coupled to the verification unit to provide the variable node to the verification unit; the write port of which is coupled to the calculation unit to write the variable node new value generated by the calculation unit to the second variable node memory.
According to the tenth LDPC decoder of the second aspect of the present application, the first variable node memory and the second variable node memory can simultaneously transmit the variable nodes outwards.
According to the first LDPC decoder of the second aspect of the present application, the controller prevents updating of the first variable node memory and the second variable node memory with the variable node new value in response to the constituent LDPC codeword being legal.
According to the first LDPC decoder of the second aspect of the present application, in response to the constituent LDPC codeword being legal, if the calculation unit is decoding calculation at this time, the controller controls the calculation unit to terminate the decoding calculation and discard the already obtained decoding result.
A first LDPC decoder according to the second aspect of the present application, wherein in a first sub-stage of one round of iterative decoding, the controller instructs a variable node associated with a first row of a check matrix to be acquired from a first variable node memory and transmitted to a calculation unit, generating a new value of the variable node of the first row; if the check unit verifies that the formed LDPC code word is illegal, the controller indicates to update the first variable node memory and the second variable node memory with the new variable node value of the first row.
A fourteenth LDPC decoder according to the second aspect of the present application, wherein the controller instructs the variable nodes provided to the check unit by the second variable node memory to be all the variable nodes of the codeword to be decoded.
A fourteenth LDPC decoder according to the second aspect of the present application, wherein the controller instructs the variable node acquiring the first row associated with the check matrix from the first variable node memory to be transmitted to the calculation unit and the variable node acquiring the variable node from the second variable node memory to be transmitted to the check unit to be simultaneously performed.
A fourteenth LDPC decoder according to the second aspect of the present application, wherein in a second sub-stage of one round of iterative decoding, the controller instructs a variable node of a second row associated with the check matrix to be acquired from the first variable node memory and transmitted to the calculation unit, and generates a new value of the variable node of the second row; the controller instructs the variable node new value of the second row to update the first variable node memory and the second variable node memory; until all the variable nodes associated with all the rows of the check matrix generate corresponding new variable node values, and after the first variable node memory and the second variable node memory are updated by the corresponding new variable node values, the iterative decoding is finished.
According to a seventeenth LDPC decoder of the second aspect of the present application, after the variable nodes associated with the first row of the check matrix are completely transferred from the first variable node memory to the calculation unit in the first sub-stage, the controller instructs to start reading out the variable nodes associated with the second row of the check matrix from the first variable node memory in the second sub-stage and transferring the variable nodes to the calculation unit.
According to a seventeenth LDPC decoder of the second aspect of the present application, the controller controls writing of new values of variable nodes associated with a first row of the check matrix to the first variable node memory by the calculation unit and reading out of variable nodes associated with a second row of the check matrix from the first variable node memory for transmission to the calculation unit for parallel processing.
A seventeenth LDPC decoder according to the second aspect of the present application, wherein the controller instructs to turn on updated variable node transmissions from the second variable node memory to the check unit in a next round of iterative decoding as a portion of the variable node new values associated with the last row of the check matrix are written to the first variable node memory.
According to a twentieth LDPC decoder of the second aspect of the present application, new variable node values associated with a last row of the check matrix are all written into the first variable node memory, and the controller instructs all of the updated variable nodes stored in the second variable node memory to be transferred to the check unit in a next iteration of decoding.
A seventeenth LDPC decoder according to the second aspect of the present application, wherein the controller instructs to turn on the updated variable node transmission from the first variable node memory to the calculation unit in the next round of iterative decoding as a part of the variable node new value associated with the last row of the check matrix is written to the first variable node memory.
According to a third aspect of the present application there is provided a first memory controller according to the third aspect of the present application comprising an LDPC decoder as claimed in any one of the preceding claims.
According to the LDPC decoding process provided by the application, the process of reading data from the second variable node memory for checking whether the legal LDPC code word is obtained is performed simultaneously with the process of reading data from the first variable node memory for updating the variable node by iterative decoding, so that the delay of LDPC decoding is shortened. In the LDPC decoding process, the first part of the variable node is updated simultaneously with the process of reading the second part of the variable node from the first variable node memory, thereby further shortening the delay of LDPC decoding. And updating the second portion of the variable node during the LDPC decoding process concurrently with reading the variable node from the second variable node memory for verification, thereby further reducing the delay of the LDPC decoding.
Drawings
The application, as well as a preferred mode of use and further objectives and advantages thereof, will best be understood by reference to the following detailed description of illustrative embodiments when read in conjunction with the accompanying drawings, wherein:
FIG. 1 is a Tanner graph of an LDPC code;
FIG. 2 shows a block diagram of a prior art LDPC decoder;
FIG. 3 illustrates a decoding flow of a prior art LDPC decoder;
FIG. 4 shows a timing diagram of a decoding process of a prior art LDPC decoder;
FIG. 5 illustrates a block diagram of an LDPC decoder according to an embodiment of the present application;
FIG. 6 illustrates a decoding flow of an LDPC decoder according to an embodiment of the present application;
fig. 7 illustrates a timing diagram of a decoding process of an LDPC decoder according to an embodiment of the present application.
Detailed Description
Embodiments of the present application are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the application.
Fig. 5 illustrates a block diagram of an LDPC decoder according to an embodiment of the present application.
The controller 510 is coupled to the various components of the LDPC decoder, controls the LDPC decoding process, controls the cooperation among the various components of the LDPC decoder, including loading of the check matrix, writing and reading of data of the various memory cells, controls the iterative decoding process, identifies decoding termination conditions, and the like.
The calculation unit 520 is used for processing the calculation in the decoding process, and calculating new values of the variable nodes and the check nodes according to the operation indicated by the LDPC decoding algorithm. Alternatively, there are a plurality of calculation units 520 to calculate in parallel. A first variable node memory 530 for storing variable node information. The first variable node memory 530 is a dual port memory, including a read port and a write port, which can simultaneously transmit data. Check node memory 540 for storing check nodes. Optionally, the check node memory 540 is also a dual port memory. The temporary variable memory 55 is used to store temporary information, such as symbols, minimum values, etc., generated during the calculation by the calculation unit. Check unit 560 is used to check whether the variable node is a legitimate LDPC codeword.
The LDPC decoder according to the embodiment of fig. 5 further includes a second variable node memory 570. The second variable node memory 570 includes two ports, a read port and a write port. The second variable node memory 570 is also used to store variable nodes. The variable nodes stored in the second variable node memory 570 are copies of the variable nodes stored in the first variable node memory 530. For example, for any update to the first variable node memory 530 (initializing or updating variable nodes), the same update is also applied to the second variable node memory 570. The second variable node memory 570 is equivalent to adding a second read port to the first variable node memory 530, so that the first variable node memory 530 and the second variable node memory 570 can simultaneously transmit variable nodes outwards.
According to the embodiment of fig. 5, the read port of the first variable node memory 530 is coupled to the calculation unit 520 to provide the variable nodes to the calculation unit 520. The write port of the first variable node memory 530 is coupled to the calculation unit 520, so that the calculation unit 520 writes the updated variable node to the first variable node memory 530 through the write port. The read port of the second variable node memory 570 is coupled to the check unit 560 to provide the variable nodes to the check unit 560. The write port of the second variable node memory 570 is coupled to the calculation unit 520 such that the calculation unit 520 writes the updated variable node to the second variable node memory 570 also through the write port.
Fig. 6 illustrates a decoding flow of an LDPC decoder according to an embodiment of the present application.
After decoding of the codeword is started, the first variable node memory 530 and the second variable node memory 570 are initialized with the codeword to be decoded and the check node memory 540 is initialized with the check matrix under the direction of the controller 510 (610). While the variable node is acquired from the first variable node memory 530 and transferred to the calculation unit 520 (620), the variable node is acquired from the second variable node memory 570 and transferred to the verification unit 560 (622), and the verification unit 560 checks whether the acquired variable node constitutes a legal LDPC codeword.
The calculation unit 520 performs iterative decoding according to the LDPC decoding algorithm, generating new values of the obtained variable nodes (and check nodes) (630). And the check result of the check unit 560 indicates whether the obtained variable node constitutes a legal LDPC codeword (660). If the check unit 560 indicates that the obtained variable nodes constitute legal LDPC codewords (check pass), the new values of the variable nodes generated by the calculation unit 520 are not updated to the first variable node memory 530 (and the second variable node memory 570) under the action of the controller 510, and the decoding process is ended, and the variable results (also stored in the first variable node memory 530 and/or the second variable node memory 570) obtained by the check unit 560 are taken as decoding results. Alternatively, if the verification unit 560 indicates that the calculation unit 520 is decoding calculation when verification is passed, the controller 510 further instructs the calculation unit 520 to stop decoding calculation, and discards the already obtained decoding result.
If check unit 560 indicates that the obtained variable node does not constitute a legal LDPC codeword (check failed) (660), controller 510 instructs calculation unit 520 to write the generated new value of the variable node to first variable node memory 530 and second variable node memory 570 (650). And controller 510 also instructs the start of the next iteration of decoding, transmitting the new variable node of first variable node memory 530 to calculation unit 520 (620), and simultaneously transmitting the new variable node of second variable node memory 570 to verification unit 560 (622).
In an alternative embodiment, each round of iterative decoding (620, 630, and 650) includes a plurality of sub-phases, each sub-phase processing a variable node associated with a row of the check matrix. Within each sub-phase, the (part of the) variable nodes are transferred from the first variable node memory 530 to the calculation unit 520, the calculation unit 520 generates new values for the variable nodes and writes the new values for the variable nodes back to the first variable node memory 530 and the second variable node memory 570. The next sub-phase of iterative decoding is then started. The writing of new values of variable nodes back to the first variable node memory 530 and the second variable node memory 570 of one sub-phase, and the reading of data from the first variable node memory 530 (and the second variable node memory 570) of the next sub-phase, each access a different variable node, occur substantially simultaneously.
If the check unit 560 indicates that the obtained variable nodes constitute legal LDPC codewords (check pass) (660), decoding is finished, and the variable nodes are output as decoding results of the LDPC decoder. At this point the calculation unit 520 is also generating new values for variable nodes and may have already generated new values for some variable nodes. In response to the verification passing 660, the controller 510 prevents the first variable node memory 530 (and the second variable node memory 570) from being updated with the new value of the variable node generated by the calculation unit 520.
Fig. 7 illustrates a timing diagram of a decoding process of an LDPC decoder according to an embodiment of the present application.
In fig. 7, the rightward direction is the time lapse direction. The upper portion of the body portion of fig. 7 illustrates operations (732, 742, 762, and 772) of writing data to the first variable node memory 530 and the second variable node memory 570, the middle portion of the body portion of fig. 7 illustrates operations (730, 740, 760, and 770) of reading data from the first variable node memory 530 to the calculation unit 520, and the lower portion of the body portion of fig. 7 illustrates operations (720, 750, and 780) of reading data from the second variable node memory 570 to the verification unit 560.
The example of 2 rows of check matrix is illustrated in fig. 7. In one iterative decoding process, for each row of the check matrix, variable nodes corresponding to the row of the check matrix are acquired from the first variable node memory 530, and are calculated by the calculation unit 520.
In the initialization phase (see also fig. 6, 610), variable nodes are stored in a first variable node memory 530 and the same variable nodes are also stored in a second variable node memory 570 (see also fig. 5) (710). In the first sub-phase of a round of iterative decoding, variable nodes are read from the first variable node memory 530 and provided to the computation unit 520 (730). Substantially simultaneously therewith, variable nodes are read out from the second variable node memory 570 and provided to the verification unit 560 (720), the verification unit 560 verifying whether the variable nodes constitute a legal LDPC codeword. Operation 720 is performed substantially in parallel with operation 730, thereby reducing the delay of the LDPC decoding process. By way of example, the variable nodes provided to computation unit 520 are variable nodes associated with the first row of the check matrix, while the variable nodes provided to check unit 560 are all variable nodes of the codeword to be decoded.
By way of example, the check unit 560 indicates a check failure (724).
The calculation unit 520 updates variable nodes associated with the first row of the check matrix according to the LDPC decoding algorithm. Since the check unit 560 indicates that the check fails, the calculation unit 520 can write the updated variable node back to the first variable node memory 530 (732). The variable nodes written back to the first variable node memory 530 are also written to the second variable node memory 570 (732).
After the variable nodes associated with the first row of the check matrix are read out of the first variable node memory 530 (730), the variable nodes associated with the second row of the check matrix are also read out of the first variable node memory 530 and provided to the computation unit 520 in a second sub-phase of the round of iterative decoding (740). Reading out the variable nodes associated with the second row of the check matrix from the first variable node memory 530 (740) is processed substantially in parallel with writing the updated variable nodes associated with the first row of the check matrix to the first variable node memory 530, each utilizing one access port (read port and write port) of the first variable node memory 530, thereby reducing the latency of the LDPC decoding process.
The computation unit 520 also updates the variable nodes associated with the second row of the check matrix and writes the updated variable nodes back to the first variable node memory 530 (742) and also to the second variable node memory 570 (742). With the updated portion of the variable nodes associated with the second row of the check matrix written back to the first variable node memory 530 (and the second variable node memory 570) (742), the controller 510 initiates a data transfer (750) at the second variable node memory 570 to the check unit 560 to identify whether a second round of iterative decoding is required. Referring to fig. 7, at the beginning of a data transfer (750) from the second variable node memory 570 to the check unit 560, the process of writing back the updated portion of the variable nodes associated with the second row of the check matrix to the first variable node memory 530 (and the second variable node memory 570) (742) has not been completed. At 750, the transfer from the second variable node memory 570 to the check unit 560 is initiated early by transferring the updated check node portion to the check unit 560. For example, there are 4096 variable nodes, and after the 1 st to 2048 th variable nodes are updated to the second variable node memory 570, although the 2049 th to 4096 th variable nodes have not been updated to the second variable node memory 570, the 1 st to 2048 th variable nodes may start to be transferred from the second variable node memory 570 to the verification unit 560.
So that immediately after the completion of writing the updated variable node back to the second variable node memory 570 (742), the verification unit 560 receives all the updated variable nodes and starts the verification for the second round of iterative decoding.
When the process of writing back the updated portion of the variable nodes associated with the second row of the check matrix to the first variable node memory 530 (and the second variable node memory 570) (742) has not been completed, the variable nodes associated with the first row of the check matrix are read out of the first variable node memory 530 at 760 so that the calculation unit 520 obtains the variable nodes for the second round of iterative decoding calculation as early as possible.
For example, the check matrix includes 2 rows, so that the variable nodes associated with the second row of the check matrix updated by the calculation unit 520 are written back to the first variable node memory 530 (and the second variable node memory 570) (742), and the first round of iterative decoding is ended.
The second round of iterative decoding is similar to the first round of iterative decoding in processing procedure. If check unit 560 indicates that the variable node is still not a valid LDPC codeword (end of 750), calculation unit 520 performs a second round of iterative decoding based on turning on the variable node associated with the first row of the check matrix and writes back the updated variable node to first variable node memory 530 (and second variable node memory 570) (762).
After the variable nodes corresponding to the first row of the check matrix are provided to the calculation unit 520 from the first variable node memory 530 (end 760), the variable nodes corresponding to the second row of the check matrix are provided to the calculation unit 520 next (770). After receiving the variable nodes corresponding to the first row of the check matrix, the computing unit 520 updates the variable nodes and writes the updated variable nodes back to the first variable node memory 530 (and the second variable node memory 570) (762); upon receiving the variable nodes corresponding to the second row of the check matrix (end of 770), the computing unit 520 updates the variable nodes and writes the updated variable nodes back to the first variable node memory 530 (and the second variable node memory 570) (772). By way of example, the check matrix includes 2 rows, and thus the further round of iterative decoding ends.
According to an embodiment of the present application, in the LDPC decoding process, a process of reading data from the second variable node memory 570 for checking whether a legal LDPC codeword is obtained is performed simultaneously with a process of reading data from the first variable node memory 530 for updating variable nodes by iterative decoding, thereby reducing a delay of LDPC decoding. In the LDPC decoding process, the first portion of the variable node is updated simultaneously with the process of reading the second portion of the variable node from the first variable node memory 530, thereby further reducing the delay of LDPC decoding. And updating the second portion of the variable node during the LDPC decoding process concurrently with the process of reading the variable node from the second variable node memory 570 for verification, thereby further reducing the delay of LDPC decoding. The LDPC decoding method according to the embodiment of the present application may be implemented by software, hardware, firmware, FPGA (field programmable gate array ) and/or ASIC (application specific integrated circuit, application Specific Integrated Circuit), or the like. The LDPC decoding method according to the embodiment of the application can be applied to solid state storage equipment based on an NVM (non-volatile memory) chip, including but not limited to a solid state disk, a U disk and an SD card, and can also be applied to portable electronic equipment such as a mobile phone, a tablet computer and the like, and other various electronic equipment which uses an NVM chip (such as a NAND flash memory) and needs to store information. The application also provides a memory controller comprising the LDPC decoder. The LDPC decoding method according to the embodiment of the present application can also be applied to equipment or services of LDPC codes used for communication, magnetic storage, optical storage, etc.
Although the present application has been described with reference to examples, which are intended for purposes of illustration only and not to be limiting of the application, variations, additions and/or deletions to the embodiments may be made without departing from the scope of the application.
Many modifications and other embodiments of the applications set forth herein will come to mind to one skilled in the art to which these embodiments pertain having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is to be understood that the applications are not to be limited to the specific embodiments disclosed and that modifications and other embodiments are intended to be included within the scope of the appended claims. Although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.
Claims (10)
1. An LDPC decoding method comprising:
transmitting the variable node stored in the first variable node memory to a computing unit to generate a new value of the variable node;
transmitting the variable nodes stored in the second variable node memory to a verification unit to verify the legitimacy of the LDPC code words formed by the variable nodes; the second variable node memory is the same as the variable nodes stored in the first variable node memory;
ending iterative decoding if the formed LDPC code word is legal;
if the formed LDPC code word is illegal, updating a first variable node memory and a second variable node memory through the new variable node value generated by the calculating unit;
transmitting the updated new value of the variable node in the first variable node memory to a computing unit; and transmitting the updated new value of the variable node in the second variable node memory to the verification unit so as to start the iterative decoding of the next round.
2. The LDPC decoding method as claimed in claim 1, wherein in a first sub-stage of one round of iterative decoding, variable nodes associated with a first row of a check matrix stored in a first variable node memory are transmitted to a calculation unit, and new values of the variable nodes of the first row are generated;
and if the check unit verifies that the formed LDPC code word is illegal, updating the first variable node memory and the second variable node memory through the new variable node value of the first row.
3. An LDPC decoder, comprising: the system comprises a first variable node memory, a second variable node memory, a calculation unit, a verification unit and a controller;
the controller instructs to acquire variable nodes from the first variable node memory and transmit the variable nodes to the computing unit to generate new values of the variable nodes, and instructs to acquire variable nodes from the second variable node memory and transmit the variable nodes to the checking unit to check the legitimacy of the variable nodes forming the LDPC codeword; the second variable node memory is the same as the variable nodes stored in the first variable node memory;
if the formed LDPC code word is legal, the controller indicates that iterative decoding is finished;
if the formed LDPC code word is illegal, the controller instructs the calculation unit to write the new value of the generated variable node into the first variable node memory and the second variable node memory;
transmitting the updated new value of the variable node in the first variable node memory to a computing unit; and transmitting the updated new value of the variable node in the second variable node memory to the verification unit so as to start the iterative decoding of the next round.
4. The LDPC decoder of claim 3, further comprising: and the controller instructs to acquire the check node from the check node memory and transmit the check node to the computing unit, and the computing unit generates new values of the variable node and the check node according to iterative decoding of the check node and the variable node.
5. The LDPC decoder as claimed in claim 4, wherein the controller controls the first variable node memory and the second variable node memory to be initialized with codewords to be decoded and the check node memory to be initialized with a check matrix in an initialization phase.
6. The LDPC decoder of any of claims 3 to 5 wherein the first variable node memory is a dual port memory having a read port coupled to the computing unit to provide the variable node to the computing unit; the write port of which is coupled to the calculation unit to write the variable node new value generated by the calculation unit to the first variable node memory.
7. The LDPC decoder of any of claims 3 through 5 wherein the second variable node memory is a dual port memory having a read port coupled to a verification unit to provide a variable node to the verification unit; the write port of which is coupled to the calculation unit to write the variable node new value generated by the calculation unit to the second variable node memory.
8. The LDPC decoder of claim 7 wherein the first variable node memory and the second variable node memory are operable to concurrently transmit variable nodes outward.
9. The LDPC decoder of claim 3, wherein in a first sub-phase of a round of iterative decoding, the controller instructs a first variable node memory to retrieve variable nodes associated with a first row of a check matrix for transmission to a computation unit, generating new values for the variable nodes of the first row;
if the check unit verifies that the formed LDPC code word is illegal, the controller indicates to update the first variable node memory and the second variable node memory with the new variable node value of the first row.
10. A memory controller comprising the LDPC decoder of any of claims 3 to 9.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810374178.0A CN110401453B (en) | 2018-04-24 | 2018-04-24 | Low delay LDPC decoder and decoding method thereof |
| CN202311175629.5A CN117040546A (en) | 2018-04-24 | 2018-04-24 | Low delay LDPC decoder and decoding method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810374178.0A CN110401453B (en) | 2018-04-24 | 2018-04-24 | Low delay LDPC decoder and decoding method thereof |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311175629.5A Division CN117040546A (en) | 2018-04-24 | 2018-04-24 | Low delay LDPC decoder and decoding method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110401453A CN110401453A (en) | 2019-11-01 |
| CN110401453B true CN110401453B (en) | 2023-10-03 |
Family
ID=68321979
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810374178.0A Active CN110401453B (en) | 2018-04-24 | 2018-04-24 | Low delay LDPC decoder and decoding method thereof |
| CN202311175629.5A Pending CN117040546A (en) | 2018-04-24 | 2018-04-24 | Low delay LDPC decoder and decoding method thereof |
Family Applications After (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311175629.5A Pending CN117040546A (en) | 2018-04-24 | 2018-04-24 | Low delay LDPC decoder and decoding method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (2) | CN110401453B (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101478312A (en) * | 2008-12-15 | 2009-07-08 | 北京创毅视讯科技有限公司 | LDPC decoder and method for decoding implementation |
| CN107852176A (en) * | 2015-01-14 | 2018-03-27 | 北京航空航天大学 | LDPC code encoder and decoder |
| CN107872231A (en) * | 2016-09-28 | 2018-04-03 | 北京忆芯科技有限公司 | LDPC interpretation methods and device |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI425519B (en) * | 2009-12-09 | 2014-02-01 | Nat Chip Implementation Ct Nat Applied Res Lab | Method for arranging memories of low-complexity low-density parity-check codes decoder and the ldpc codes decoder thereof |
-
2018
- 2018-04-24 CN CN201810374178.0A patent/CN110401453B/en active Active
- 2018-04-24 CN CN202311175629.5A patent/CN117040546A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101478312A (en) * | 2008-12-15 | 2009-07-08 | 北京创毅视讯科技有限公司 | LDPC decoder and method for decoding implementation |
| CN107852176A (en) * | 2015-01-14 | 2018-03-27 | 北京航空航天大学 | LDPC code encoder and decoder |
| CN107872231A (en) * | 2016-09-28 | 2018-04-03 | 北京忆芯科技有限公司 | LDPC interpretation methods and device |
Non-Patent Citations (1)
| Title |
|---|
| 黎海涛 ; 杨磊磊 ; 刘飞 ; 袁海英 ; .多元LDPC译码器的设计与实现.高技术通讯.2013,(12),第91-99页. * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110401453A (en) | 2019-11-01 |
| CN117040546A (en) | 2023-11-10 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102412847B (en) | Method and apparatus for decoding low density parity check code using united node processing | |
| US7552097B2 (en) | Methods and apparatus for decoding LDPC codes | |
| CN108053862B (en) | Recovering data for a failed memory cell using reliability information from a plurality of memory cells and a parity memory cell | |
| US9432053B1 (en) | High speed LDPC decoder | |
| US8707144B2 (en) | LDPC decoder with targeted symbol flipping | |
| US8775896B2 (en) | Non-binary LDPC decoder with low latency scheduling | |
| US8739004B2 (en) | Symbol flipping LDPC decoding system | |
| KR101306645B1 (en) | Error correction decoding by trial and error | |
| US7853854B2 (en) | Iterative decoding of a frame of data encoded using a block coding algorithm | |
| TWI411912B (en) | Error-floor mitigation of codes using write verification | |
| US8667360B2 (en) | Apparatus, system, and method for generating and decoding a longer linear block codeword using a shorter block length | |
| US20130275827A1 (en) | Multi-Section Non-Binary LDPC Decoder | |
| US10707902B2 (en) | Permutation network designing method, and permutation circuit of QC-LDPC decoder | |
| US10484020B2 (en) | System and method for parallel decoding of codewords sharing common data | |
| CN109586731B (en) | System and method for decoding error correction codes | |
| US8862961B2 (en) | LDPC decoder with dynamic graph modification | |
| US20170134049A1 (en) | Decoding method, memory storage device and memory control circuit unit | |
| US10790854B2 (en) | Coset probability based majority-logic decoding for non-binary LDPC codes | |
| US10700708B2 (en) | Permutation network designing method, and permutation circuit of QC-LDPC decoder | |
| CN107872231B (en) | LDPC decoding method and device | |
| US8516351B2 (en) | Compact decoding of punctured block codes | |
| KR20160002946A (en) | Method and apparatus of ldpc encoder in 10gbase-t system | |
| CN110401453B (en) | Low delay LDPC decoder and decoding method thereof | |
| US10826531B2 (en) | Error correction circuit and operating method thereof | |
| CN111769839B (en) | Fast bit-flipping decoding method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |