CN110401453A - Low latency ldpc decoder and its interpretation method - Google Patents
Low latency ldpc decoder and its interpretation method Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1105—Decoding
- H03M13/1111—Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
- H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
- H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
- H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
- H03M13/1148—Structural properties of the code parity-check or generator matrix
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Abstract
This application involves low density parity check code (Low Density Parity Check Code, LDPC) interpretation methods, comprising: the variable node that the first variable node memory stores is transferred to computing unit to generate the new value of the variable node；The variable node that second variable node memory stores is transferred to verification unit to verify the legitimacy that the variable node is constituted LDPC code word；If the LDPC code word constituted is legal, terminate iterative decoding；If the LDPC code word constituted is illegal, the variable node generated by computing unit, which is newly worth, updates the first variable node memory and the second variable node memory.Due to reading the process for verifying the data for whether obtaining legal LDPC code word from the second variable node memory, it is carried out simultaneously with the process for updating the data of variable node for iterative decoding is read from the first variable node memory, so as to shorten the delay of LDPC decoding.
Description
Technical field
This application involves the decoding sides low density parity check code (Low Density Parity Check Code, LDPC)
Method, more particularly it relates to the optimization to the LDPC decoding process based on minimum-sum algorithm.
Background technique
LDPC code is a kind of Error Correction of Coding, and compared with other Error Corrections of Coding, under identical code rate, LDPC code has error correction
The characteristics of ability is strong, fast convergence rate, therefore be SSD (solid state drive, Solid State Drive) controller neck at this stage
The optimal Error Correction of Coding in domain.
LDPC code is a kind of binary packet code, using supersparsity matrix as check matrix.Every row is (every in check matrix
Column) in nonzero element it is rare.For any legal code word V, the product of code word V and check matrix H is zero.It uses in the prior art
Tanner figure description LDPC code.Tanner figure is made of two class nodes, and one kind is variable node, and one kind is check-node.Each
Variable node corresponds to a bit of code word, and each check-node corresponds to a line of check matrix H.Variable node and check-node
Line correspond to " 1 " in check matrix.Fig. 1 is the Tanner figure of LDPC code.In iterative decoding process, decoder utilizes school
The constraint relationship for testing node and variable node is iterated decoding.The input of each variable node is to receive the corresponding logarithm of sequence seemingly
So output of ratio and check-node last time iteration；Then, the output of variable node is sent to corresponding verification by " line "
Node is decoded using the constraint relationship of check-node.In this process, a kind of node is output into another section
The input of point, " line " corresponding to nonzero element becomes channel of both node switching information in matrix.In Chinese patent
A kind of interpretation method of LDPC code is provided in application 2016108617916 (patent name is LDPC interpretation method and device),
Its full text is incorporated by reference into the application.
Common LDPC decoding algorithm includes: belief propagation algorithm (Belief Propagation, BP), minimum-sum algorithm
(Min-Sum) and bit reversal algorithm (Bit Flip) etc..And minimum-sum algorithm and based on the innovatory algorithm of minimum-sum algorithm by
It is simple in its hardware timeout, and there is error-correcting performance good enough to be widely adopted in SSD controller field.
Minimum-sum algorithm includes multiple key steps.Initializing variable node and check-node first, variable node just
Initial value is, for example, from the value that storage medium is read, the initial value of check-node is obtained according to used check matrix.In
In one wheel of LDPC iterative decoding, check-node and variable node are updated.Updated variable node and check-node will be under
It is used in one wheel decoding.Verification also is executed to variable node, to identify whether it is correct code word.If having obtained correctly
Code word stops decoding process.
AN-MS (Adaptive Normalize Min-Sum Algorithm) algorithm is that one kind is changed based on minimum-sum algorithm
Into iterative decoding algorithm.It is that a kind of error correcting capability is strong, and is relatively easy hard-wired LDPC decoding algorithm.AN-MS is calculated
The core decoding process of method includes two parts: variable node processing and code check node processing.It needs to complete to become in an iteration
Measure node processing and code check node processing.It completes to decode if decoding result after iteration correctly, otherwise starts next iteration,
Until it is successfully decoded or be more than preset maximum number of iterations.
AN-MS algorithm is discussed in detail referring to " Wu X, Song Y, Cui L, et al.Adaptive-normalized
Min-sum algorithm [C], 2010 2nd International Conference on Future Computer and
Communication.2010. ", its full text is incorporated by reference into the application.
Ldpc decoder implements LDPC decoding algorithm.Fig. 2 illustrates the block diagram of the ldpc decoder of the prior art.
Controller 210 controls LDPC and decodes process, controls the cooperation between each component of decoder, adding including check matrix
It carries, the data write-in and reading of each storage unit control iterative decoding process, identification decoding termination condition etc..
Computing unit 220 is used to handle the calculating during decoding, according to the operation that decoding algorithm indicates, calculates variable section
The new value of point and check-node.Computing unit 220 have it is multiple, concurrently to calculating.Variable node memory 230, for depositing
Store up variable node information；Check node memory 240, for storing check-node, temporary variable memory 250 is based on storing
Calculate the temporary information, such as symbol, minimum value etc. generated in unit calculating process.Verification unit 260 is for verifying variable node
It whether is legal LDPC code word.
Fig. 3 illustrates the decoding process of the ldpc decoder of the prior art.
After starting the decoding to code word, under the instruction of controller 210, deposited with code word initializing variable node to be decoded
Reservoir 230, with check matrix initiation verification node memory 240 (310).Variable section is obtained from variable node memory 230
Point (320), verification unit 260 check whether the variable node obtained constitutes legal LDPC code word (330).If variable node
Legal LDPC code word (340) is constituted, then decoding terminates, decoding result (360) of the output variable node as ldpc decoder.If
Variable node does not constitute legal LDPC code word (340) still, and variable node and check-node are supplied to calculating list by computing unit 220
Member 220 carries out an iteration decoding (350).During an iteration decoding, computing unit 220 generates variable node and verification
The new value of node, new value are used to update variable node memory and check node memory.And verification unit 260 obtains again
The variable node in variable node memory is taken, and is verified.
Fig. 4 illustrates the timing diagram of the decoding process of the ldpc decoder of the prior art.
In Fig. 4, direction to the right is direction of passing the time.There are 2 behavior examples to be described with check matrix in Fig. 4.One
In secondary iterative decoding process, for every row of check matrix, the row correspondence with check matrix is obtained from variable node memory 230
Variable node, calculated by computing unit 220.Fig. 4 is shown around the access to variable node memory 230.
At initial phase (referring also to Fig. 3,310), by variable node storage to variable node memory 230 (410).It connects
Get off, reads variable node (420) from variable node memory 230, be supplied to verification unit 260.Optionally, from variable node
Before 230 transmission variables node of memory betides the initialization completion of variable node memory 230 to verification unit 260 (420),
To shorten the delay of LDPC decoding.For example, variable node includes 4096, variable node is stored in the part of variable node
After memory 230, i.e., starting is transmitted from variable node memory 230 to the data of verification unit 260, has been written to transmission
The Partial Variable node of variable node memory 230.
Verification unit 260 is verified (422) to variable node, in response to check results (failure), again from variable section
Point memory 230 reads variable node, and the corresponding variable node of the first row of same check matrix is transferred to computing unit 220
(430).Computing unit generates the corresponding variable node of the first row of updated same check matrix, and writes back to variable node and deposit
Reservoir 230 (432).To occur the process (432) of updated variable node write-in variable node memory 230 will be same
The variable node of check matrix is transferred to after computing unit 220 (430).
It, will also be with verification after the corresponding variable node of the first row of same check matrix is transferred to computing unit 220 (430)
The corresponding variable node of the second row of matrix is transferred to computing unit 220 (440), and computing unit 220 generates updated same school
The corresponding variable node of the second row of matrix is tested, and writes back to variable node memory 230 (442).So far first time iteration is translated
Code is completed.
Next variable node is transferred to verification unit 260 (450), to identify it is legal whether variable node constitutes
LDPC code word.If variable node is not still legal LDPC code word, controller 210 opens the second wheel iterative decoding.
Second wheel iterative decoding is identical with the treatment process of first round iterative decoding.It will be same from variable node memory 230
The corresponding variable node of the first row of check matrix is supplied to computing unit 220 (460), next by the second of same check matrix
The corresponding variable node of row is supplied to computing unit 220 (470).In the corresponding variable node of the first row for receiving same check matrix
Afterwards, computing unit 220 updates these variable nodes, and updated variable node is write back variable node memory 230
(462)；After receiving the corresponding variable node of the second row of same check matrix, computing unit 220 updates these variable nodes, and
Updated variable node is write back into variable node memory 230 (472).As an example, check matrix includes 2 rows, thus extremely
This another wheel iterative decoding terminates.
Next variable node is transferred to verification unit 260 (480), to identify it is legal whether variable node constitutes
LDPC code word.
Summary of the invention
The application is intended to provide a kind of LDPC interpretation method or ldpc decoder, to further decrease ldpc decoder introducing
Delay.
According to a first aspect of the present application, the first LDPC interpretation method according to the application first aspect is provided, comprising:
The variable node that first variable node memory stores is transferred to computing unit to generate the new value of the variable node；By
The variable node of two variable node memories storage is transferred to verification unit to verify the variable node and be constituted LDPC code word
Legitimacy；If the LDPC code word constituted is legal, terminate iterative decoding；If the LDPC code word constituted is illegal, pass through calculating
The variable node that unit generates, which is newly worth, updates the first variable node memory and the second variable node memory.
According to the first LDPC interpretation method of the application first aspect, wherein by the storage of the first variable node memory
Variable node is transferred to computing unit and the variable node that the second variable node memory stores is transferred to verification unit simultaneously
It carries out.
According to the first LDPC interpretation method of the application first aspect, wherein in initial phase, with code word to be decoded
The first variable node memory and the second variable node memory are initialized, with check matrix initiation verification node memory.
According to the 3rd LDPC interpretation method of the application first aspect, comprising: the verification for storing check node memory
Node-node transmission is iterated decoding according to check-node and variable node and generates variable node newly value and verification section to computing unit
The new value of point.
According to one of the first to fourth LDPC interpretation method of the application first aspect, wherein in response to the LDPC of composition
Code word is legal, and prevention is newly worth with variable node updates the first variable node memory and the second variable node memory.
According to one of the first to the 5th LDPC interpretation method of the application first aspect, wherein in response to the LDPC of composition
Code word is legal, if computing unit is decoding calculating at this time, terminates decoding and calculates, and abandon obtained decoding result.
According to the third of the application first aspect or the 4th LDPC interpretation method, wherein the first of a wheel iterative decoding
In sub-stage, the variable node of the first row for being associated with check matrix of the first variable node memory storage is transferred to calculating
Unit, the variable node for generating the first row are newly worth；If the LDPC code word that verification unit verifying is constituted is illegal, pass through institute
Stating the variable node of the first row, newly value updates the first variable node memory and the second variable node memory.
According to the 7th LDPC interpretation method of the application first aspect, wherein the variable node for being supplied to verification unit is
All variable nodes of code word to be decoded.
According to the 7th LDPC interpretation method of the application first aspect, wherein by the storage of the first variable node memory
It is associated with the change that the variable node of the first row of check matrix is transferred to computing unit and stores the second variable node memory
Amount node-node transmission carries out simultaneously to verification unit.
According to the 7th LDPC interpretation method of the application first aspect, wherein in the second sub-stage of a wheel iterative decoding
In, the variable node of the second row for being associated with check matrix of the first variable node memory storage is transferred to computing unit,
The variable node for generating second row is newly worth；Newly be worth by the variable node of the second row update the first variable node memory and
Second variable node memory；Until the variable node for being associated with all rows of check matrix is generated corresponding variable node
New value, and after newly be worth by corresponding variable node and updating the first variable node memory and the second variable node memory, it is somebody's turn to do
Wheel iterative decoding terminates.
According to the tenth LDPC interpretation method of the application first aspect, wherein verification square will be associated in the first sub-stage
After the variable node of the first row of battle array is transferred to computing unit from the first variable node memory completely, start in the second sub-stage
The variable node for reading the second row for being associated with check matrix from the first variable node memory is transferred to computing unit.
According to the tenth LDPC interpretation method of the application first aspect, wherein deposited from computing unit to the first variable node
Reservoir write-in is associated with the first row variable node of check matrix and newly value and reads from the first variable node memory and be associated with school
The the second row variable node for testing matrix is transferred to computing unit parallel processing.
According to the tenth LDOC interpretation method of the application first aspect, wherein with last for being associated with check matrix
The part that capable variable node is newly worth is written into the first variable node memory, opens in next round iterative decoding from the second variable
The updated variable node of node memory to verification unit transmits.
According to the 13rd LDOC interpretation method of the application first aspect, wherein be associated with the last line of check matrix
Variable node be newly worth the first variable node memory be all written, the second variable node is deposited in next round iterative decoding
The updated variable node of reservoir storage is all transferred to verification unit.
According to the tenth LDOC interpretation method of the application first aspect, wherein with last for being associated with check matrix
The part that capable variable node is newly worth is written into the first variable node memory, opens in next round iterative decoding from the first variable
The updated variable node of node memory to computing unit transmits.
According to a second aspect of the present application, the first ldpc decoder according to the application second aspect is provided, comprising: the
One variable node memory, the second variable node memory, computing unit, verification unit and controller；The controller instruction
Variable node is obtained from the first variable node memory and is transferred to computing unit to generate the new value of the variable node, and is referred to
Show that obtaining variable node from the second variable node memory is transferred to verification unit to check that the variable node is constituted LDPC code
The legitimacy of word；If the LDPC code word constituted is legal, controller indicates that iterative decoding terminates；If the LDPC code word constituted does not conform to
Method, controller then indicate that computing unit will generate variable node newly value the first variable node memory of write-in and the second variable node
Memory.
According to the first ldpc decoder of the application second aspect, wherein the controller indicates that the first variable node is deposited
The variable node of reservoir storage is transferred to computing unit and the variable node of the second variable node memory storage is transferred to verification
Unit carries out simultaneously.
According to the first ldpc decoder of the application second aspect, further includes: for storing the check-node of check-node
Memory, the controller instruction obtain check-node from check node memory and are transferred to computing unit, and computing unit
Decoding, which is iterated, according to check-node and variable node generates the variable node new value that newly value and verification save.
According to the third ldpc decoder of the application second aspect, wherein in initial phase, the controller control is used
Code word to be decoded initializes the first variable node memory and the second variable node memory, with check matrix initiation verification
Node memory.
According to one of first to fourth ldpc decoder of the application second aspect, wherein the computing unit be it is multiple,
Multiple computing unit parallel computations.
According to one of first to fourth ldpc decoder of the application second aspect, wherein first variable node is deposited
Reservoir is dual-ported memory, and read port is coupled to computing unit, to provide variable node to computing unit；Its write port coupling
Computing unit is closed, is newly worth with the variable node generated to the first variable node memory write-in computing unit.
According to the 6th ldpc decoder of the application second aspect, wherein the reading end of the first variable node memory
Mouth and write port can simultaneous transmission data.
According to one of first to fourth ldpc decoder of the application second aspect, wherein the check node memory
For dual-ported memory.
According to one of first to fourth ldpc decoder of the application second aspect, wherein ldpc decoder, further includes:
For storing the temporary variable memory of the temporary information generated in computing unit calculating process, temporary variable memory is coupled to
Computing unit.
According to one of first to fourth ldpc decoder of the application second aspect, ldpc decoder, wherein described second
Variable node memory is dual-ported memory, and read port is coupled to verification unit, to provide variable node to verification unit；
Its write port is coupled to computing unit, is newly worth with the variable node generated to the second variable node memory write-in computing unit.
According to the tenth ldpc decoder of the application second aspect, wherein the first variable node memory and second
Variable node memory can transmission variables node outward simultaneously.
According to the first ldpc decoder of the application second aspect, wherein it is legal in response to the LDPC code word of composition, it is described
Controller prevention is newly worth with variable node updates the first variable node memory and the second variable node memory.
According to the first ldpc decoder of the application second aspect, wherein it is legal in response to the LDPC code word of composition, if this
When computing unit decoding calculating, the controller control computing unit terminates decoding and calculates, and abandons translating of having obtained
Code result.
According to the first ldpc decoder of the application second aspect, wherein in the first sub-stage of a wheel iterative decoding,
The controller instruction is transferred to from the variable node that the first variable node memory obtains the first row for being associated with check matrix
Computing unit, the variable node for generating the first row are newly worth；If the LDPC code word that verification unit verifying is constituted is illegal, control
Device then indicates that newly value updates the first variable node memory and the second variable node memory with the variable node of the first row.
According to the 14th ldpc decoder of the application second aspect, wherein the controller indicates the second variable node
Memory be supplied to verification unit variable node be code word to be decoded all variable nodes.
According to the 14th ldpc decoder of the application second aspect, wherein the controller is indicated from the first variable section
The variable node that point memory obtains the first row for being associated with check matrix is transferred to computing unit and deposits from the second variable node
Reservoir obtains variable node and is transferred to verification unit while carrying out.
According to the 14th ldpc decoder of the application second aspect, wherein in the second sub-stage of a wheel iterative decoding
In, the controller instruction obtains the variable node transmission for being associated with the second row of check matrix from the first variable node memory
To computing unit, the variable node for generating second row is newly worth；The controller indicates that the variable node of the second row is newly worth more
New first variable node memory and the second variable node memory；Until the variable section of all rows of check matrix will be associated with
Point generates corresponding variable node and is newly worth, and newly be worth the first variable node memory of update and the by corresponding variable node
After two variable node memories, which terminates.
According to the 17th ldpc decoder of the application second aspect, wherein verification square will be associated in the first sub-stage
After the variable node of the first row of battle array is transferred to computing unit from the first variable node memory completely, the controller instruction is opened
It is transferred in second sub-stage that begins from the variable node that the first variable node memory reads the second row for being associated with check matrix
Computing unit.
According to the 17th ldpc decoder of the application second aspect, wherein controller control from computing unit to
The write-in of first variable node memory is associated with the first row variable node of check matrix newly value and from the storage of the first variable node
The second row variable node that device reading is associated with check matrix is transferred to computing unit parallel processing.
According to the 17th LDOC decoder of the application second aspect, wherein with last for being associated with check matrix
The part that capable variable node is newly worth is written into the first variable node memory, and the controller instruction is opened next round iteration and translated
It is transmitted in code from the second variable node memory to the updated variable node of verification unit.
According to the 20th LDOC decoder of the application second aspect, wherein be associated with the last line of check matrix
Variable node, which is newly worth, is all written the first variable node memory, by second in the controller instruction next round iterative decoding
The updated variable node of variable node memory storage is all transferred to verification unit.
According to the 17th LDOC decoder of the application second aspect, wherein with last for being associated with check matrix
The part that capable variable node is newly worth is written into the first variable node memory, and controller instruction is opened in next round iterative decoding
It is transmitted from the first variable node memory to the updated variable node of computing unit.
According to the third aspect of the application, the first storage control according to the application third aspect is provided, including upper
State described in any item LDOC decoders.
According to LDPC provided by the present application decode process it is found that for verify whether obtained legal LDPC code word from
Second variable node memory reads the process of data, with updated for iterative decoding variable node from the first variable node
The process that memory reads data carries out simultaneously, so as to shorten the delay of LDPC decoding.During LDPC decoding, updates and become
The first part for measuring node carries out simultaneously with the process for the second part for reading variable node from the first variable node memory,
To further shorten the delay of LDPC decoding.And during LDPC decoding, the second part of variable node is updated, with
Process of the variable node for verification is read from the second variable node memory to carry out simultaneously, is translated to further shorten LDPC
The delay of code.
Detailed description of the invention
When being read together with attached drawing, by reference to the detailed description below to illustrative embodiment, will be best understood
The present invention and preferred use pattern and its further objects and advantages, wherein attached drawing include:
Fig. 1 is the Tanner figure of LDPC code；
Fig. 2 illustrates the block diagram of the ldpc decoder of the prior art；
Fig. 3 illustrates the decoding process of the ldpc decoder of the prior art；
Fig. 4 illustrates the timing diagram of the decoding process of the ldpc decoder of the prior art；
Fig. 5 illustrates the block diagram of the ldpc decoder according to the embodiment of the present application；
Fig. 6 illustrates the decoding process according to the ldpc decoder of the embodiment of the present application；
Fig. 7 illustrates the timing diagram of the decoding process according to the ldpc decoder of the embodiment of the present application.
Specific embodiment
The embodiment of the present invention is described below in detail, examples of the embodiments are shown in the accompanying drawings, wherein from beginning to end
Same or similar label indicates same or similar element or element with the same or similar functions.Below with reference to attached
The embodiment of figure description is exemplary, and for explaining only the invention, and is not construed as limiting the claims.
Fig. 5 illustrates the block diagram of the ldpc decoder according to the embodiment of the present application.
Controller 510 is coupled to each component of ldpc decoder, and control LDPC decodes process, controls each portion of ldpc decoder
Cooperation between part, the load including check matrix, the data write-in and reading of each storage unit control iterative decoding process,
Identification decoding termination condition etc..
Computing unit 520 is used to handle the calculating during decoding, according to the operation that LDPC decoding algorithm indicates, calculates and becomes
Measure the new value of node and check-node.Optionally, computing unit 520 has multiple, concurrently to calculate.The storage of first variable node
Device 530, for storing variable node information.First variable node memory 530 be dual-ported memory, including read port with write
Port, read port and write port can simultaneous transmission data.Check node memory 540, for storing check-node.Optionally,
Check node memory 540 is also dual-ported memory.Temporary variable memory 55 is for storing in computing unit calculating process
Temporary information of generation, such as symbol, minimum value etc..Verification unit 560 is for verifying whether variable node is legal LDPC
Code word.
Ldpc decoder according to the embodiment of Fig. 5 further includes the second variable node memory 570.Second variable node is deposited
Reservoir 570 includes two ports, read port and write port.Second variable node memory 570 is also used for storage variable node.The
The variable node stored in two variable node memories 570 is the variable node stored in the first variable node memory 530
Copy.For example, for the update (initialization or updating variable node) arbitrarily to the first variable node memory 530, similarly
Update is also applied to the second variable node memory 570.Second variable node memory 570 is equivalent to as the first variable node
Memory 530 increases the second read port, so that the first variable node memory 530 and the second variable node memory 570 can
Outside transmission variables node simultaneously.
According to the embodiment of Fig. 5, the read port of the first variable node memory 530 is coupled to computing unit 520, in terms of
It calculates unit 520 and variable node is provided.The write port of first variable node memory 530 is coupled to computing unit 520, to calculate
The first variable node memory 530 is written by updated variable node, by write port in unit 520.Second variable node is deposited
The read port of reservoir 570 is coupled to verification unit 560, to provide variable node to verification unit 560.The storage of second variable node
The write port of device 570 is coupled to computing unit 520, so that computing unit 520 is by updated variable node, also by write port
The second variable node memory 570 is written.
Fig. 6 illustrates the decoding process according to the ldpc decoder of the embodiment of the present application.
After starting the decoding to code word, under the instruction of controller 510, the first variable section is initialized with code word to be decoded
Point memory 530 and the second variable node memory 570, with check matrix initiation verification node memory 540 (610).In
While being transferred to computing unit 520 (620) from the first variable node memory 530 acquisition variable node, from the second variable section
Point memory 570 obtains variable node and is transferred to verification unit 560 (622), and verification unit 560 checks that the variable node obtained is
It is no to constitute legal LDPC code word.
Computing unit 520 is iterated decoding according to LDPC decoding algorithm, generate acquisition variable node (and verification section
Point) new value (630).And whether the variable node that the check results instruction of verification unit 560 obtains constitutes legal LDPC code
Word (660).If the variable node that the instruction of verification unit 560 obtains constitutes legal LDPC code word (verification passes through), in controller
Under the action of 510, the new value for the variable node that computing unit 520 generates will not be updated to the first variable node memory 530
(with the second variable node memory 570), and decode process and terminate, the variable result that verification unit 560 obtains (is also stored
In the first variable node memory 530 and/or the second variable node memory 570) as decoding result.Optionally, if verification
Computing unit 520 is decoding calculating when the instruction of unit 560 is verified, and controller 510 also indicates the stopping of computing unit 520 and translates
Code calculates, and abandons obtained decoding result.
If the variable node that the instruction of verification unit 560 obtains does not constitute legal LDPC code word (verification does not pass through) (660),
Controller 510 indicate computing unit 520 by the new value of the variable node of generation be written to the first variable node memory 530 and
Second variable node memory 570 (650).And controller 510 also indicates and starts next round iterative decoding, by the first variable section
The new variables node-node transmission of memory 530 is put to computing unit 520 (620), and simultaneously by the second variable node memory 570
New variables node-node transmission to verification unit 560 (622).
In alternative embodiments, every wheel iterative decoding (620,630 and 650) includes multiple sub-stages, every sub- rank
A line associated variable node of the section processing with check matrix.In each sub-stage, transmitted from the first variable node memory 530
For (part) variable node to computing unit 520, computing unit 520 generates the new value of variable node, and by the new value of variable node
Write back to the first variable node memory 530 and the second variable node memory 570.Next the next of iterative decoding is opened
Sub-stage.The new value of variable node is write back the first variable node memory 530 and deposits with the second variable node by one sub-stage
The process of reservoir 570 is read with next sub-stage from the first variable node memory 530 (with the second variable node memory 570)
The process of data out respectively accesses different variable nodes, and generally occurs simultaneously.
If the variable node that the instruction of verification unit 560 obtains constitutes legal LDPC code word (verification passes through) (660), decode
Terminate, decoding result of the output variable node as ldpc decoder.Computing unit 520 is also generating the new of variable node at this time
Value, and the new value of Partial Variable node may have been produced.In response to verification by (660), the prevention of controller 510 is used tricks
The new value for calculating the variable node that unit 520 generates updates the first variable node memory 530 (with the second variable node memory
570)。
Fig. 7 illustrates the timing diagram of the decoding process according to the ldpc decoder of the embodiment of the present application.
In Fig. 7, direction to the right is direction of passing the time.The top of the main part of Fig. 7 is illustrated to the first variable section
The operation (732,742,762 and 772) of point memory 530 and the second variable node memory 570 write-in data, the main body of Fig. 7
Partial centre illustrate from the first variable node memory 530 read data to computing unit 520 operation (730,740,
760 and 770), the lower part of the main part of Fig. 7 illustrates from the second variable node memory 570 and reads data to verification unit
560 operation (720,750 and 780).
There are 2 behavior examples to be described with check matrix in Fig. 7.During an iteration decoding, for check matrix
Every row, from the first variable node memory 530 obtain with the row of check matrix corresponding variable node, by computing unit 520 into
Row calculates.
At initial phase (referring also to Fig. 6,610), by variable node storage to the first variable node memory 530, with
And same variable node is also stored into the second variable node memory 570 (referring also to Fig. 5) (710).It is translated in a wheel iteration
In first sub-stage of code, variable node is read from the first variable node memory 530 and is supplied to computing unit 520 (730).With
This essentially simultaneously, from the second variable node memory 570 reads variable node, is supplied to verification unit 560 (720), school
Verification certificate member 560 verifies whether variable node constitutes legal LDPC code word.Operation 720 is held substantially in parallel with operation 730
Row, to reduce the delay of LDPC decoding process.As an example, the variable node for being supplied to computing unit 520 is associated with school
The variable node of the first row of matrix is tested, and the variable node for being supplied to verification unit 560 is all variables of code word to be decoded
Node.
As an example, the instruction verification failure of verification unit 560 (724).
Computing unit 520 updates the variable node for being associated with the first row of check matrix according to LDPC decoding algorithm.Due to
The instruction verification failure of verification unit 560, computing unit 520 are able to writing back updated variable node into the storage of the first variable node
Device 530 (732).The variable node for being written back into the first variable node memory 530 is also written to the second variable node memory
570(732)。
The variable node of the first row of check matrix will be associated with after the reading of the first variable node memory 530
(730), the variable node of the second row of check matrix and then will be also associated in the second sub-stage of a wheel iterative decoding
It is read from the first variable node memory 530 and is supplied to computing unit 520 (740).It is read from the first variable node memory 530
It is associated with the variable node (740) of the second row of check matrix out, it is updated with being written to the first variable node memory 530
The variable node (732) for being associated with the first row of check matrix is generally processed in parallel, and is deposited each with the first variable node
An access port (read port and write port) for reservoir 530, to reduce the delay of LDPC decoding process.
Computing unit 520 also updates the variable node for being associated with the second row of check matrix, and by updated variable section
Point writes back the first variable node memory 530 (742), and also writes back to the second variable node memory 570 (742).With
The part of the variable node of updated the second row for being associated with check matrix be written back into the first variable node memory 530 (with
Second variable node memory 570) (742), controller 510, which is opened, arrives verification unit 560 in the second variable node memory 570
Data transmit (750), with identification second wheel iterative decoding whether need to carry out.Referring to Fig. 7, stored from the second variable node
When the data transmission (750) of device 570 to verification unit 560 starts, by the change of updated the second row for being associated with check matrix
The part of amount node writes back the process of the first variable node memory 530 (with the second variable node memory 570) (742) not yet
It completes.750, by transmitting the check-node part being updated to verification unit 560, initiated ahead of time from the second variable section
Point memory 570 arrives the transmission of verification unit 560.For example, variable node has 4096, in the 1st~2048 variable node quilt
It updates to after the second variable node memory 570, although the 2049-4096 variable node is not yet updated to the second variable section
Point memory 570, but can start to be transferred to verification unit from the second variable node memory 570 by the 1-2048 variable node
560。
Thus after the completion of updated variable node to be write back to the operation of the second variable node memory 570 (742)
Soon, verification unit 560 is received by all updated variable nodes, and starts the school for the second wheel iterative decoding
It tests.
It is deposited the part of the variable node of updated the second row for being associated with check matrix is write back the first variable node
When the process of reservoir 530 (with the second variable node memory 570) (742) is not yet completed, 760, deposited from the first variable node
Reservoir 530 reads the variable node for being associated with the first row of check matrix, so that computing unit 520 is obtained as early as possible for the second wheel
The variable node that iterative decoding calculates.
As an example, check matrix includes 2 rows, thus the second row for being associated with check matrix that computing unit 520 updates
Variable node, after being written back into the first variable node memory 530 (and second variable node memory 570) (742), first
Wheel iterative decoding terminates.
Second wheel iterative decoding is similar with the treatment process of first round iterative decoding.If 560 indicator variable section of verification unit
Point is not still legal LDPC code word (750 end), and computing unit 520 is associated with the first row of check matrix according to opening
Variable node second takes turns iterative decoding, and updated variable node is write back the first variable node memory 530 and (is become with second
Measure node memory 570) (762).
Calculating is being supplied to from the first variable node memory 530 by the corresponding variable node of the first row of same check matrix
After unit 520 (760 end), the corresponding variable node of the second row of same check matrix is next supplied to computing unit 520
(770).After the corresponding variable node of the first row for receiving same check matrix, computing unit 520 updates these variable nodes, and
Updated variable node is write back into the first variable node memory 530 (and second variable node memory 570) (762)；
After receiving the corresponding variable node of the second row of same check matrix (770 end), computing unit 520 updates these variable sections
Point, and updated variable node is write back into the first variable node memory 530 (and second variable node memory 570)
(772).As an example, check matrix includes 2 rows, thus so far another wheel iterative decoding terminates.
According to an embodiment of the present application, during LDPC is decoded, legal LDPC code word whether has been obtained for verifying
The process that data are read from the second variable node memory 570, with updated for iterative decoding variable node from first
The process that variable node memory 530 reads data carries out simultaneously, so as to shorten the delay of LDPC decoding.It was decoded in LDPC
Cheng Zhong updates the first part of variable node, with the second part from the first variable node memory 530 reading variable node
Process carries out simultaneously, to further shorten the delay of LDPC decoding.And during LDPC decoding, update variable node
Second part, with from the second variable node memory 570 read variable node for verification process carry out simultaneously, thus into
One step shortens the delay of LDPC decoding.It can be by software, hardware, firmware, FPGA (field programmable gate array, Field
Programmable Gate Array) and/or ASIC (application specific integrated circuit, Application Specific
Integrated Circuit) etc. realize LDPC interpretation method according to an embodiment of the present invention.And according to embodiments of the present invention
LDPC interpretation method can be applied to the solid storage device based on NVM chip, including but not limited to solid state hard disk, USB flash disk, SD
Card can also be applied to the portable electronic devices such as mobile phone, tablet computer and other a variety of use NVM chip (such as NAND
Flash memory) the electronic equipment for needing to store information.The application also provides a kind of storage control, including above-mentioned LDOC decoder.
LDPC interpretation method according to an embodiment of the present invention applies also for setting for the LDPC code that communication, magnetic storage, optical storage etc. use
Standby or service.
Although the example of present invention reference is described, it is intended merely to the purpose explained rather than to limit of the invention
System, the change to embodiment, increase and/or deletion can be made without departing from the scope of the present invention.
In the field benefited involved in these embodiments, from the description above with the introduction presented in associated attached drawing
Technical staff many modifications of the invention and other embodiments recorded here will be recognized.It should therefore be understood that this hair
It is bright to be not limited to disclosed specific embodiment, it is intended to will to modify and other embodiments include in the scope of the appended claims
It is interior.Although using specific term herein, them are only used on general significance and describing significance and not is
The purpose of limitation and use.
Claims (10)
1. a kind of LDPC interpretation method, comprising:
The variable node that first variable node memory stores is transferred to computing unit to generate the new value of the variable node；
The variable node that second variable node memory stores is transferred to verification unit to verify the variable node and be constituted
The legitimacy of LDPC code word；
If the LDPC code word constituted is legal, terminate iterative decoding；
If the LDPC code word constituted is illegal, the variable node generated by computing unit the first variable node of newly value update is deposited
Reservoir and the second variable node memory.
2. LDPC interpretation method according to claim 1, wherein in the first sub-stage of a wheel iterative decoding, by the
The variable node of the first row for being associated with check matrix of one variable node memory storage is transferred to computing unit, described in generation
The variable node of the first row is newly worth；
If the LDPC code word that verification unit verifying is constituted is illegal, update first is newly worth by the variable node of the first row
Variable node memory and the second variable node memory.
3. a kind of ldpc decoder, comprising: the first variable node memory, the second variable node memory, computing unit, verification
Unit and controller；
The controller instruction obtains variable node from the first variable node memory and is transferred to computing unit to generate the change
The new value of node is measured, and indicates to obtain variable node from the second variable node memory to be transferred to verification unit described to check
The legitimacy of variable node composition LDPC code word；
If the LDPC code word constituted is legal, controller indicates that iterative decoding terminates；
If the LDPC code word constituted is illegal, controller indicates that computing unit will generate variable node the first variable of newly value write-in
Node memory and the second variable node memory.
4. ldpc decoder according to claim 3, further includes: for storing the check node memory of check-node,
The controller instruction obtains check-node from check node memory and is transferred to computing unit, and computing unit is according to verification
Node and variable node are iterated decoding and generate the variable node new value that newly value and verification save.
5. ldpc decoder according to claim 4, wherein in initial phase, the controller is controlled with to be decoded
Code word initialize the first variable node memory and the second variable node memory, deposited with check matrix initiation verification node
Reservoir.
6. according to the described in any item ldpc decoders of claim 3 to 5, wherein the first variable node memory is double
Port store, read port are coupled to computing unit, to provide variable node to computing unit；Its write port is coupled to calculating
Unit is newly worth with the variable node generated to the first variable node memory write-in computing unit.
7. according to the described in any item ldpc decoders of claim 3 to 5, wherein the second variable node memory is double
Port store, read port are coupled to verification unit, to provide variable node to verification unit；Its write port is coupled to calculating
Unit is newly worth with the variable node generated to the second variable node memory write-in computing unit.
8. ldpc decoder according to claim 7, wherein the first variable node memory and the second variable node
Memory can transmission variables node outward simultaneously.
9. ldpc decoder according to claim 3, wherein in the first sub-stage of a wheel iterative decoding, the control
Device instruction processed is transferred to calculating list from the variable node that the first variable node memory obtains the first row for being associated with check matrix
Member, the variable node for generating the first row are newly worth；
If the LDPC code word that verification unit verifying is constituted is illegal, controller indicates newly to be worth with the variable node of the first row
Update the first variable node memory and the second variable node memory.
10. a kind of storage control, including the described in any item LDOC decoders of claim 3 to 9.
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| CN101478312A (en) * | 2008-12-15 | 2009-07-08 | 北京创毅视讯科技有限公司 | LDPC decoder and method for decoding implementation |
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| US20110138248A1 (en) * | 2009-12-09 | 2011-06-09 | National Chip Implementation Center National Applied Research Laboratories | Method for arranging memories of low-complexity ldpc decoder and low-complexity ldpc decoder using the same |
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