CN101478312A - LDPC decoder and method for decoding implementation - Google Patents

Abstract

The invention discloses a low-density parity check (LDPC) encoder and a method thereof for realizing coding. In the LDPC encoder, information of a variable node is refreshed by a currently participant check node after processing of each level is completed during the information transfer process; and the variable node also participates in other check nodes, so that a VCVNU unit uses the refreshed variable node information when processing the level including the other check nodes. Therefore, the variable node information is refreshed continuously between the levels, and the information transfer mechanism is different from the existing mechanism completely; the information transfer mechanism of the LDPC encoder utilizes the known information more fully, so the convergence speed is increased, less iteration times are used to complete the coding, decoding delay is reduced, and the decoding performance is enhanced at the same time. At the same time, a memory cell is saved to a great extent because C2V information is simplified greatly, thereby effectively saving the memory space.

Description

The method of a kind of ldpc decoder and realization decoding thereof

Technical field

The present invention relates to decoding technique, the method that refers to a kind of low-density checksum (LDPC, Low-DensityParity Check) decoder especially and realize deciphering.

Background technology

Utilize chnnel coding (error correcting code) to realize that error control is one of key technology in the radio digital communication.Traditional channel error correction coding mode mainly contains convolution code, RS block code etc.Low-density checksum LDPC sign indicating number is an application focus in recent years.

The LDPC sign indicating number is that a class has sparse parity check matrix, has the superperformance of approaching the Shannon limit.Decipher complexity than traditional convolution code and RS block code height though utilize the LDPC sign indicating number, but along with the improvement of decoding algorithm and the development of large scale integrated circuit level, the superperformance of LDPC sign indicating number has obtained paying attention to also having begun to be widely used in fields such as satellite communication, audio-video-frequency broadcast.At present, use the LDPC sign indicating number to comprise the system that meets mobile multimedia industry standard (CMMB), national standard of digital terrestrial broadcasting (DTTB), WiMAX802.16e, DVB-S2 etc. as the communication/broadcast system of channel decoding.

The LDPC sign indicating number can be represented that the line number p of matrix represents the check-node number by check matrix H, and columns v represents variable node number (or being called the information bit node).In the ldpc decoder course of work, information is transmitted between check-node and variable node, thereby makes the posterior probability information of variable node more reliably finish decoding by iteration repeatedly.In ldpc decoder, generally include the VNU unit, check-node unit (CNU, Check-Node Unit), control unit and memory cell.The information that variable node unit (VNU, Variable-Node Unit) is used to calculate from the variable node to the check-node is V2C information, upgrades the posterior information of self simultaneously, is equivalent to finish the row processing of check matrix; The information that the CNU unit is used to calculate from the check-node to the variable node is C2V information, is equivalent to finish the row processing of check matrix; Control unit is used to control whole decode procedure, comprises the input control of prior information, the control whether iteration continues, and the output control after the iteration end etc.; Memory cell can be divided into the initial prior information that memory set A and memory set B two parts: memory set A are used for preserving the input variable node, and the result of calculation that memory set B preserves in the iterative process is C2V information and V2C information.

The check matrix H of LDPC sign indicating number is a sparse matrix, and thousands of row and thousands of row are arranged usually.Each iteration need be finished the calculating of all row and all row, if adopt full serial to calculate then postpone excessively, if adopt full parallel computation then need more hardware resources, the framework that therefore adopts part parallel and part serial is a relatively reasonable manner.Under the framework of this string and combination, carry out parallel computation with one group of CNU unit, the set of the row of its processing is called a level course, and the CNU unit is successively handled until all row of traversal; Similarly, with one group of VNU unit to the row parallel computation, until the traversal all row.

CNU and VNU are the core calculations unit of ldpc decoder.In traditional ldpc decoder, the calculating of CNU and VNU is mutually independently, begin column processing again after promptly all row are handled, and the row that begins next iteration after in like manner all row are handled is again handled.Therefore the V2C information that C2V information that CNU calculates and VNU calculate need alternately be kept in the memory cell.

Fig. 1 a is in the prior art VNU computational process, calculates the schematic diagram of V2C information, as shown in Figure 1a, at first reads the prior information of variable node from memory set A, the C2V information that the CNU unit writes before reading from memory set B; After calculating was finished, Fig. 1 b was in the prior art VNU computational process, and the schematic diagram of storage V2C information shown in Fig. 1 b, is written back to the V2C information that obtains among the memory cell B.Fig. 1 a and Fig. 1 b have finished the computing of a perpendicular layers, and the VNU unit then repeats the process of Fig. 1 a and Fig. 1 b, finish the calculating of next perpendicular layers, and be processed intact until all row.The calculating of VNU is as shown in Equation (1):

Q _ji(k)＝f _v2c(λ _j，{R _i′j(k)|i′∈C[j]\i}) (1)

Wherein, λ _jIt is the initial input prior information of variable node j; R _{I ' j}(k) representative is passed to the C2V information of variable node j from check-node i ' in the k time iteration; Q _Ji(k) representative is passed to the V2C information of check-node i from variable node j in the k time iteration; C[j] set of the check-node that links to each other with variable node j of representative.

In whole VNU calculation stages, the CNU unit is idle.

Fig. 2 a is in the prior art CNU computational process, calculates the schematic diagram of C2V information, shown in Fig. 2 a, and after the VNU calculation stages is finished, in the CNU computing interval, the V2C information that the VNU unit writes before at first reading from memory set B; After calculating was finished, Fig. 2 b was in the prior art CNU computational process, and the schematic diagram of storage C2V information shown in Fig. 2 b, is written back to the C2V information that obtains in the memory cell.Fig. 2 a and Fig. 2 b have finished the computing of a level course, and the CNU unit then repeats the process of Fig. 2 a and Fig. 2 b, finish the calculating of next level course, and be processed intact until all row.The calculating of CNU is as shown in Equation (2):

R _ij(k)＝f _c2v({Q _j′i(k-1)|j′∈R[i]\j}) (2)

Wherein, R _Ij(k) representative is passed to the C2V information of variable node j from check-node i in the k time iteration; Q _{J ' i}(k) representative is passed to the V2C information of check-node i from variable node j ' in the k time iteration; R[i] set of the variable node that links to each other with check-node i of representative.

In whole C NU calculation stages, the VNU unit is idle.

After VNU and CNU calculation stages are all finished, if decoding is unsuccessful and iterations does not reach set upper limit, then control unit indication goes back to the VNU calculation stages, and iterations adds 1, and promptly each iteration all comprises a CNU calculation stages and a VNU calculation stages.

The whole decoding flow process of the above ldpc decoder as shown in Figure 3, Fig. 3 is the flow chart of prior art LDPC decoding, roughly is described below:

Step 300: initializing variable node prior information.

Step 301: judge whether all verification formulas are set up,, otherwise enter step 302 if set up then export decode results and process ends.

Step 302: whether iterations reaches the upper limit, if then export decode results and process ends, otherwise enters step 303.

Step 303～step 304: read next group C2V information row and variable node, carry out VNU and calculate.

Step 305: judge that whether all row calculate and finish, if enter step 306, otherwise return step 303.

Step 306～step 307: read next group V2C information row, carry out CNU and calculate.

Step 308: judge that whether all row calculate and finish, if enter step 309, otherwise return step 306.

Step 309: return step 301 after iterations adds one.

In the flow process shown in Figure 3, step 303～step 305 is a VNU computational process, whenever executes the computing of once just finishing a perpendicular layers, and step 306～step 308 is a CNU computational process, whenever executes the computing of once just finishing a level course.Specific implementation repeats no more here referring to the description to Fig. 1 a～Fig. 2 b.

In sum, in the existing ldpc decoder framework, CNU and VNU independently carry out.CNU is calculated, and the V2C information of using is all from last iteration VNU result calculated, and current up-to-date C2V information can't be upgraded variable node, thus the V2C information that can't obtain upgrading; In like manner, VNU is calculated, the C2V information of using also is all not use current up-to-date information from last iteration CNU result calculated.Because up-to-date information can't be used for iteration immediately, has influenced convergence rate,, existing LDPC needs many iterationses so realizing the method for decoding.

In addition, ldpc decoder need consume considerable memory cell.In check matrix, to element c _{I, j}=1, represent check-node i to link to each other with variable node j, bi-directional V2C that existing computational methods need replace on this edge and C2V information, from the above mentioned, these informational needs store in the memory cell.Therefore need in data quantity stored and the check matrix 1 number identical.With the CMMB1/2 code check is example, and check matrix is 4608 * 9216, and it is that each check-node links to each other with 6 variable nodes that each row has 61, therefore needs storage 4608 * 6 numbers.

Minimum-sum algorithm (Min-Sum) provides a kind of calculating C2V information approach of simplification, utilize this algorithm, C2V information that each row calculates can only be preserved 2 numbers, rather than in the Traditional calculating methods with every row in 1 number equate (this numerical value can be big more than 2 usually).Yet transmit under the framework in the information of existing ldpc decoder, carry out because CNU and VNU are alternately independent, memory cell also needs alternately to preserve respectively C2V information and V2C information, although the quantity of C2V information can be owing to adopting minimum-sum algorithm to be reduced, but the quantity of V2C information is constant, even the employing minimum-sum algorithm also can only be saved operand, can not save memory cell.

Summary of the invention

In view of this, main purpose of the present invention is to provide a kind of ldpc decoder, can accelerate convergence rate, reduces decoding and postpones, and saves memory cell simultaneously effectively.

Another object of the present invention is to provide a kind of decoder to realize the method for decoding, can accelerate convergence rate, reduce decoding and postpone, save memory cell simultaneously effectively.

For achieving the above object, technical scheme of the present invention specifically is achieved in that

A kind of low-density checksum ldpc decoder comprises control unit, memory cell and variable-verification-VCVNU unit, variable node unit at least, wherein,

Control unit is used to control whole decode procedure, comprises the input control of prior information, the control whether iteration continues, and the output control after the iteration end;

Memory cell comprises first memory group and second memory group: the first memory group is used for being kept at the information of the variable node that iterative process brings in constant renewal in; The second memory group is used to preserve the information that check-node sends variable node to;

The VCVNU unit is used for the row at check matrix, and variable node is carried out preliminary treatment, calculates the information transmission between variable node and the check-node and upgrades variable node.

Described VCVNU unit comprises the variable node pretreatment unit, the check information computing unit, and variable node updating block and register, wherein,

The variable node pretreatment unit, be used for reading check-node information corresponding to the current line of check matrix H from described second memory group, from described first memory group, read the variable node information that links to each other with these check-nodes, variable node is carried out preliminary treatment, the variable node information of handling is transmitted to the check information computing unit, simultaneously it is kept in the register;

The check information computing unit is used to finish the C2V information calculations of check-node to variable node, and is saved in the described second memory group as the check information of current check row; Simultaneously, C2V information is forwarded to the variable node updating block with the variable node information that is kept in the register;

The variable node updating block is used for finishing variable node and upgrades computing and return and deposit described first memory group.

Described VCVNU adopts improved minimum-sum algorithm in the unit, obtains the least absolute value and time least absolute value of each check row in the V2C information; Utilize the sign bit of the least absolute value of each check row, inferior least absolute value, each V2C information again, and the serial number information of minimum value, C2V information obtained, to calculate the information transmission between described variable node and the check-node.

The least absolute value of each check row and time least absolute value are respectively in the described V2C of the obtaining information:

Least absolute value C _{I, min}(k)=α * min (| Q _Ji(k) |, j ∈ R[i]);

Inferior least absolute value C _{I, 2min}(k)=α * min (| Q _{J ' i}(k) |, j ' ∈ R[i] j _Min);

Wherein, R _Ij(k) representative is passed to the C2V information of variable node j from check-node i in the k time iteration; Q _Ji(k) representative is passed to the V2C information of check-node i from variable node j in the k time iteration; α is a modifying factor, and its value is less than 1 constant, such as 0.8 greater than 0; R[i] set of the variable node that links to each other with check-node i of representative; j _MinBe corresponding to minimum | Q _Ji(k) | sequence number.

The described C2V of obtaining information is specially:

$R_{\mathrm{ij}}\left(k\right)=\left\{\begin{array}{c}{S}_i\left(k\right)*\mathrm{sign}\left(Q_{\mathrm{ji}}\left(k\right)\right)*C_{i,\min }\left(k\right),\∀j\∈R\left[i\right]\backslash j_{\min }\\ S_i\left(k\right)*\mathrm{sign}\left(Q_{\mathrm{ji}}\left(k\right)\right)*C_{i,2\min }\left(k\right),j=j_{\min }\end{array}\right.$

Wherein, $S_i\left(k\right)=\underset{j\∈R\left[i\right]}{\mathrm{\Π}}\mathrm{sign}\left(Q_{\mathrm{ji}}\left(k\right)\right)$ Sign () represents sign bit.

Described renewal variable node is specially: λ _j=Q _Ji(k)+R _Ij(k), wherein, λ _jFor being kept at the variable information of the variable node j in the described first memory group.

A kind of ldpc decoder is realized the method for decoding, and based on the described decoder of claim 1, in each iterative process, this method comprises:

Read the capable and correlated variables node of next group check information, variable node is carried out preliminary treatment;

Calculate the information transmission between variable node and the check-node and upgrade variable node; Finish until all row calculating.

Described next group check information is capable to be check-node information corresponding to the current line of check matrix; Described correlated variables node is the variable node information that links to each other with these check-nodes.

Describedly variable node is carried out pretreated method be: utilize variable information to deduct check information is passed to the variable node that is attached thereto corresponding to this check-node in last once iteration information.

The method of the information transmission between described calculating variable node and the check-node is:

Adopt improved minimum-sum algorithm, obtain the least absolute value and time least absolute value of each check row in the V2C information;

Utilize the sign bit of the least absolute value of each check row, inferior least absolute value, each V2C information, and the serial number information of minimum value, C2V information obtained.

The least absolute value of each check row and time least absolute value are respectively in the described V2C of the obtaining information:

Least absolute value C _{I, min}(k)=α * min (| Q _Ji(k) |, j ∈ R[i]);

Inferior least absolute value C _{I, 2mm}(k)=α * min (| Q _{J ' i}(k) |, j ' ∈ R[i] j _Min);

Wherein, R _Ij(k) representative is passed to the C2V information of variable node j from check-node i in the k time iteration; Q _Ji(k) representative is passed to the V2C information of check-node i from variable node j in the k time iteration; α is a modifying factor, and its value is less than 1 constant, such as 0.8 greater than 0; R[i] set of the variable node that links to each other with check-node i of representative; j _MinBe corresponding to minimum | Q _Ji(k) | sequence number.

The described C2V of obtaining information is specially:

$R_{\mathrm{ij}}\left(k\right)=\left\{\begin{array}{c}{S}_i\left(k\right)*\mathrm{sign}\left(Q_{\mathrm{ji}}\left(k\right)\right)*C_{i,\min }\left(k\right),\∀j\∈R\left[i\right]\backslash j_{\min }\\ S_i\left(k\right)*\mathrm{sign}\left(Q_{\mathrm{ji}}\left(k\right)\right)*C_{i,2\min }\left(k\right),j=j_{\min }\end{array}\right.$

Wherein, $S_i\left(k\right)=\underset{j\∈R\left[i\right]}{\mathrm{\Π}}\mathrm{sign}\left(Q_{\mathrm{ji}}\left(k\right)\right)$ Sign () represents sign bit.

Described renewal variable node is specially: λ _j=Q _Ji(k)+R _Ij(k), wherein, λ _jVariable information for the variable node j that preserves.

As seen from the above technical solution, ldpc decoder of the present invention is in information exchanging process, after each layer is handled, variable node information all can be upgraded by the check-node of current participation, because variable node has also participated in other check-nodes, therefore when with in iteration, when the VCVNU cell processing when comprising the layer of other check-nodes, with the variable node information of using after the renewal.This shows, variable node information is brought in constant renewal at the interlayer with an iteration, this information transmission mechanism is with existing complete different, information transmission mechanism of the present invention has utilized Given information more fully, thereby improved convergence rate, finish decoding with iterations still less, reduced decoding and postponed, strengthened decoding performance simultaneously.Simultaneously, because the simplification greatly of C2V information makes that memory cell has obtained saving significantly, thereby has saved memory space effectively.

Description of drawings

Fig. 1 a is in the prior art VNU computational process, calculates the schematic diagram of V2C information;

Fig. 1 b is in the prior art VNU computational process, the schematic diagram of storage V2C information;

Fig. 2 a is in the prior art CNU computational process, calculates the schematic diagram of C2V information;

Fig. 2 b is in the prior art CNU computational process, the schematic diagram of storage C2V information;

Fig. 3 is the flow chart of prior art LDPC decoding;

Fig. 4 is the composition structural representation of ldpc decoder of the present invention;

Fig. 5 is the pretreated schematic diagram of the present invention;

Fig. 6 is the schematic diagram that the present invention stores the preliminary treatment result;

Fig. 7 is that the present invention realizes the schematic diagram that check information calculates;

Fig. 8 is that the present invention realizes the schematic diagram that variable node upgrades;

Fig. 9 is the flow chart that ldpc decoder of the present invention is realized decoding.

Embodiment

For making purpose of the present invention, technical scheme and advantage clearer, below with reference to the accompanying drawing embodiment that develops simultaneously, the present invention is described in more detail.

Fig. 4 is the composition structural representation of ldpc decoder of the present invention, as shown in Figure 4, ldpc decoder of the present invention comprises control unit, memory cell and variable-verification-variable node unit (VCVNU, Variable-Check-Variable Nodes Unit) at least, wherein

Control unit is used to control whole decode procedure, comprises the input control of prior information, the control whether iteration continues, and the output control after the iteration end etc.Its function and composition and existing decoder basically identical.

Memory cell comprises first memory group and second memory group two parts.The first memory group is used to preserve the information of variable node, constitutes with the memory of existing ldpc decoder different to be: the variable node information that first memory is preserved is brought in constant renewal in iterative process, and is not to preserve initial prior information always; The second memory group is used to preserve the information that check-node sends variable node to, i.e. C2V information.

The VCVNU unit is used for the row at check matrix, and variable node is carried out preliminary treatment, calculates the information transmission between variable node and the check-node and upgrades variable node.VCVNU can be divided into three subelements: variable node pretreatment unit, check information computing unit and variable node updating block.Ldpc decoder of the present invention uses level course of one group of VCVNU unit parallel processing, i.e. the row of a collection of check matrix H, and the variable node after the renewal is used for the processing of next level course.

In the existing LDPC decoding, the VNU unit is used for calculating V2C information, and the CNU unit is used for calculating C2V information, and the VNU unit is carried out respectively in the different stages separately with the CNU unit.And the present invention uses the mode of intelligence transmission of upgrading variable node information between level course.

Decoder has been taked the strategy of variable node information immediate updating among the present invention, and C2V information is used to upgrade variable node information immediately, no longer includes special VNU calculation stages, so the second memory group is not used further to preserve V2C information yet.

Below in conjunction with Fig. 5～Fig. 8, introduce the operation principle of ldpc decoder of the present invention in detail.

Fig. 5 is the pretreated schematic diagram of the present invention, as shown in Figure 5, variable node pretreatment unit in the VCVNU unit, from the second memory group, read check-node information, from the first memory group, read the variable node information that links to each other with these check-nodes corresponding to the current line of check matrix H.

The variable node information that reads from the first memory group for the first time is the initial prior information of variable node.

Fig. 6 is the pretreated schematic diagram of the present invention, as shown in Figure 6, carries out the variable node preliminary treatment at the variable node pretreatment unit, and the variable node information of handling is transmitted to the check information computing unit, simultaneously it is kept in the register.Because the check information that reads from the second memory group is passed to the information of the variable node that is attached thereto corresponding to this check-node in last once iteration, therefore, preliminary treatment is exactly earlier this part information to be deducted.

Still use λ _jRepresentative is kept at the variable information of the variable node j in the first memory group, need to prove the λ here _jOnly when the decoding beginning, be initialized as the initial prior information of variable node, in iterative process, bring in constant renewal in afterwards.The variable node preliminary treatment can be expressed as follows with formula (3):

Q _ji(k)＝λ _j-R _ij(k-1) (3)

Wherein, R _Ij(k) representative is passed to the C2V information of variable node j from check-node i in the k time iteration; Q _Ji(k) representative is passed to the V2C information of check-node i from variable node j in the k time iteration.

Fig. 7 is that the present invention realizes the schematic diagram that check information calculates, and as shown in Figure 7, the check information computing unit is used to finish the C2V information calculations of check-node to variable node, and this part information is saved in the second memory group as the check information of current check row; Simultaneously, C2V information is forwarded to the variable node updating block with the variable node information that is kept in the register.

The algorithm that obtains C2V information has multiple algorithm, in order to save memory, can adopt improved minimum-sum algorithm, by this algorithm computation and preserve the variable node number of two absolute value minimums and the sign bit of each variable node.Calculate by Q respectively following formula (4) and (5) _Ji(k) least absolute value in Dai Biao the V2C information and time least absolute value:

C _i，min(k)＝α*min(|Q _ji(k)|，j∈R[i]) (4)

C _i，2min(k)＝α*min(|Q _j′i(k)|，j′∈R[i]\j _min) (5)

Wherein, α is a modifying factor, and its value is less than 1 constant, such as 0.8 greater than 0; R[i] set of the variable node that links to each other with check-node i of representative; j _MinBe corresponding to minimum | Q _Ji(k) | sequence number.

Among the present invention,, reduced decoding and postponed, strengthened decoding performance because convergence rate has been accelerated in the introducing of modifying factor α.

Calculate C2V information as shown in Equation (6):

$R_{\mathrm{ij}}\left(k\right)=\left\{\begin{array}{c}{S}_i\left(k\right)*\mathrm{sign}\left(Q_{\mathrm{ji}}\left(k\right)\right)*C_{i,\min }\left(k\right),\∀j\∈R\left[i\right]\backslash j_{\min }\\ S_i\left(k\right)*\mathrm{sign}\left(Q_{\mathrm{ji}}\left(k\right)\right)*C_{i,2\min }\left(k\right),j=j_{\min }\end{array}\right.---\left(6\right)$

Wherein, $S_i\left(k\right)=\underset{j\∈R\left[i\right]}{\mathrm{\Π}}\mathrm{sign}\left(Q_{\mathrm{ji}}\left(k\right)\right),$ Sign () represents sign bit.

This shows that under minimum-sum algorithm, C2V information can be reduced to: each check row is only preserved the sign bit of least absolute value, inferior least absolute value, each V2C information, and the serial number information of minimum value gets final product.And the information that the algorithm of existing calculating C2V information need calculate and preserve all variable nodes that link to each other with this check-node, and usually the variable node that connects of each check-node more than 6 or 6, therefore say, among the present invention, because C2V information has obtained simplifying greatly, so the second memory group has obtained saving significantly, thereby has saved memory space effectively.

Fig. 8 is that the present invention realizes the schematic diagram that variable node upgrades, and as shown in Figure 8, the variable node updating block is used for finishing variable node renewal computing and returns and deposit the first memory group.The realization of variable node updating block can be expressed as shown in the formula (7):

λ _j＝Q _ji(k)+R _ij(k) (7)

So far, the row of the intact one group of check matrix of VCVNU cell processing, or be called one deck.The processing of this level course has not comprised singly that the row of check-node calculates, and has also upgraded the information of variable node.Subsequently, under the control of control unit, VCVNU unit and memory cell turn to down one deck, repeat the processing procedure of three subelements in the VCVNU unit, promptly finish iteration one time until all capable disposing of all check matrixes.

Describe as seen from the operation principle of ldpc decoder of the present invention, in information exchanging process, after each layer is handled, variable node information all can be upgraded by the check-node of current participation, because variable node has also participated in other check-nodes, therefore when the VCVNU cell processing to comprise other check-nodes layer time, with the variable node information of using after the renewal.This shows, variable node information is brought in constant renewal at interlayer, this information transmission mechanism is with existing complete different, information transmission mechanism of the present invention has utilized Given information more fully, thereby improved convergence rate, finish decoding with iterations still less, reduced decoding and postponed, strengthened decoding performance simultaneously.Simultaneously, because the simplification greatly of C2V information makes that memory cell has obtained saving significantly, thereby has saved memory space effectively.

Fig. 9 is the flow chart that ldpc decoder of the present invention is realized decoding, and as shown in Figure 9, the present invention's decoding may further comprise the steps:

Step 900: initializing variable node prior information.

Step 901: judge whether all verification formulas are set up,, otherwise enter step 902 if set up then export decode results and process ends.

Step 902: whether iterations reaches the upper limit, if then export decode results and process ends, otherwise enters step 903.

Here, the realization of step 900～step 902 belongs to technology as well known to those skilled in the art, and is in full accord with step 300～step 303, no longer describes in detail here.

Step 903: read the capable and correlated variables node of next group check information.

Next group check information is capable to be check-node information corresponding to the current line of check matrix H, and the correlated variables node is the variable node information that links to each other with these check-nodes.

Step 904: variable node is carried out preliminary treatment.The variable node preliminary treatment is exactly to utilize variable information to deduct check information to pass to the information of the variable node that is attached thereto corresponding to this check-node in last once iteration, and available preamble formula (3) is realized.

Step 905: carry out CNU and calculate.

This step is used to finish the C2V information calculations of check-node to variable node, the algorithm that obtains C2V information has multiple algorithm, in order to save memory, can adopt improved minimum-sum algorithm, by this algorithm computation and preserve the variable node number of two absolute value minimums and the sign bit of each variable node.Specific implementation can be referring to preamble formula (6).

Step 906: variable node is upgraded.Specific implementation can be referring to preamble formula (7).

Step 907: judge that whether all row calculate and finish, if enter step 908, otherwise return step 903.

Step 908: return step 901 after iterations adds one.

In the flow process shown in Figure 9, step 903～step 907 is a VCVNU computational process, and every execution is once just finished going of one group of check matrix or is called the processing of one deck.Specific implementation repeats no more here referring to the description to Fig. 1 a～Fig. 2 b.

The above is preferred embodiment of the present invention only, is not to be used to limit protection scope of the present invention.Within the spirit and principles in the present invention all, any modification of being done, be equal to and replace and improvement etc., all should be included within protection scope of the present invention.

Claims (13)

1. a low-density checksum ldpc decoder is characterized in that, comprises control unit, memory cell and variable-verification-VCVNU unit, variable node unit at least, wherein,

Control unit is used to control whole decode procedure, comprises the input control of prior information, the control whether iteration continues, and the output control after the iteration end;

Memory cell comprises first memory group and second memory group: the first memory group is used for being kept at the information of the variable node that iterative process brings in constant renewal in; The second memory group is used to preserve the information that check-node sends variable node to;

The VCVNU unit is used for the row at check matrix, and variable node is carried out preliminary treatment, calculates the information transmission between variable node and the check-node and upgrades variable node.

2. ldpc decoder according to claim 1 is characterized in that, described VCVNU unit comprises the variable node pretreatment unit, the check information computing unit, and variable node updating block and register, wherein,

The variable node pretreatment unit, be used for reading check-node information corresponding to the current line of check matrix H from described second memory group, from described first memory group, read the variable node information that links to each other with these check-nodes, variable node is carried out preliminary treatment, the variable node information of handling is transmitted to the check information computing unit, simultaneously it is kept in the register;

The check information computing unit is used to finish the C2V information calculations of check-node to variable node, and is saved in the described second memory group as the check information of current check row; Simultaneously, C2V information is forwarded to the variable node updating block with the variable node information that is kept in the register;

The variable node updating block is used for finishing variable node and upgrades computing and return and deposit described first memory group.

3. ldpc decoder according to claim 1 is characterized in that, described VCVNU adopts improved minimum-sum algorithm in the unit, obtains the least absolute value and time least absolute value of each check row in the V2C information; Utilize the sign bit of the least absolute value of each check row, inferior least absolute value, each V2C information again, and the serial number information of minimum value, C2V information obtained, to calculate the information transmission between described variable node and the check-node.

4. ldpc decoder according to claim 3 is characterized in that, the least absolute value of each check row and time least absolute value are respectively in the described V2C of the obtaining information:

Least absolute value C _{I, min}(k)=α * min (| Q _Ji(k) |, j ∈ R[i]);

Inferior least absolute value C _{I, 2min}(k)=α * min (| Q _{J ' i}(k) |, j ' ∈ R[i] j _Min);

Wherein, R _Ij(k) representative is passed to the C2V information of variable node j from check-node i in the k time iteration; Q _Ji(k) representative is passed to the V2C information of check-node i from variable node j in the k time iteration; α is a modifying factor, and its value is less than 1 constant, such as 0.8 greater than 0; R[i] set of the variable node that links to each other with check-node i of representative; j _MinBe corresponding to minimum | Q _Ji(k) | sequence number.

5. ldpc decoder according to claim 4 is characterized in that, the described C2V of obtaining information is specially:

$R_{\mathrm{ij}}\left(k\right)=\left\{\begin{array}{c}{S}_i\left(k\right)*\mathrm{sign}\left(Q_{\mathrm{ji}}\left(k\right)\right)*C_{i,\min }\left(k\right),\∀j\∈R\left[i\right]\backslash j_{\min }\\ S_i\left(k\right)*\mathrm{sign}\left(Q_{\mathrm{ji}}\left(k\right)\right)*C_{i,2\min }\left(k\right),j=j_{\min }\end{array}\right.$

Wherein, $S_i\left(k\right)=\underset{j\∈R\left[i\right]}{\mathrm{\Π}}\mathrm{sign}\left(Q_{\mathrm{ji}}\left(k\right)\right)$ Sign () represents sign bit.

6. ldpc decoder according to claim 5 is characterized in that, described renewal variable node is specially: λ _j=Q _Ji(k)+R _Ij(k), wherein, λ _jFor being kept at the variable information of the variable node j in the described first memory group.

7. the method that ldpc decoder is realized deciphering based on the described decoder of claim 1, is characterized in that, in each iterative process, this method comprises:

Read the capable and correlated variables node of next group check information, variable node is carried out preliminary treatment;

Calculate the information transmission between variable node and the check-node and upgrade variable node; Finish until all row calculating.

8. method according to claim 7 is characterized in that, described next group check information is capable to be check-node information corresponding to the current line of check matrix; Described correlated variables node is the variable node information that links to each other with these check-nodes.

9. method according to claim 7, its characteristic value be, describedly variable node is carried out pretreated method is: utilize variable information to deduct check information is passed to the variable node that is attached thereto corresponding to this check-node in last once iteration information.

10. method according to claim 7 is characterized in that, the method for the information transmission between described calculating variable node and the check-node is:

Adopt improved minimum-sum algorithm, obtain the least absolute value and time least absolute value of each check row in the V2C information;

Utilize the sign bit of the least absolute value of each check row, inferior least absolute value, each V2C information, and the serial number information of minimum value, C2V information obtained.

11. method according to claim 10 is characterized in that, the least absolute value of each check row and time least absolute value are respectively in the described V2C of the obtaining information:

Least absolute value C _{I, min}(k)=α * min (| Q _Ji(k) |, j ∈ R[i]);

Inferior least absolute value C _{I, 2min}(k)=α * min (| Q _{J ' i}(k) |, j ' ∈ R[i] j _Min);

Wherein, R _Ij(k) representative is passed to the C2V information of variable node j from check-node i in the k time iteration; Q _Ji(k) representative is passed to the V2C information of check-node i from variable node j in the k time iteration; α is a modifying factor, and its value is less than 1 constant, such as 0.8 greater than 0; R[i] set of the variable node that links to each other with check-node i of representative; j _MinBe corresponding to minimum | Q _Ji(k) | sequence number.

12. method according to claim 11 is characterized in that, the described C2V of obtaining information is specially:

$R_{\mathrm{ij}}\left(k\right)=\left\{\begin{array}{c}{S}_i\left(k\right)*\mathrm{sign}\left(Q_{\mathrm{ji}}\left(k\right)\right)*C_{i,\min }\left(k\right),\∀j\∈R\left[i\right]\backslash j_{\min }\\ S_i\left(k\right)*\mathrm{sign}\left(Q_{\mathrm{ji}}\left(k\right)\right)*C_{i,2\min }\left(k\right),j=j_{\min }\end{array}\right.$

Wherein, $S_i\left(k\right)=\underset{j\∈R\left[i\right]}{\mathrm{\Π}}\mathrm{sign}\left(Q_{\mathrm{ji}}\left(k\right)\right)$ Sign () represents sign bit.

13. method according to claim 12 is characterized in that, described renewal variable node is specially: λ _j=Q _Ji(k)+R _Ij(k), wherein, λ _jVariable information for the variable node j that preserves.

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