CN110379859A - A kind of thin film transistor (TFT), preparation method and electronic device - Google Patents
A kind of thin film transistor (TFT), preparation method and electronic device Download PDFInfo
- Publication number
- CN110379859A CN110379859A CN201910669616.0A CN201910669616A CN110379859A CN 110379859 A CN110379859 A CN 110379859A CN 201910669616 A CN201910669616 A CN 201910669616A CN 110379859 A CN110379859 A CN 110379859A
- Authority
- CN
- China
- Prior art keywords
- layer
- graphene
- silicon
- substrate
- tft
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 42
- 238000002360 preparation method Methods 0.000 title claims abstract description 27
- 229910021389 graphene Inorganic materials 0.000 claims abstract description 172
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 167
- 239000010703 silicon Substances 0.000 claims abstract description 167
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 166
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims abstract description 149
- 239000000758 substrate Substances 0.000 claims abstract description 89
- 238000009413 insulation Methods 0.000 claims abstract description 37
- 239000010410 layer Substances 0.000 claims description 717
- 229910052718 tin Inorganic materials 0.000 claims description 86
- -1 tin alkene Chemical class 0.000 claims description 83
- 239000013078 crystal Substances 0.000 claims description 80
- 238000000034 method Methods 0.000 claims description 44
- 229910052751 metal Inorganic materials 0.000 claims description 37
- 239000002184 metal Substances 0.000 claims description 37
- 239000011888 foil Substances 0.000 claims description 32
- 238000000151 deposition Methods 0.000 claims description 29
- 238000005229 chemical vapour deposition Methods 0.000 claims description 26
- 230000008021 deposition Effects 0.000 claims description 26
- 239000013081 microcrystal Substances 0.000 claims description 19
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 15
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 15
- 239000002356 single layer Substances 0.000 claims description 13
- 238000000137 annealing Methods 0.000 claims description 12
- 229920005591 polysilicon Polymers 0.000 claims description 11
- 239000010408 film Substances 0.000 claims description 10
- 150000002500 ions Chemical class 0.000 claims description 10
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 229910021424 microcrystalline silicon Inorganic materials 0.000 claims description 7
- 238000005566 electron beam evaporation Methods 0.000 claims description 6
- 230000002708 enhancing effect Effects 0.000 claims description 4
- 238000000407 epitaxy Methods 0.000 claims 1
- 238000005303 weighing Methods 0.000 claims 1
- 238000005516 engineering process Methods 0.000 abstract description 2
- 125000005842 heteroatom Chemical group 0.000 abstract description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N Alumina Chemical compound [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 15
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 12
- 230000000052 comparative effect Effects 0.000 description 10
- 230000000694 effects Effects 0.000 description 10
- 150000001336 alkenes Chemical class 0.000 description 9
- 239000011889 copper foil Substances 0.000 description 8
- 230000007547 defect Effects 0.000 description 8
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 7
- 239000004810 polytetrafluoroethylene Substances 0.000 description 7
- 229920001343 polytetrafluoroethylene Polymers 0.000 description 7
- XKRFYHLGVUSROY-UHFFFAOYSA-N argon Substances [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 6
- 239000002887 superconductor Substances 0.000 description 6
- 239000004372 Polyvinyl alcohol Substances 0.000 description 5
- 229910052786 argon Inorganic materials 0.000 description 5
- 239000010949 copper Substances 0.000 description 5
- 239000007789 gas Substances 0.000 description 5
- 239000010931 gold Substances 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 229920002451 polyvinyl alcohol Polymers 0.000 description 5
- 239000004575 stone Substances 0.000 description 5
- 239000011651 chromium Substances 0.000 description 4
- 238000001312 dry etching Methods 0.000 description 4
- 239000004926 polymethyl methacrylate Substances 0.000 description 4
- 230000001681 protective effect Effects 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 239000010936 titanium Substances 0.000 description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 3
- 239000004696 Poly ether ether ketone Substances 0.000 description 3
- 239000004695 Polyether sulfone Substances 0.000 description 3
- 239000004743 Polypropylene Substances 0.000 description 3
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 3
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 3
- 238000000576 coating method Methods 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 229910002804 graphite Inorganic materials 0.000 description 3
- 239000010439 graphite Substances 0.000 description 3
- 239000001257 hydrogen Substances 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 description 3
- 239000000203 mixture Substances 0.000 description 3
- 239000005543 nano-size silicon particle Substances 0.000 description 3
- 229920003229 poly(methyl methacrylate) Polymers 0.000 description 3
- 229920006393 polyether sulfone Polymers 0.000 description 3
- 229920002530 polyetherether ketone Polymers 0.000 description 3
- 229920000139 polyethylene terephthalate Polymers 0.000 description 3
- 239000005020 polyethylene terephthalate Substances 0.000 description 3
- 239000011241 protective layer Substances 0.000 description 3
- 229910000077 silane Inorganic materials 0.000 description 3
- 238000004544 sputter deposition Methods 0.000 description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 2
- 229910052779 Neodymium Inorganic materials 0.000 description 2
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- UMIVXZPTRXBADB-UHFFFAOYSA-N benzocyclobutene Chemical compound C1=CC=C2CCC2=C1 UMIVXZPTRXBADB-UHFFFAOYSA-N 0.000 description 2
- 229910052799 carbon Inorganic materials 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 2
- 239000004205 dimethyl polysiloxane Substances 0.000 description 2
- 235000013870 dimethyl polysiloxane Nutrition 0.000 description 2
- 150000002148 esters Chemical class 0.000 description 2
- 238000004050 hot filament vapor deposition Methods 0.000 description 2
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 238000001755 magnetron sputter deposition Methods 0.000 description 2
- 238000001451 molecular beam epitaxy Methods 0.000 description 2
- 229910052750 molybdenum Inorganic materials 0.000 description 2
- 239000011733 molybdenum Substances 0.000 description 2
- QEFYFXOXNSNQGX-UHFFFAOYSA-N neodymium atom Chemical compound [Nd] QEFYFXOXNSNQGX-UHFFFAOYSA-N 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 229920000435 poly(dimethylsiloxane) Polymers 0.000 description 2
- 229920003207 poly(ethylene-2,6-naphthalate) Polymers 0.000 description 2
- 239000004417 polycarbonate Substances 0.000 description 2
- 239000011112 polyethylene naphthalate Substances 0.000 description 2
- 229920006375 polyphtalamide Polymers 0.000 description 2
- 229920001155 polypropylene Polymers 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- 239000004332 silver Substances 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 229910052719 titanium Inorganic materials 0.000 description 2
- 238000007738 vacuum evaporation Methods 0.000 description 2
- 229910017083 AlN Inorganic materials 0.000 description 1
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 1
- 229920002799 BoPET Polymers 0.000 description 1
- 239000005041 Mylar™ Substances 0.000 description 1
- 206010051986 Pneumatosis Diseases 0.000 description 1
- 239000004952 Polyamide Substances 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 239000004954 Polyphthalamide Substances 0.000 description 1
- 239000004793 Polystyrene Substances 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 239000010953 base metal Substances 0.000 description 1
- STTCDNLESVYWPH-UHFFFAOYSA-N benzene-1,4-diamine;terephthalic acid Chemical compound NC1=CC=C(N)C=C1.OC(=O)C1=CC=C(C(O)=O)C=C1 STTCDNLESVYWPH-UHFFFAOYSA-N 0.000 description 1
- 239000003153 chemical reaction reagent Substances 0.000 description 1
- 229940114081 cinnamate Drugs 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000002322 conducting polymer Substances 0.000 description 1
- 229920001940 conductive polymer Polymers 0.000 description 1
- 229910021419 crystalline silicon Inorganic materials 0.000 description 1
- 229920005565 cyclic polymer Polymers 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 125000000118 dimethyl group Chemical group [H]C([H])([H])* 0.000 description 1
- 238000003618 dip coating Methods 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 229910052736 halogen Inorganic materials 0.000 description 1
- 150000002367 halogens Chemical class 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- 150000002466 imines Chemical class 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000007641 inkjet printing Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 150000004702 methyl esters Chemical class 0.000 description 1
- 238000000813 microcontact printing Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 239000002159 nanocrystal Substances 0.000 description 1
- 239000002086 nanomaterial Substances 0.000 description 1
- HURSIASBWGCKKE-UHFFFAOYSA-N naphthalene naphthalene-1-carboxylic acid Chemical compound C1(=CC=CC2=CC=CC=C12)C(=O)O.C1=CC=CC2=CC=CC=C12 HURSIASBWGCKKE-UHFFFAOYSA-N 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- CXQXSVUQTKDNFP-UHFFFAOYSA-N octamethyltrisiloxane Chemical compound C[Si](C)(C)O[Si](C)(C)O[Si](C)(C)C CXQXSVUQTKDNFP-UHFFFAOYSA-N 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 238000004987 plasma desorption mass spectroscopy Methods 0.000 description 1
- 229920002647 polyamide Polymers 0.000 description 1
- 229920000515 polycarbonate Polymers 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 239000002994 raw material Substances 0.000 description 1
- 239000012495 reaction gas Substances 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 150000004756 silanes Chemical class 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229920005573 silicon-containing polymer Polymers 0.000 description 1
- 239000002002 slurry Substances 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 238000005507 spraying Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000004408 titanium dioxide Substances 0.000 description 1
- WBYWAXJHAXSJNI-VOTSOKGWSA-M trans-cinnamate Chemical compound [O-]C(=O)\C=C\C1=CC=CC=C1 WBYWAXJHAXSJNI-VOTSOKGWSA-M 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 229920002554 vinyl polymer Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
- H01L29/161—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys
- H01L29/165—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System including two or more of the elements provided for in group H01L29/16, e.g. alloys in different semiconductor regions, e.g. heterojunctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78684—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising semiconductor materials of Group IV not being silicon, or alloys including an element of the group IV, e.g. Ge, SiN alloys, SiC alloys
Abstract
The application provides a kind of thin film transistor (TFT), preparation method and electronic device, belongs to electronics and photoelectron field of display technology.Thin film transistor (TFT) includes substrate, active layer, source layer, drain electrode layer, gate insulation layer and grid layer.Active layer is graphene hetero structure layers, and graphene hetero structure layers include the graphene layer and silicon layer of overlapping, and graphene layer or silicon layer are located at the surface of substrate.The surface that source layer and drain electrode layer are located at substrate makes graphene hetero structure layers between source layer and drain electrode layer.Gate insulation layer is located at the position not covered by source layer, drain electrode layer and graphene hetero structure layers on the surface on the surface and substrate away from substrate of source layer, drain electrode layer and graphene hetero structure layers.Grid layer is located at the surface away from substrate of gate insulation layer.The active layer of this thin film transistor (TFT) is the hetero structure layers that graphene layer and silicon layer are formed, and makes electron transport ability more preferably, the electric property of obtained thin film transistor (TFT) is more preferable.
Description
Technical field
This application involves electronics and photoelectron field of display technology, in particular to a kind of thin film transistor (TFT), its preparation
Method and electronic device.
Background technique
Graphene is as representative two-dimension nano materials with its excellent physics and architectural characteristic in electronics, sensing
It is received significant attention with fields such as photoelectric devices, although the carrier mobility with superelevation, graphene layer are preparing film
It is easily damaged during transistor, it, can be to the electric property of thin film transistor (TFT) if do not repaired to graphene layer
Cause adverse effect.
Summary of the invention
The application's is designed to provide a kind of thin film transistor (TFT), preparation method and electronic device, and it is different to form graphene
Matter structure improves the electric property of thin film transistor (TFT).
In a first aspect, the embodiment of the present application provides a kind of thin film transistor (TFT), including substrate, active layer, source layer, drain electrode
Layer, gate insulation layer and grid layer.Active layer is graphene hetero structure layers, and graphene hetero structure layers include graphene layer and silicon
Crystal layer, graphene layer or silicon layer are located at the surface of substrate.The surface that source layer and drain electrode layer are located at substrate keeps graphene heterogeneous
Structure sheaf is between source layer and drain electrode layer.Gate insulation layer is located at the back of source layer, drain electrode layer and graphene hetero structure layers
The position not covered by source layer, drain electrode layer and graphene hetero structure layers on the surface on surface and substrate from substrate.Grid
Pole layer is located at the surface away from substrate of gate insulation layer.
Silicon layer plays the role of to graphene layer reparation and protection, and after silicon layer and graphene layer cooperation, can
Collectively as active layer, keep carrier transport effect more preferable, after gate insulation layer and grid layer cooperation, obtained film crystal
The electric property of pipe is more preferably.
With reference to first aspect, in another embodiment, graphene hetero structure layers include the graphene layer being successively overlapped, silicon
Crystal layer and tin alkene layer, graphene layer or tin alkene layer are located at the surface of substrate.
Graphene hetero structure layers form superconductor-semiconductor-superconductor active layer structure, can be improved electron-transport
Efficiency, and silicon layer sheet can repair the defect of graphene layer as semiconductor, can also be used as the protective layer of graphene layer,
At the same time as the substrate of tin alkene layer deposition, the electric property of thin film transistor (TFT) is enable to effectively improve.
With reference to first aspect, in another embodiment, graphene layer is single-layer graphene, and tin alkene layer is single layer tin alkene.It is single
Layer graphene with a thickness of 0.3-0.4nm, single layer tin alkene with a thickness of 0.4-0.6nm, single-layer graphene and single layer tin alkene are set
It is little to the thickness effect of active layer after layer, and graphene layer and tin alkene layer are used as superconductor, after cooperating with silicon layer,
The electron-transport effect of obtained active layer is more preferable.
With reference to first aspect, in another embodiment, silicon layer is non-monocrystal silicon layer.Silicon layer is non-monocrystal silicon layer knot
Structure is easy preparation, during forming silicon layer, will not damage to single-layer graphene, and can be to single-layer graphene
It is repaired and is protected, keep the electron-transport effect of active layer more preferable.
With reference to first aspect, in another embodiment, non-monocrystal silicon layer includes microcrystal silicon layer, polysilicon layer and nanometer silicon layer
It is one or more.
With reference to first aspect, in another embodiment, silicon layer includes the first crystal layer and the second crystal layer, the first crystal layer and stone
The contact of black alkene layer, the second crystal layer are contacted with tin alkene layer, the thickness of the thickness of the first crystal layer less than the second crystal layer.
The crystal grain of first crystal layer is smaller, thinner thickness, more preferable to the repairing effect of graphene layer, the crystal grain of the second crystal layer compared with
Greatly, during thickness is thicker, is conducive to the formation of tin alkene layer, and tin alkene layer is formed, the first crystal layer will not be destroyed, to graphene
Layer forms good protective effect, and the electron-transport of the active layer made is more efficient.
With reference to first aspect, in another embodiment, the first crystal layer with a thickness of 50-80nm, the second crystal layer with a thickness of
150-400nm。
Second aspect, the embodiment of the present application provide a kind of preparation method of thin film transistor (TFT), and including the following steps: will be active
Layer, which is transferred to the surface of substrate and carries out patterned process to active layer, forms patterned active layer.It is formed on the surface of the substrate
Patterned source layer and drain electrode layer, make active layer between source layer and drain electrode layer.In active layer, source layer and drain electrode layer
The surface and substrate away from substrate surface not by source layer, drain electrode layer and active layer cover position formed gate insulation
Layer.Grid layer is formed on the surface away from substrate of gate insulation layer.Wherein, the forming method of active layer includes: in metal foil
Surface forms graphene layer by CVD method, deposits silicon layer on the surface away from metal foil of graphene layer, etches away metal
Foil.
Single-layer graphene is formed on the surface of metal foil by CVD method, list can be repaired during forming silicon layer
The defect of layer graphene can also be used as the protective layer of graphene layer, and forms graphene layer and form silicon layer by metal
Foil etches away metal foil after forming silicon layer as substrate, and obtained graphene hetero structure layers are transferred to substrate
Surface, and the patterned process of active layer is carried out, the growth for carrying out graphene heterojunction structure directly on substrate is avoided, film is made
The range of choice of the substrate of transistor is wider.Silicon layer plays the role of to graphene layer reparation and protection, and silicon layer and stone
After black alkene layer cooperation, carrier transport effect can be kept more preferable collectively as active layer, cooperated with gate insulation layer and grid layer
After, the electric property of obtained thin film transistor (TFT) is more preferably.
In conjunction with second aspect, in another embodiment, the forming method of active layer includes: to pass through on the surface of metal foil
CVD method forms graphene layer, deposits silicon layer on the surface away from metal foil of graphene layer, deviates from graphene in silicon layer
The surface of layer grows tin alkene layer, etches away metal foil.
The active layer of formation is superconductor-semiconductor-superconductor structure, can be improved electron-transport efficiency, and silicon wafer
Layer can repair the defect of graphene layer, can also be used as the protective layer of graphene layer, can simultaneously serve as originally as semiconductor
The substrate of tin alkene layer growth, enables the electric property of thin film transistor (TFT) to effectively improve.
In conjunction with second aspect, in another embodiment, it is (4.8-5.6) that the method for depositing silicon layer, which includes: in vacuum degree,
×10-4Pa, deposition pressure use radio frequency plasma to enhance chemical vapour deposition technique in graphene under conditions of being 100-150Pa
Deposition of microcrystalline silicon layer on layer.Or vacuum degree be (1.5-3.0) × 10-3Pa, deposition pressure use under conditions of being 0.5-10Pa
Ecr plasma enhances chemical vapour deposition technique deposit polycrystalline silicon layer on graphene layer.Or it is in vacuum degree
(1.2-1.8)×10-4Pa, deposition pressure use very high frequency plasma to enhance chemical vapor deposition under conditions of being 100-150Pa
Area method deposits nanometer silicon layer on graphene layer.
To obtain silicon layer, and the graphene heterojunction structure that silicon layer and graphene layer collectively constitute thin film transistor (TFT) has
Active layer.
In conjunction with second aspect, in another embodiment, the method for growth tin alkene layer includes: that inert ion is sputtered onto silicon wafer
The surface of layer；The high annealing at 800-1000 DEG C；Electron beam evaporation tin metal, the silicon wafer face of uniform deposition after annealing；?
It anneals at a temperature of 400-800 DEG C.Or in 500-800 DEG C of at a temperature of deoxidation and silicon wafer face of annealing；Silicon wafer face after annealing
Surface molecular beam epitaxy grow tin atom crystalline film layer；Bombard the tin atom layer using inert ion, make tin atom with
The sp that silicon layer is formed3Key fracture is reconstructed into sp2Key.
To obtain tin alkene layer, and graphene layer, silicon layer and tin alkene layer collectively constitute thin film transistor (TFT) graphene it is different
Matter structure active layer.
In conjunction with second aspect, in another embodiment, further includes: in graphene layer away from the surface of metal foil deposition the
One crystal layer deposits the second crystal layer away from the surface of graphene layer in the first crystal layer, in the second crystal layer away from first crystal layer
Surface grows tin alkene layer, the thickness of the thickness of the first crystal layer less than the second crystal layer.
The crystal grain of first crystal layer is smaller, thinner thickness, during depositing the first crystal layer, can be good at repairing graphite
The crystal grain of the defect generated in alkene growth course, the second crystal layer is larger, and thickness is thicker, is conducive to the formation of tin alkene layer, and in life
During long tin alkene layer, due to the protective effect of the second crystal layer, the first crystal layer will not be destroyed, graphene layer is formed well
The electron-transport of protective effect, the active layer made is more efficient.
The third aspect, the embodiment of the present application provide a kind of electronic device, including a kind of above-mentioned thin film transistor (TFT).Using above-mentioned
Thin film transistor (TFT) can be used to prepare the electronic device of various function admirables.
Detailed description of the invention
Technical solution in ord to more clearly illustrate embodiments of the present application, below will be to needed in the embodiment attached
Figure is briefly described, it should be understood that the following drawings illustrates only some embodiments of the application, therefore is not construed as pair
The restriction of range for those of ordinary skill in the art without creative efforts, can also be according to this
A little attached drawings obtain the protection scope that other relevant attached drawings also belong to the application.
Figure 1A is the cross-sectional view of the structure realized after step S10 in the embodiment of the present application one；
Figure 1B is the cross-sectional view of the structure realized in step S14 in the embodiment of the present application one；
Fig. 1 C is the cross-sectional view of the structure realized after step S14 in the embodiment of the present application one；
Fig. 1 D is the cross-sectional view of the structure realized in step S16 in the embodiment of the present application one；
Fig. 1 E is the cross-sectional view of the structure realized after step S16 in the embodiment of the present application one；
Fig. 1 F is the cross-sectional view of the structure realized after step S18 in the embodiment of the present application one；
Fig. 1 G is the cross-sectional view of the structure realized after step S20 in the embodiment of the present application one；
Fig. 2 is the sectional view for the thin film transistor (TFT) that the embodiment of the present application two provides.
Icon: 210- substrate；220- active layer；221- graphene layer；222- silicon layer；223- tin alkene layer；231- source electrode
Layer；232- drain electrode layer；250- gate insulation layer；260- grid layer；The first conductive layer of 230-.
Specific embodiment
It, below will be in the embodiment of the present application to keep the purposes, technical schemes and advantages of the embodiment of the present application clearer
Technical solution be clearly and completely described.The person that is not specified actual conditions in embodiment, according to normal conditions or manufacturer builds
The condition of view carries out.Reagents or instruments used without specified manufacturer is the conventional production that can be obtained by commercially available purchase
Product.
The thin film transistor (TFT) of the embodiment of the present application, preparation method and electronic device are specifically described below.
Embodiment one please refers to Figure 1A-Fig. 1 G,
S10, Figure 1A are the cross-sectional view of the structure realized after step S10 in the embodiment of the present application one.Figure 1A is please referred to, is made
Active layer 220 is had, that is, prepares graphene hetero structure layers:
S110 forms graphene layer 221, forms graphene layer 221 by CVD method on the surface of metal foil, CVD method refers to
Chemical vapour deposition technique (Chemical Vapor Deposition), the list of large area, high quality can be prepared by CVD method
Layer graphene film, with methane (CH4) it is raw material, single-layer graphene film is grown on metal foil.
Wherein, metal foil can be copper foil or nickel foil, single-layer graphene with a thickness of 0.3-0.4nm, form ultra-thin stone
Black alkene layer 221.
S120 forms silicon layer 222, deposits silicon layer 222, graphite on the surface away from metal foil of graphene layer 221
During alkene layer 221 is grown, some defects can be generated, during depositing silicon layer 222, graphene layer can be repaired
221 defect, and silicon layer 222 is used as semiconductor, electron-transport is able to carry out, in the process of subsequent growth tin alkene layer 223
In, can be used as the substrate of growth tin alkene layer 223, while graphene layer 221 protected, avoid graphene layer 221 by
It destroys.
Optionally, silicon layer 222 is non-single crystalline layers, is easy preparation, will not be to stone during forming silicon layer 222
Black alkene layer 221 damages, and can graphene layer 221 be repaired and be protected, and the electron-transport effect of active layer 220 is made
More preferably.
Silicon layer 222 is non-monocrystal silicon layer, and non-monocrystal silicon layer includes one kind of microcrystal silicon layer, polysilicon layer and nanometer silicon layer
Or it is a variety of.
In one embodiment, silicon layer 222 be microcrystal silicon layer, microcrystal silicon layer the preparation method comprises the following steps: using radio frequency etc. from
Daughter enhances chemical vapour deposition technique deposition of microcrystalline silicon layer on graphene layer 221.Vacuum degree is (4.8-5.6) × 10-4Pa sinks
Pneumatosis pressure is 100-150Pa.
Wherein, under conditions of metal foil and the temperature of graphene layer 221 are 200-450 DEG C, good crystallite can be obtained
Silicon layer, the crystal layer thickness of microcrystal silicon layer are 300-400nm, and the crystallite dimension of microcrystal silicon layer is 20-70nm.
In another embodiment, silicon layer 222 be polysilicon layer, polysilicon layer the preparation method comprises the following steps: using electron cyclotron
Resonance Plasma enhances chemical vapour deposition technique deposit polycrystalline silicon layer on graphene layer 221.Vacuum degree be (1.5-3.0) ×
10-3Pa, deposition pressure 0.5-10Pa.
Wherein, under conditions of metal foil and the temperature of graphene layer 221 are 150-400 DEG C, good polycrystalline can be obtained
Silicon layer, the crystal layer thickness of polysilicon layer are 150-300nm, and the crystallite dimension of polysilicon layer is 20-30nm.
In other embodiments, silicon layer 222 be nanometer silicon layer, nanometer silicon layer the preparation method comprises the following steps: using very high frequency(VHF) etc.
Gas ions enhancing chemical vapour deposition technique deposits nanometer silicon layer on graphene layer 221.Vacuum degree is (1.2-1.8) × 10-4Pa,
Deposition pressure is 100-150Pa.
Wherein, under conditions of metal foil and the temperature of graphene layer 221 are 150-300 DEG C, good nanometer can be obtained
Silicon layer, the crystal layer thickness of nanometer silicon layer are 50-80nm, and the crystallite dimension of nanometer silicon layer is 5-8nm.
In one embodiment, multilayer also can be set into silicon layer 222, such as: first in graphene layer 221 away from gold
Belong to the surface deposit polycrystalline silicon layer of foil, then deposits nanometer silicon layer on the surface away from graphene layer 221 of polysilicon layer.It is optional
Ground, first in the surface deposition of microcrystalline silicon layer away from metal foil of graphene layer 221, then in microcrystal silicon layer away from graphene layer
221 surface deposits nanometer silicon layer.Alternatively, first in the surface deposition of microcrystalline silicon layer away from metal foil of graphene layer 221, then
The surface away from graphene layer 221 of microcrystal silicon layer deposits nanometer silicon layer, then on the surface away from microcrystal silicon layer of nanometer silicon layer
Form polysilicon layer.
If silicon layer 222 includes two layers, such as the first crystal layer and the second crystal layer, the first crystal layer is nanometer silicon layer, and second is brilliant
Layer is microcrystal silicon layer, first deposits nanometer silicon layer, then deviating from nanometer silicon layer on the surface away from metal foil of graphene layer 221
The surface deposition of microcrystalline silicon layer of graphene layer 221, the thinner thickness of nanometer silicon layer, crystal grain is smaller, passes through the formation of nanometer silicon layer
The defect generated during graphene growth can be repaired well.And after forming microcrystal silicon layer, microcrystal silicon layer is thicker, brilliant
Grain is larger, can be used as the substrate to form tin alkene layer 223, during forming tin alkene layer 223, will not destroy a nanometer silicon layer,
There can be good protective effect to graphene layer 221, keep the electron-transport of graphene hetero structure layers more efficient.And shape
Temperature at silicon layer 222 is lower, during forming silicon layer 222, will not destroy the structure of graphene layer 221, and energy
It is enough that graphene layer 221 is repaired.
Optionally, the first crystal layer with a thickness of 50-80nm, the second crystal layer with a thickness of 150-400nm.In one embodiment
In, the second crystal layer with a thickness of 150-300nm, the first crystal layer is nanometer silicon layer, and the second crystal layer is polysilicon layer, then first in graphite
The surface away from metal foil of alkene layer 221 deposits nanometer silicon layer, then deposits on the surface away from graphene layer 221 of nanometer silicon layer
Polysilicon layer.
In another embodiment, the second crystal layer with a thickness of 300-400nm, the first crystal layer is nanometer silicon layer, the second crystal layer
For microcrystal silicon layer, then nanometer silicon layer, then deviating from nanometer silicon layer first are deposited on the surface away from metal foil of graphene layer 221
The surface deposition of microcrystalline silicon layer of graphene layer 221.
In the embodiment of the present application, the generation type of silicon layer 222 is not limited, and the generation type of silicon layer 222 may be used also
To include hot filament CVD, impulse modulation radio frequency plasma enhancing chemical vapour deposition technique, high vacuum chemical
At least one of vapour deposition process, catalytic chemical vapor deposition technique, electron beam evaporation.
During silicon layer 222 is formed, reaction gas may is that the mixed gas of silane and high-purity hydrogen composition, halogen
Mixed gas or silane, the mixed gas of halogenated silanes and high-purity hydrogen composition for silane and high-purity hydrogen composition.
In other embodiments, silicon layer can also be monocrystalline silicon layer.
S140 forms tin alkene layer 223, forms tin alkene layer 223 on the surface away from graphene layer 221 of silicon layer 222, such as
Fruit silicon layer 222 is only one layer, then forms tin alkene layer 223, tin alkene layer on the surface away from graphene layer 221 of silicon layer 222
In 223 forming processes, by silicon layer 222 be used as substrate, be conducive to the formation of tin alkene layer 223 and avoid graphene layer 221 by
It destroys.
If silicon layer 222 is two layers, tin alkene layer 223, tin alkene are formed on the surface away from the first crystal layer of the second crystal layer
In 223 forming process of layer, by the second crystal layer as substrate, the first crystal layer is avoided to be destroyed, graphene layer 221 is formed and is protected
Shield, the electron-transport of the active layer 220 made are more efficient.
Wherein, the process of tin alkene layer 223 is formed are as follows: (1), inert ion (such as: argon ion, helium ion or ne ion) splashes
The surface of radiosilicon crystal layer 222, such as: carry out 15 argon ion sputterings.(2), by 221/ silicon layer of base metal foil/graphene layer
222 are heated to 800-1000 DEG C and high annealing obtains clean smooth silicon wafer face.(3), electron beam evaporation tin metal, it is uniformly heavy
Product makes substrate be maintained at room temperature on silicon wafer face.(4), 400-800 DEG C at a temperature of anneal, the surface of silicon layer 222 is formed
With a thickness of the tin alkene layer 223 of 0.4-0.6nm, the superconductor layer structure of sequential 2 D is formed.
In one embodiment, the forming method of tin alkene layer 223 include: (1), 500-800 DEG C at a temperature of deoxidation simultaneously
Annealing obtains clean smooth silicon wafer face.(2), the surface molecular beam epitaxy in silicon wafer face grows tin atom crystalline film layer, makes
Sp is formed between silicon wafer face and tin atom layer3Key.(3), tin is bombarded using argon ion (inert ion) in particle injection device
Atomic layer, the sp for forming tin atom and silicon layer 2223Key fracture is reconstructed into sp2Key obtains 223 structure of tin alkene layer.
S160 forms graphene heterojunction structure active layer 220, etches away metal foil, forms graphene hetero structure layers.Its
In, please refer to Figure 1A, with graphene layer 221 for the first active layer in hetero structure layers, silicon layer 222 is the second active layer, tin
Alkene layer 223 is third active layer, forms superconductor-semiconductor-superconductor structure, improves the electron-transport efficiency of active layer 220.
S12 selects a substrate 210:
Substrate 210 can be glass substrate, silicon substrate or flexible base board.Wherein, flexible base board 210 includes PI (polyamides
Imines, Polyimide), PET (polyethylene terephthalate, Polyethylene terephthalate), PEN (poly- naphthalene
Naphthalate, Polyethylene naphthalate), PES (polyether sulfone, Polyethersulfone), PC (poly- carbon
Acid esters, Polycarbonate), PVA (polyvinyl alcohol, Polyvinyl alcohol), PP (polypropylene, Polypropylene),
MYLAR film, PEEK (polyether-ether-ketone, Polyetheretherketone), PPA (poly- terephthalate p-phenylenediamine,
Polyphthalamide), PTFE (polytetrafluoroethylene (PTFE), Polytetrafluoroethylene), PMMA (poly-methyl methacrylate
Ester, Polymethyl methacrylate), PDMS (dimethyl silicone polymer, Polydimethylsiloxane) etc..Due to
It does not need directly to form graphene layer 221, silicon layer 222 and tin alkene layer 223 over the substrate 210, but it is different to form graphene
After matter structure active layer 220, it is transferred to the surface of substrate 210, so, the range of choice of substrate 210 is larger, is conducive to be formed not
With the thin film transistor (TFT) of substrate 210.
S14 forms patterned active layer 220:
Figure 1B is the cross-sectional view of the structure realized in step S14 in the embodiment of the present application one；Fig. 1 C is the embodiment of the present application one
The middle cross-sectional view of the structure realized after step S14.Figure 1B and Fig. 1 C is please referred to, active layer 220 is transferred to the table of substrate 210
Face such as Figure 1B, and form patterned active layer 220 such as Fig. 1 C.Active layer 220 is the graphene layer 221 of overlapping, silicon layer 222
With tin alkene layer 223, then graphene layer 221 is transferred to the surface of substrate 210, silicon layer 222 is located at the upper table of graphene layer 221
Face, tin alkene layer 223 are located at the upper surface of silicon layer 222, or tin alkene layer 223 is transferred to the surface of substrate 210, silicon layer
222 are located at the upper surface of tin alkene layer 223, and graphene layer 221 is located at the upper surface of silicon layer 222.
The generation type of patterned active layer 220 includes: to apply lighting on the surface of tin alkene layer 223 or graphene layer 221
Resistance layer is exposed, progress dry etching handles to obtain patterned graphene/crystalline silicon/tin alkene active layer after developing process
220。
S16 forms source layer 231 and drain electrode layer 232:
Fig. 1 D is the cross-sectional view of the structure realized in step S16 in the embodiment of the present application one；Fig. 1 E is the embodiment of the present application one
The middle cross-sectional view of the structure realized after step S16.Fig. 1 D and Fig. 1 E is please referred to, is formed on the surface of substrate 210 patterned
Source layer 231 and drain electrode layer 232, make active layer 220 between source layer 231 and drain electrode layer 232.Do not had in substrate 210
The first conductive layer 230 such as Fig. 1 D is formed on the position of the covering of active layer 220 and active layer 220, is applied on the surface of the first conductive layer 230
Cloth photoresist layer is exposed, dry etching is carried out after developing process handles to obtain patterned source layer 231 and drain electrode layer 232, and
Active layer 220 is between source layer 231 and drain electrode layer 232 such as Fig. 1 E.
Wherein, the material of the first conductive layer 230 can be metal, such as: golden (Au), titanium (Ti), silver-colored (Ag), aluminium (Al),
Copper (Cu), nickel (Ni), tungsten (W), molybdenum (Mo), chromium (Cr), neodymium (Nd), gold paste, silver paste, copper slurry are one or more of；Conducting polymer；
Metal oxide；Carbon nano tube-doped or composite material；Nano-silver thread or NANO CRYSTAL COPPER WIRE.
The method that first conductive layer 230 is formed includes magnetron sputtering, vacuum evaporation, ink jet printing, silk-screen printing, intaglio process
One of brush, chemical vapor deposition, roll-to-roll printing, micro-contact printing, nano impression.
In the present embodiment, source layer 231 and drain electrode layer 232 with a thickness of 60-2000nm, optionally, source layer 231 and leakage
Pole layer 232 with a thickness of 80-1000nm, optionally, source layer 231 and drain electrode layer 232 with a thickness of 100-800nm.
S18 forms gate insulation layer 250:
Fig. 1 F is the cross-sectional view of the structure realized after step S18 in the embodiment of the present application one.Fig. 1 F is please referred to, active
Layer 220, the surface and substrate 210 away from substrate 210 of source layer 231 and drain electrode layer 232 surface not by active layer
220, the position that source layer 231 and drain electrode layer 232 cover forms gate insulation layer 250.In tin alkene layer 223, source layer 231, drain electrode
The surface in layer 232 and the region not covered by source layer 231 and drain electrode layer 232 forms gate insulation layer 250.
Wherein, gate insulation layer 250 can be inorganic insulation layer or organic insulator.The generation type of inorganic insulation layer is to pass through
CVD method or atomic layer deposition method are by insulative material deposition in tin alkene layer 223, source layer 231, drain electrode layer 232 and substrate 210
The region that surface is not covered by source layer 231, drain electrode layer 232 and active layer 220.Wherein, inorganic insulating material includes: titanium dioxide
The oxides such as silicon, aluminium oxide, silicon nitride, aluminium nitride or nitride.
The generation type of organic insulator is by spin coating, spraying, dip-coating, blade coating, contact coating or slit
The mode of coating by insulating materials be coated on the surface of tin alkene layer 223, source layer 231, drain electrode layer 232 and substrate 210 not by
The region that source layer 231, drain electrode layer 232 and active layer 220 cover.Wherein, organic insulating material includes: perfluor cyclic polymer
(CYTOP), Freon C318 (PFCB), polystyrene (PS), polytetrafluoroethylene (PTFE) (PTFE), polyvinyl alcohol (PVA), poly- methyl-prop
E pioic acid methyl ester (PMMA), benzocyclobutene (BCB), polyvinyl cinnamate (PVC), photoresist (SU-8) etc..
In the present embodiment, gate insulation layer 250 with a thickness of 10-1000nm, optionally, gate insulation layer 250 with a thickness of 50-
800nm, optionally, gate insulation layer 250 with a thickness of 100-500nm.
S20 forms grid layer 260:
Fig. 1 G is the cross-sectional view of the structure realized after step S20 in the embodiment of the present application one.Fig. 1 G is please referred to, it is exhausted in grid
The surface away from substrate 210 of edge layer 250 forms grid layer 260.The second conductive layer is formed on the surface of gate insulation layer 250,
The surface of second conductive layer is coated with photoresist layer, is exposed, is etched to obtain grid layer 260 after developing process.
The material of second conductive layer can be metal, such as: gold (Au), titanium (Ti), silver (Ag), aluminium (Al), copper (Cu), nickel
(Ni), molybdenum (Mo), chromium (Cr), neodymium (Nd), tin indium oxide (ITO) are one or more of.Pass through magnetron sputtering or vacuum evaporation mode
It is deposited on 250 surface of gate insulation layer.
Grid layer 260 with a thickness of 5-1000nm, optionally, grid layer 260 with a thickness of 10-500nm, optionally, grid
Pole layer 260 with a thickness of 20-200nm.
The structure of obtained thin film transistor (TFT) includes: that substrate 210, active layer 220, source layer 231, drain electrode layer 232, grid are exhausted
Edge layer 250 and grid layer 260.Wherein, active layer 220 is located at the surface of substrate 210, and source layer 231 and drain electrode layer 232 are located at base
The surface of plate 210 and active layer 220 is between source layer 231 and drain electrode layer 232.Gate insulation layer 250 be located at source layer 231,
The surface on the surface and substrate 210 away from substrate 210 of drain electrode layer 232 and active layer 220 not by source layer 231, drain electrode
The position that layer 232 and active layer 220 cover.Grid layer 260 is located at the surface of gate insulation layer 250.
Active layer 220 is graphene hetero structure layers.Active layer 220 is the graphene layer 221 of overlapping, 222 and of silicon layer
Tin alkene layer 223.The setting of silicon layer 222 can not only carry out electron-transport as semiconductor, and can repair graphene layer
The defect generated in 221 growth courses also forms graphene layer 221 during forming tin alkene layer 223 and protects, avoids stone
Black alkene layer 221 is destroyed, and active layer 220 forms superconductor-semiconductor-superconductor structure, the electron-transport effect of active layer 220
Rate is higher.When graphene hetero structure layers are set, it can make that graphene layer 221 is located at the upper surface of substrate 210 and substrate 210 connects
Touching, tin alkene layer 223 are contacted with gate insulation layer 250；The upper surface that tin alkene layer 223 can also be made to be located at substrate 210 connects with substrate 210
Touching, graphene layer 221 are contacted with gate insulation layer 250.
Optionally, silicon layer 222 includes the first crystal layer and the second crystal layer, and the first crystal layer is contacted with graphene layer 221, and second
Crystal layer is contacted with tin alkene layer 223, the thickness of the thickness of the first crystal layer less than the second crystal layer.The crystal grain of first crystal layer is smaller, thickness
Relatively thin, more preferable to the repairing effect of graphene layer 221, the crystal grain of the second crystal layer is larger, and thickness is thicker, so as to tin alkene layer 223
It is formed, and during the formation of tin alkene layer 223, the first crystal layer will not be destroyed, protection well is formed to graphene layer 221 and is made
With the electron-transport of the active layer 220 made is more efficient.
Embodiment two
Fig. 2 is the sectional view for the thin film transistor (TFT) that the embodiment of the present application two provides.Referring to Fig. 2, embodiment is second is that this Shen
Please embodiment one a kind of distressed structure schematic diagram.Referring to Fig. 2, on the basis of embodiment 1, active layer 220 is graphene
Hetero structure layers do not include tin alkene layer in active layer 220, and active layer 220 is the graphene layer 221 and silicon layer 222 of overlapping,
When the surface of graphene layer 221 deposits silicon layer 222, silicon layer 222 can repair graphene layer 221, make active layer
220 electron-transport efficiency improves.When graphene hetero structure layers are set, graphene layer 221 can be made to be located at the upper of substrate 210
Surface is contacted with substrate 210, and silicon layer 222 is contacted with gate insulation layer 250；Silicon layer 222 can also be made to be located at the upper of substrate 210
Surface is contacted with substrate 210, and graphene layer 221 is contacted with gate insulation layer 250.
When shifting active layer 220, graphene layer 221 can be transferred to the surface of substrate 210, silicon layer 222 is located at
The upper surface of graphene layer 221, or silicon layer 222 is transferred to the surface of substrate 210, graphene layer 221 is located at silicon layer
222 upper surface.
Embodiment 1
The preparation method of thin film transistor (TFT) includes:
(1), graphene layer 221 is formed by CVD method on the surface of copper foil, is 1.5 × 10 in vacuum degree-4Pa, deposition gas
Pressure is 112.3Pa, and temperature uses very high frequency plasma to enhance chemical vapour deposition technique in graphene layer under conditions of being 213 DEG C
221 upper surface deposition thickness is the nanometer silicon layer of 20nm.Copper foil is etched away, graphene hetero structure layers are formed.
(2), graphene hetero structure layers are transferred to the surface of pet substrate 210, are in contact with substrate graphene layer,
The surface of silicon layer is coated with photoresist layer, is exposed, progress dry etching handles to obtain patterned active layer after developing process.
(3), patterned source layer and drain electrode layer are formed on the surface of pet substrate, active layer is made to be located at source layer and leakage
Between the layer of pole.
(4), in active layer, source layer and drain electrode layer away from the surface of substrate and the surface of substrate 210 not by source electrode
The position of layer, drain electrode layer and active layer covering forms gate insulation layer.
(5), grid layer is formed on the surface away from substrate of gate insulation layer.
Embodiment 2
The preparation method of embodiment 2 and the preparation method of embodiment 1 are different in: by argon ion sputtering in nanometer silicon layer
Surface, substrate copper foil/graphene layer/nanometer silicon layer is heated to 850 DEG C and high annealing obtains clean smooth nano-silicon
Crystal face.Electron beam evaporation tin metal, uniform deposition make substrate be maintained at room temperature on nano-silicon crystal face.It anneals at 490 DEG C, shape
At the tin alkene layer with a thickness of 0.48nm.It etches away copper foil and forms graphene hetero structure layers.Other step methods are consistent.
Embodiment 3
The preparation method of embodiment 3 and the preparation method of embodiment 2 are different in: being 5.2 × 10 in vacuum degree-4Pa,
Using radio frequency plasma enhancing chemical vapour deposition technique in nanometer under conditions of deposition pressure is 133.3Pa, temperature is 260 DEG C
The surface deposition thickness of silicon layer is the microcrystal silicon layer of 300nm, reuses surface shape of the method in microcrystal silicon layer of the offer of embodiment 2
At tin alkene layer.It etches away copper foil and forms graphene hetero structure layers.Other step methods are consistent.
Embodiment 4
The preparation method of embodiment 4 and the preparation method of embodiment 3 are different in: forming nanometer silicon layer and microcrystal silicon layer
Sequence it is different, embodiment 4 forms microcrystal silicon layer on the surface of graphene layer, then forms nano-silicon on the surface of microcrystal silicon layer
Layer.Other step methods are consistent.
Comparative example 1
The preparation method of thin film transistor (TFT) includes:
(1), graphene layer is formed by CVD method on the surface of copper foil, etches away copper foil.
(2), graphene layer is transferred to the surface of pet substrate, photoresist layer is coated on the surface of graphene layer, is exposed
Dry etching is carried out after light, developing process to handle to obtain patterned graphene active layer.
(3), patterned source layer and drain electrode layer are formed on the surface of pet substrate, active layer is made to be located at source layer and leakage
Between the layer of pole.
(4), gate insulation layer is formed on the surface away from substrate of active layer, source layer and drain electrode layer.
(5), grid layer is formed on the surface away from substrate of gate insulation layer.
Comparative example 2
The preparation method of comparative example 2 and the preparation method of comparative example 1 are different in: carrying out multiple argon to alumina substrate
Alumina substrate is heated to 850 DEG C and high annealing obtains aluminium oxide crystal face by ion sputtering.Electron beam evaporation tin metal,
It is even to be deposited on aluminium oxide crystal face, so that aluminium oxide crystal face is maintained at room temperature.It anneals at 490 DEG C, obtains the list with a thickness of 0.48nm
Layer tin alkene etches away alumina substrate and forms tin alkene layer.Graphene active layer is namely substituted for tin alkene layer active layer, other
Step method is consistent.
Experimental example 1
The carrier mobility for the thin film transistor (TFT) that detection embodiment 1- embodiment 4 and comparative example 1 and comparative example 2 obtain
Rate, threshold voltage and current on/off ratio obtain table 1.
The electric property of 1 thin film transistor (TFT) of table
| Group | Carrier mobility (cm2/Vs) | Threshold voltage (V) | Current on/off ratio |
| Embodiment 1 | 118 | 4.7 | 5.2×107 |
| Embodiment 2 | 164 | 3.9 | 6.3×107 |
| Embodiment 3 | 183 | 3.2 | 6.9×107 |
| Embodiment 4 | 135 | 4.1 | 6.1×107 |
| Comparative example 1 | 102 | 5.8 | 4.4×107 |
| Comparative example 2 | 58 | 7.2 | 2.8×107 |
As it can be seen from table 1 compared to comparative example 1 (individual graphene layer) or comparative example 2 (individual tin alkene layer), it is real
The carrier mobility for applying the thin film transistor (TFT) that a 1- embodiment 4 provides improves, and threshold voltage reduces, and current on/off ratio increases,
Electric property is more preferably.
Embodiment 1-4 is compared to as can be seen that the film that graphene layer, silicon layer and tin alkene layer are obtained collectively as active layer
Electric property of the electric property of transistor better than the thin film transistor (TFT) that graphene layer and silicon layer are obtained as active layer.
If embodiment 2-4, which compares can be seen that, forms two layers of silicon layer, and close to the silicon layer of graphene layer side
Thickness is less than the thickness of the silicon layer close to tin alkene layer side, and the electric property of obtained thin film transistor (TFT) is more preferably；If close
The thickness of the silicon layer of graphene layer side is greater than the thickness of the silicon layer close to tin alkene layer side, with only one layer of silicon layer phase
Than the electric property of the thin film transistor (TFT) made instead reduces.
Embodiments described above is some embodiments of the present application, instead of all the embodiments.The reality of the application
The detailed description for applying example is not intended to limit claimed scope of the present application, but is merely representative of the selected implementation of the application
Example.Based on the embodiment in the application, obtained by those of ordinary skill in the art without making creative efforts
Every other embodiment, shall fall in the protection scope of this application.
Claims (10)
1. a kind of thin film transistor (TFT) characterized by comprising
Substrate；
Active layer, the active layer are graphene hetero structure layers, and the graphene hetero structure layers include the graphene of overlapping
Layer and silicon layer, the graphene layer or the silicon layer are located at the surface of the substrate；
The surface that source layer and drain electrode layer, the source layer and the drain electrode layer are located at the substrate makes the graphene hetero-junctions
Structure layer is between the source layer and the drain electrode layer；
Gate insulation layer, the gate insulation layer are located at the back of the source layer, the drain electrode layer and the graphene hetero structure layers
The surface on surface and the substrate from the substrate it is not heterogeneous by the source layer, the drain electrode layer and the graphene
The position of structure sheaf covering；
Grid layer, the grid layer are located at the surface away from the substrate of the gate insulation layer.
2. thin film transistor (TFT) according to claim 1, which is characterized in that the graphene hetero structure layers include successively weighing
Folded graphene layer, silicon layer and tin alkene layer, the graphene layer or the tin alkene layer are located at the surface of the substrate；
Optionally, the graphene layer is single-layer graphene, and the tin alkene layer is single layer tin alkene.
3. thin film transistor (TFT) according to claim 2, which is characterized in that the silicon layer is non-monocrystal silicon layer；
Optionally, the non-monocrystal silicon layer includes the one or more of microcrystal silicon layer, polysilicon layer and nanometer silicon layer.
4. thin film transistor (TFT) according to claim 2, which is characterized in that the silicon layer includes that the first crystal layer and second are brilliant
Layer, first crystal layer are contacted with the graphene layer, and second crystal layer is contacted with the tin alkene layer, first crystal layer
Thickness is less than the thickness of second crystal layer；
Optionally, first crystal layer with a thickness of 50-80nm, second crystal layer with a thickness of 150-400nm.
5. a kind of preparation method of thin film transistor (TFT), which comprises the steps of:
Active layer is transferred to the surface of substrate and carries out patterned process to the active layer and forms patterned active layer；
Patterned source layer and drain electrode layer are formed on the surface of the substrate, the active layer is made to be located at the source layer and institute
It states between drain electrode layer；
In the active layer, the source layer and the drain electrode layer away from the surface of the substrate and the surface of the substrate
Not by the source layer, the drain electrode layer and the active layer cover position formed gate insulation layer；
Grid layer is formed on the surface away from the substrate of the gate insulation layer；
Wherein, the forming method of the active layer includes: to form graphene layer by CVD method on the surface of metal foil, described
The surface away from the metal foil of graphene layer deposits silicon layer, etches away the metal foil.
6. the preparation method of thin film transistor (TFT) according to claim 5, which is characterized in that the forming method of the active layer
It include: the graphene layer is formed by CVD method on the surface of metal foil, in the graphene layer away from the metal foil
Surface deposits silicon layer, grows tin alkene layer on the surface away from the graphene layer of the silicon layer, etches away the metal
Foil.
7. the preparation method of thin film transistor (TFT) according to claim 6, which is characterized in that the method for the deposition silicon layer
Include:
It is (4.8-5.6) × 10 in vacuum degree-4Pa, deposition pressure are increased under conditions of being 100-150Pa using radio frequency plasma
Extensive chemical vapour deposition process deposition of microcrystalline silicon layer on the graphene layer；
Or vacuum degree be (1.5-3.0) × 10-3Pa, deposition pressure use electron cyclotron resonace etc. under conditions of being 0.5-10Pa
Gas ions enhance chemical vapour deposition technique deposit polycrystalline silicon layer on the graphene layer；
Or vacuum degree be (1.2-1.8) × 10-4Pa, deposition pressure use very high frequency(VHF) plasma under conditions of being 100-150Pa
Body enhancing chemical vapour deposition technique deposits nanometer silicon layer on the graphene layer.
8. the preparation method of thin film transistor (TFT) according to claim 6, which is characterized in that the method for the growth tin alkene layer
Include:
Inert ion is sputtered onto the surface of the silicon layer；The high annealing at 800-1000 DEG C；Electron beam evaporation tin metal,
The silicon wafer face of uniform deposition after annealing；400-800 DEG C at a temperature of anneal；
Or in 500-800 DEG C of the at a temperature of deoxidation and silicon wafer face of annealing；The surface molecular in the silicon wafer face after annealing
Beam epitaxy grows tin atom crystalline film layer；The tin atom layer is bombarded using inert ion, makes tin atom and the silicon layer
The sp of formation3Key fracture is reconstructed into sp2Key.
9. the preparation method of thin film transistor (TFT) according to claim 6, which is characterized in that further include: in the graphene
The surface away from the metal foil of layer deposits the first crystal layer, heavy on the surface away from the graphene layer of first crystal layer
The second crystal layer of product grows the tin alkene layer, first crystal layer on the surface away from first crystal layer of second crystal layer
Thickness be less than second crystal layer thickness.
10. a kind of electronic device, which is characterized in that including a kind of thin film transistor (TFT) according to any one of claims 1-4.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910669616.0A CN110379859B (en) | 2019-07-23 | 2019-07-23 | Thin film transistor, preparation method thereof and electronic device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910669616.0A CN110379859B (en) | 2019-07-23 | 2019-07-23 | Thin film transistor, preparation method thereof and electronic device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN110379859A true CN110379859A (en) | 2019-10-25 |
| CN110379859B CN110379859B (en) | 2022-08-16 |
Family
ID=68255319
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910669616.0A Active CN110379859B (en) | 2019-07-23 | 2019-07-23 | Thin film transistor, preparation method thereof and electronic device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN110379859B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20160307756A1 (en) * | 2014-07-02 | 2016-10-20 | Fuji Electric Co., Ltd. | Method of manufacturing silicon carbide semiconductor device |
| CN107256899A (en) * | 2017-06-28 | 2017-10-17 | 泰州巨纳新能源有限公司 | Based on the silicon heterogenous passive site sensitive detector of graphene |
| CN107275398A (en) * | 2017-05-04 | 2017-10-20 | 中国科学院微电子研究所 | A kind of silicon heterogenous transistor arrangement of deflocculated graphite alkene and its manufacture method |
| CN107845687A (en) * | 2017-10-27 | 2018-03-27 | 合肥鑫晟光电科技有限公司 | Thin film transistor (TFT) and preparation method thereof, electronic equipment |
-
2019
- 2019-07-23 CN CN201910669616.0A patent/CN110379859B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20160307756A1 (en) * | 2014-07-02 | 2016-10-20 | Fuji Electric Co., Ltd. | Method of manufacturing silicon carbide semiconductor device |
| CN107275398A (en) * | 2017-05-04 | 2017-10-20 | 中国科学院微电子研究所 | A kind of silicon heterogenous transistor arrangement of deflocculated graphite alkene and its manufacture method |
| CN107256899A (en) * | 2017-06-28 | 2017-10-17 | 泰州巨纳新能源有限公司 | Based on the silicon heterogenous passive site sensitive detector of graphene |
| CN107845687A (en) * | 2017-10-27 | 2018-03-27 | 合肥鑫晟光电科技有限公司 | Thin film transistor (TFT) and preparation method thereof, electronic equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| CN110379859B (en) | 2022-08-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US10164135B2 (en) | Electronic device including graphene-based layer(s), and/or method or making the same | |
| US8591680B2 (en) | Debonding and transfer techniques for hetero-epitaxially grown graphene, and products including the same | |
| US8507797B2 (en) | Large area deposition and doping of graphene, and products including the same | |
| JP5139368B2 (en) | Thin film transistor manufacturing method | |
| US20110033688A1 (en) | Large area deposition of graphene via hetero-epitaxial growth, and products including the same | |
| TW201442245A (en) | Thin film transistor and method of making the same | |
| TWI526559B (en) | Process for forming carbon film or inorganic material film on substrate by physical vapor deposition | |
| JP2009278105A (en) | Method of manufacturing thin film transistor | |
| CN108793146A (en) | A method of transfer graphene | |
| CN108428666A (en) | The production method of flexible TFT backplate and flexible TFT backplate | |
| KR101122676B1 (en) | Method of forming graphene layer using armorphous carbon layer | |
| KR101156355B1 (en) | Method of forming graphene layer using si layer solved carbon | |
| Zhou et al. | Defect Etching of Phase‐Transition‐Assisted CVD‐Grown 2H‐MoTe2 | |
| TWI520901B (en) | Method of transferring graphene layer | |
| Cheng et al. | Low threshold field emission from nanocrystalline diamond/carbon nanowall composite films | |
| Oh et al. | Large-scale, single-oriented ZnO nanostructure on h-BN films for flexible inorganic UV sensors | |
| CN112174121A (en) | Preparation method of large-size clean graphene material | |
| CN110379859A (en) | A kind of thin film transistor (TFT), preparation method and electronic device | |
| US11658232B2 (en) | Field effect transistor based on graphene nanoribbon and method for making the same | |
| US20220177313A1 (en) | Graphene nanoribbon composite structure and method for making the same | |
| US11948793B2 (en) | Field effect transistor based on graphene nanoribbon and method for making the same | |
| KR101706963B1 (en) | Method for manufacturing graphene hybrid electrode | |
| TWI545217B (en) | Method of forming double-layer of carbon/metal and triple-layer of carbon/metal/carbon on a substrate and structure thereof | |
| KR101449278B1 (en) | Graphene growth method using semiconductor | |
| KR101143694B1 (en) | Method of forming graphene layer using metal layer solved carbon |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |