CN110379780A - A kind of silicon substrate fan-out-type wafer-level packaging method and structure - Google Patents

A kind of silicon substrate fan-out-type wafer-level packaging method and structure Download PDF

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Publication number
CN110379780A
CN110379780A CN201910701998.0A CN201910701998A CN110379780A CN 110379780 A CN110379780 A CN 110379780A CN 201910701998 A CN201910701998 A CN 201910701998A CN 110379780 A CN110379780 A CN 110379780A
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silicon substrate
support plate
chip
layer
glass support
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CN110379780B (en
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王成迁
明雪飞
吉勇
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CETC 58 Research Institute
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CETC 58 Research Institute
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    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
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    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
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    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
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    • H01L2224/92—Specific sequence of method steps
    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92244—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H01L2924/15155—Shape the die mounting substrate comprising a recess for hosting the device the shape of the recess being other than a cuboid
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    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

Abstract

The present invention discloses a kind of silicon substrate fan-out-type wafer-level packaging method and structure, belongs to integrated antenna package technical field.Silicon substrate is provided first, etch heat dissipation channel in the silicon substrate front and deposits cutoff layer；The first glass support plate is bonded on the cutoff layer；Then go out groove in the silicon substrate back-etching, be embedded to chip and filled up with dry film material；It is open at the pad of chip followed by photoetching, forms first layer wiring；Successively made in the second glass support plate passivation layer, n-layer wiring and micro convex point, and with the first layer wire bond；The second glass support plate is disassembled again, and makes solder mask and salient point；The first glass support plate is disassembled, single chip is cut into, completes encapsulation.

Description

A kind of silicon substrate fan-out-type wafer-level packaging method and structure
Technical field
The present invention relates to integrated antenna package technical field, in particular to a kind of silicon substrate fan-out-type wafer-level packaging method and Structure.
Background technique
Currently, integrated antenna package develops towards three-dimensional systematic encapsulation direction, as integrated level and performance requirement are more next Higher, chip frequency, bandwidth and processing speed are continuously improved, so that chip packing-body energy consumption greatly increases, this is also just to encapsulation Heat-sinking capability proposes requirements at the higher level.Application No. is the silicon substrates for the integrated heat dissipation structure that 201711364900.4 patent of invention proposes Fan-out package and wafer-level packaging method, the groove at the silicon substrate back side and positive heat dissipation channel etching depth are difficult to control, and are carved Depth is excessive that heat dissipation channel groove is caused to be pierced for erosion, and etching depth is too small to cause heat dissipation effect bad.
In addition, chip I/O quantity is more and more, to the three of high integration since wafer manufacture process capability constantly enhances The demand for tieing up system in package is more and more, so that the number of plies that is routed again of wafer-level packaging is also being continuously increased, multiple wiring is drawn Wafer flow difficulty is continuously improved in the warpage risen, while warpage has also seriously affected lithographic accuracy, becomes high integration three Tie up a big obstacle of system in package development.
Summary of the invention
The purpose of the present invention is to provide a kind of silicon substrate fan-out-type wafer-level packaging method and structures, to solve existing core The problem of chip package heat-sinking capability is poor and multilayer wiring easily causes warpage.
In order to solve the above technical problems, the present invention provides a kind of silicon substrate fan-out-type wafer-level packaging method, comprising:
Silicon substrate is provided, etch heat dissipation channel in the silicon substrate front and deposits cutoff layer；
The first glass support plate is bonded on the cutoff layer；
Go out groove in the silicon substrate back-etching, is embedded to chip and is filled up with dry film material；
It is open at the pad of chip using photoetching, forms first layer wiring；
Successively made in the second glass support plate passivation layer, n-layer wiring and micro convex point, and with the first layer wire bond；
The second glass support plate is disassembled, and makes solder mask and salient point；
The first glass support plate is disassembled, single chip is cut into, completes encapsulation.
Optionally, go out groove in the silicon substrate back-etching, be embedded to chip and filled up with dry film material and include:
By grinding or etching technics by the silicon substrate thinning back side to target thickness, then etch groove；
By heat conductive adhesive glue by the chip buried groove, outwardly, the heat conductive adhesive glue is polymer to the pad of chip Material；
The gap between chip and silicon substrate is filled up with dry film material using vacuum film pressing technology, and surface is made smooth；Wherein,
The groove is embedded in the depth of the heat dissipation channel not less than 1 μm；
The height error of the chip is formed after embedment chip height and the silicon-base plane is no more than 5 μm.
Optionally, the quantity of the groove is greater than or equal to 1, and depth is not less than 10 μm；One is embedded in each groove Chip or multiple chips.
Optionally, the dry film material is the polymerizable material including resinae and polyimide.
Optionally, the second glass support plate is disassembled, and makes solder mask and salient point includes:.
Optionally, second glass support plate is dismantled by laser solution bonding pattern, and makes the last layer cloth Line；
Solder mask and salient point are formed on surface again.
Optionally, first glass support plate is bonded by temporarily bonding glue with the cutoff layer, and first glass carries Plate and second glass support plate include the interim bonding laser reactive layer for being bonded glass and being formed on the bonding glass； Wherein,
The thickness of the bonding glass is not less than 100 μm；The thickness of the interim bonding glue is not less than 1 μm, the interim bonding The thickness of laser reactive layer is not less than 0.1 μm.
Optionally, the width of the heat dissipation channel, length and depth are not less than 1 μm, and the quantity of the heat dissipation channel is not Less than 1.
Optionally, the material of the cutoff layer is the one or more or metal material one or more of inorganic material, Its thickness is not less than 0.1 μm,
The inorganic material includes SiO2, SiC and SiN；
The metal material includes Al, Cu, Ni, Sn and Au.
The present invention also provides a kind of silicon substrate fan-out-type wafer level packaging structures, are sealed by above-mentioned silicon substrate fan-out-type wafer scale Dress method is prepared.
A kind of silicon substrate fan-out-type wafer-level packaging method and structure are provided in the present invention, first offer silicon substrate, in institute It states silicon substrate front etching heat dissipation channel and deposits cutoff layer；The first glass support plate is bonded on the cutoff layer；Then described Silicon substrate back-etching goes out groove, is embedded to chip and is filled up with dry film material；It is open at the pad of chip followed by photoetching, shape It is routed at first layer；Successively made in the second glass support plate passivation layer, n-layer wiring and micro convex point, and with the first layer cloth Line bonding；The second glass support plate is disassembled again, and makes solder mask and salient point；The first glass support plate is disassembled, single chip is cut into, it is complete At encapsulation.
The present invention solves chip package heat dissipation problem, and heat dissipation channel by etching heat dissipation channel directly in silicon substrate Surface is deposited with cutoff layer, and silicon substrate groove is embedded into heat dissipation channel, increases heat dissipation area, and heat-sinking capability greatly enhances.Separately Outside, in order to solve the warpage issues of multiple wiring, n-layer wiring is formed by introducing glass support plate, by the first layer of itself and silicon substrate Wire bond completes final routing, to avoid the warpage issues caused by the multiple wiring of same matrix.Encapsulation work of the invention Skill is simple, at low cost, and scale of mass production is suitble to use.
Detailed description of the invention
Fig. 1 is silicon substrate fan-out-type wafer-level packaging method flow diagram provided by the invention；
Fig. 2 is the schematic diagram in silicon substrate front etching heat dissipation channel；
Fig. 3 is to deposit cutoff layer schematic diagram on heat dissipation channel surface；
Fig. 4 is the first glass support plate schematic diagram；
Fig. 5 is schematic diagram after silicon substrate surface and the bonding of the first glass support plate；
Fig. 6 is in silicon substrate back-etching groove schematic diagram；
Fig. 7 is by the schematic diagram in chip buried groove；
Fig. 8 is the schematic diagram for making dry film material；
Fig. 9 is production first layer schematic wiring diagram；
Figure 10 is the multilayer wiring schematic diagram in the second glass support plate；
Figure 11 is the schematic diagram by the multilayer wiring of the second glass support plate together with first layer wire bond；
Figure 12 is the schematic diagram for making the last layer wiring after removing the second glass support plate；
Figure 13 is the schematic diagram for making solder mask and salient point；
Figure 14 is the schematic diagram for removing the first glass support plate and being cut into single encapsulation chip.
Specific embodiment
Below in conjunction with the drawings and specific embodiments to a kind of silicon substrate fan-out-type wafer-level packaging method work proposed by the present invention It is further described.According to following explanation and claims, advantages and features of the invention will be become apparent from.It should be noted It is that attached drawing is all made of very simplified form and using non-accurate ratio, only to facilitate, lucidly aid in illustrating this hair The purpose of bright embodiment.
Embodiment one
The present invention provides a kind of silicon substrate fan-out-type wafer-level packaging methods, and process is as shown in Figure 1, include the following steps:
Step S11, silicon substrate is provided, etch heat dissipation channel in the silicon substrate front and deposits cutoff layer；
Step S12, the first glass support plate is bonded on the cutoff layer；
Step S13, go out groove in the silicon substrate back-etching, be embedded to chip and filled up with dry film material；
Step S14, it is open at the pad of chip using photoetching, forms first layer wiring；
Step S15, passivation layer, n-layer wiring and micro convex point are successively made in the second glass support plate, and are routed with the first layer Bonding；
Step S16, the second glass support plate is disassembled, and makes solder mask and salient point；
Step S17, the first glass support plate is disassembled, single chip is cut into, completes encapsulation.
Specifically, firstly, silicon substrate 101 is provided, in the 101 front etching heat dissipation channel 102 of silicon substrate, as shown in Fig. 2, simultaneously Deposit cutoff layer 103 as shown in Figure 3.Wherein, 103 thickness of cutoff layer is not less than 0.1 μm；The material of cutoff layer 103 can Think the one or more of inorganic material, such as SiO2, SiC and SiN；Or metal material it is one or more, as Al, Cu, Ni, Sn and Au etc..The quantity of the heat dissipation channel 102 be greater than or equal to 1, width, length and depth all 1 μm with On.
Then the first glass support plate is bonded on the cutoff layer 103, the first glass support plate structure as shown in figure 4, Including bonding glass 201 and the interim bonding laser reactive layer 202 being formed on the bonding glass 201.As shown in figure 5, institute It states the first glass support plate to be bonded on the cutoff layer 103 by temporarily bonding glue 203, the interim bonding glue 203 is filled into In the heat dissipation channel 102.Preferably, the thickness of the bonding glass 201 is at 100 μm or more, and the interim bonding glue is at 1 μm More than, the interim bonding laser reactive layer 202 is at 0.1 μm or more.
Then target thickness is thinned to by grinding or etching technics at 101 back side of silicon substrate, uses dry etching Method etches groove 104, as shown in fig. 6, the groove 104 is embedded in the depth h1 of the heat dissipation channel 102 not less than 1 μ M, the size of the groove 104 determine according to chip size to be embedded to, at least 10 μm of depth, the quantity of the groove 104 For one or more.
Referring to Fig. 7, chip 301 is embedded in the groove 104 by heat conductive adhesive glue 303, pad 302 outwardly, institute Stating heat conductive adhesive glue 303 is polymer material, and the height and the silicon substrate 101 that the chip 301 is formed after embedment chip 301 are flat The height error in face is no more than 5 μm.One or more chips 301 are embedded in each groove 104.Due to the groove 104 Bottom is embedded into the heat dissipation channel 102, increases heat dissipation area in this way, greatly improves heat-sinking capability.
Using vacuum film pressing technology, the gap dry film material 106 between chip 301 and silicon substrate 101 is filled up, while by table Wheat flour is made smooth；Recycle photoetching technique that will be open at pad, the width and depth of opening are at 1 μm or more, as shown in Figure 8. Preferably, shown dry film material 106 is the polymerizable material including resinae and polyimide.Then first layer is formed 107 connection pad 302 of wiring, as shown in Figure 9.
Such as Figure 10, passivation layer 108, n-layer wiring 109 and micro convex point 110 are successively made in the second glass support plate；Again by it It is bonded with first layer wiring 107, and fills passivation layer 111 at bond voids, such as Figure 11.Wherein, second glass Support plate is identical as first glass support plate, anti-including bonding glass and the interim bonding laser being formed on the bonding glass Answer layer；Wherein, the thickness of the bonding glass is not less than 100 μm；The thickness of the interim bonding glue is described to face not less than 1 μm The thickness of Shi Jianhe laser reactive layer is not less than 0.1 μm.
Second glass support plate is dismantled by laser solution bonding pattern, and forms the last layer wiring 114, such as Figure 12.
Solder mask 112 and salient point 113 are made on surface, such as Figure 13.First glass support plate is finally passed through into laser solution Bonding pattern dismantles, and the interim bonding glue 203 is cleaned up, and is cut into single chip, completes as shown in figure 14 Encapsulation.
Embodiment two
The present embodiment two provides a kind of silicon substrate fan-out-type wafer level packaging structure, is made by the method for embodiment one, Its structure is as shown in figure 14.The silicon substrate fan-out-type wafer level packaging structure includes silicon substrate 101, the first face of the silicon substrate 101 It is etched with heat dissipation channel 102, width, length and the depth of the heat dissipation channel 102 are not less than 1 μm, and the heat dissipation is logical The quantity in road 102 is not less than 1.Cutoff layer 103 is deposited on the heat dissipation channel 102.Preferably, the material of the cutoff layer 103 Matter is the one or more or metal material one or more of inorganic material, and thickness is not less than 0.1 μm；Wherein, the nothing Machine material includes SiO2, SiC and SiN；The metal material includes Al, Cu, Ni, Sn and Au.
Second face of the silicon substrate 101 is etched with one or more groove 104, and depth is not less than 10 μm；It is described recessed Slot 104 is embedded in the depth of the heat dissipation channel 102 not less than 1 μm.A chip or multiple cores are embedded in each groove 104 Piece.Specifically, the chip 301 is embedded in the groove 104 by heat conductive adhesive glue 303, it is embedded to the chip after chip 301 The height error of 301 height formed and 101 plane of silicon substrate is no more than 5 μm.Further, the chip 301 with it is described Gap between silicon substrate 101 is filled with dry film material 106；Further, the dry film material 106 be include resinae and polyamides Polymerizable material including imines.The pad 302 of the chip 301 passes through first layer wiring 107 and micro convex point 110 and n-layer 109 connection of wiring；Passivation layer 111 is filled between the first layer wiring 107, the micro convex point 110 and n-layer wiring 109.
The n-layer wiring 109 is connected with the last layer wiring 114, and production has solder mask in the last layer wiring 114 112 and salient point 113, the fully wrapped around the last layer wiring 114 of solder mask 112.
Foregoing description is only the description to present pre-ferred embodiments, not to any restriction of the scope of the invention, this hair Any change, the modification that the those of ordinary skill in bright field does according to the disclosure above content, belong to the protection of claims Range.

Claims (9)

1. a kind of silicon substrate fan-out-type wafer-level packaging method characterized by comprising
Silicon substrate is provided, etch heat dissipation channel in the silicon substrate front and deposits cutoff layer；
The first glass support plate is bonded on the cutoff layer；
Go out groove in the silicon substrate back-etching, is embedded to chip and is filled up with dry film material；
It is open at the pad of chip using photoetching, forms first layer wiring；
Successively made in the second glass support plate passivation layer, n-layer wiring and micro convex point, and with the first layer wire bond；
The second glass support plate is disassembled, and makes solder mask and salient point；
The first glass support plate is disassembled, single chip is cut into, completes encapsulation.
2. silicon substrate fan-out-type wafer-level packaging method as described in claim 1, which is characterized in that in the silicon substrate back-etching Groove out is embedded to chip and is filled up with dry film material and include:
By grinding or etching technics by the silicon substrate thinning back side to target thickness, then etch groove；
By heat conductive adhesive glue by the chip buried groove, outwardly, the heat conductive adhesive glue is polymer to the pad of chip Material；
The gap between chip and silicon substrate is filled up with dry film material using vacuum film pressing technology, and surface is made smooth；Wherein,
The groove is embedded in the depth of the heat dissipation channel not less than 1 μm；
The height error of the chip is formed after embedment chip height and the silicon-base plane is no more than 5 μm.
3. silicon substrate fan-out-type wafer-level packaging method as claimed in claim 2, which is characterized in that the quantity of the groove is greater than Or it is equal to 1, depth is not less than 10 μm；A chip or multiple chips are embedded in each groove.
4. silicon substrate fan-out-type wafer-level packaging method as claimed in claim 2, which is characterized in that the dry film material is to include Polymerizable material including resinae and polyimide.
5. silicon substrate fan-out-type wafer-level packaging method as described in claim 1, which is characterized in that the second glass support plate of dismantling, And make solder mask and salient point includes:
Second glass support plate is dismantled by laser solution bonding pattern, and makes the last layer wiring；
Solder mask and salient point are formed on surface again.
6. silicon substrate fan-out-type wafer-level packaging method as described in claim 1, which is characterized in that first glass support plate is logical It crosses interim bonding glue to be bonded with the cutoff layer, first glass support plate and second glass support plate include bonding glass With the interim bonding laser reactive layer being formed on the bonding glass；Wherein,
The thickness of the bonding glass is not less than 100 μm；The thickness of the interim bonding glue is not less than 1 μm, the interim bonding The thickness of laser reactive layer is not less than 0.1 μm.
7. silicon substrate fan-out-type wafer-level packaging method as described in claim 1, which is characterized in that the width of the heat dissipation channel Degree, length and depth are not less than 1 μm, and the quantity of the heat dissipation channel is not less than 1.
8. silicon substrate fan-out-type wafer-level packaging method as described in claim 1, which is characterized in that the material of the cutoff layer is Inorganic material it is one or more or metal material one or more, thickness be not less than 0.1 μm,
The inorganic material includes SiO2, SiC and SiN；
The metal material includes Al, Cu, Ni, Sn and Au.
9. a kind of silicon substrate fan-out-type wafer level packaging structure, which is characterized in that fanned by any silicon substrate of claim 1-8 Type wafer-level packaging method is made out.
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Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111725154A (en) * 2020-06-29 2020-09-29 上海先方半导体有限公司 Packaging structure of embedded device and manufacturing method
CN112530813A (en) * 2020-11-30 2021-03-19 复旦大学 Temporary bonding method
CN112786448A (en) * 2021-03-15 2021-05-11 绍兴同芯成集成电路有限公司 Processing technology of IGBT wafer
CN113035756A (en) * 2021-03-24 2021-06-25 绍兴同芯成集成电路有限公司 Method for radiating substrate in ultrathin wafer processing by using glass carrier plate
CN115799184A (en) * 2023-02-13 2023-03-14 江西萨瑞半导体技术有限公司 Semiconductor packaging method

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050224968A1 (en) * 2004-03-31 2005-10-13 Aptos Corporation Wafer level mounting frame for ball grid array packaging, and method of making and using the same
CN101350338A (en) * 2007-07-17 2009-01-21 南亚电路板股份有限公司 Embedded type chip substrate structure
CN105023900A (en) * 2015-08-11 2015-11-04 华天科技（昆山）电子有限公司 Embedded silicon substrate fan-out type packaging structure and manufacturing method thereof
CN204885147U (en) * 2015-08-11 2015-12-16 华天科技（昆山）电子有限公司 Bury silicon substrate fan -out type packaging structure
CN107452689A (en) * 2017-09-14 2017-12-08 厦门大学 The embedded fan-out-type silicon pinboard and preparation method of three-dimensional systematic package application
CN107946254A (en) * 2017-12-18 2018-04-20 华天科技（昆山）电子有限公司 The silicon substrate fan-out package and wafer-level packaging method of integrated heat dissipation structure
CN210224007U (en) * 2019-07-31 2020-03-31 中国电子科技集团公司第五十八研究所 Silicon-based fan-out type wafer level packaging structure

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050224968A1 (en) * 2004-03-31 2005-10-13 Aptos Corporation Wafer level mounting frame for ball grid array packaging, and method of making and using the same
CN101350338A (en) * 2007-07-17 2009-01-21 南亚电路板股份有限公司 Embedded type chip substrate structure
CN105023900A (en) * 2015-08-11 2015-11-04 华天科技（昆山）电子有限公司 Embedded silicon substrate fan-out type packaging structure and manufacturing method thereof
CN204885147U (en) * 2015-08-11 2015-12-16 华天科技（昆山）电子有限公司 Bury silicon substrate fan -out type packaging structure
WO2017024892A1 (en) * 2015-08-11 2017-02-16 华天科技（昆山）电子有限公司 Embedded silicon substrate fan-out type packaging structure and manufacturing method therefor
CN107452689A (en) * 2017-09-14 2017-12-08 厦门大学 The embedded fan-out-type silicon pinboard and preparation method of three-dimensional systematic package application
CN107946254A (en) * 2017-12-18 2018-04-20 华天科技（昆山）电子有限公司 The silicon substrate fan-out package and wafer-level packaging method of integrated heat dissipation structure
CN210224007U (en) * 2019-07-31 2020-03-31 中国电子科技集团公司第五十八研究所 Silicon-based fan-out type wafer level packaging structure

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
吉勇: "《硅基密封气密性及结构强度研究》", 《电子与封装》, no. 8, 31 August 2014 (2014-08-31), pages 15 - 17 *

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN111725154A (en) * 2020-06-29 2020-09-29 上海先方半导体有限公司 Packaging structure of embedded device and manufacturing method
CN112530813A (en) * 2020-11-30 2021-03-19 复旦大学 Temporary bonding method
CN112786448A (en) * 2021-03-15 2021-05-11 绍兴同芯成集成电路有限公司 Processing technology of IGBT wafer
CN112786448B (en) * 2021-03-15 2022-05-31 绍兴同芯成集成电路有限公司 Processing technology of IGBT wafer
CN113035756A (en) * 2021-03-24 2021-06-25 绍兴同芯成集成电路有限公司 Method for radiating substrate in ultrathin wafer processing by using glass carrier plate
CN115799184A (en) * 2023-02-13 2023-03-14 江西萨瑞半导体技术有限公司 Semiconductor packaging method

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