CN105428331B - It is a kind of that 2.5D/3D encapsulating structures are fanned out to based on carrier - Google Patents
It is a kind of that 2.5D/3D encapsulating structures are fanned out to based on carrier Download PDFInfo
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- CN105428331B CN105428331B CN201510969543.9A CN201510969543A CN105428331B CN 105428331 B CN105428331 B CN 105428331B CN 201510969543 A CN201510969543 A CN 201510969543A CN 105428331 B CN105428331 B CN 105428331B
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- chip
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
The invention belongs to Electronic Packaging field, more particularly to a kind of 2.5/3D encapsulating structures, including TSV pinboards, flip-chip, underfill, plastic packaging material, BGA soldered balls etc. are fanned out to based on carrier.Flip-chip flip chip bonding is in the front of TSV pinboards；Plastic packaging material encapsulates all chips and TSV pinboards；TSV switching backs plant BGA soldered balls.The structure combines the plate technique that is fanned out to and transfers and realizes system in package, reduces production cost；Be conducive to reduce warpage, reduce chip offset amount, improve the feasibility of technique and the reliability of packaging body.
Description
Technical field
The invention belongs to Electronic Packaging field, more particularly to a kind of 2.5/3D encapsulating structures are fanned out to based on carrier.
Background technology
With the requirement drive of consumer electronics product, such as smart mobile phone, tablet computer, the encapsulation of electronic product towards
Thin, small and inexpensive direction is developed.The current Advanced Packaging method in relation to 2.5D and 3D has obtained the concern of industry, and obtains
Certain development result.But the Advanced Packaging design based on silicon hole is faced with many technical barriers and that cost remains high is tired
Border.
To be fanned out to encapsulation be a kind of new Advanced Packaging method for releasing in recent years, the wafer-level packaging manufacture of its initial combination
Technology and the conventional package advantage of single nude film carry out batch micro operations, so as to considerably reduce the packaging cost of electronic product.
Packaging technology flow typically is fanned out to, nude film front is mounted on silicon wafer carrier first, carrier wafer is torn open bonding after plastic packaging,
Thereafter RDL is made（Wiring layer again）And ball is planted, reliability test and product packaging are done in finally section.
At present, either wafer scale is fanned out to encapsulation or plate level is fanned out to encapsulation and faces two big technological challenges, first, warpage
Problem, second, chip offset.Warpage issues are mainly due to the package material that different heat expansion coefficient is employed in packaging technology
Material, such as plastic packaging material, chip and carrier.If used storeroom thermal coefficient of expansion mismatches, can cause several millimeters, it is even several
Ten millimeters of big warpage.Chip offset occurs harmomegathus in curing process mainly due to plastic packaging material and causes.Therefore plastic packaging material pair
The reliability effect of whole encapsulating structure should not be underestimated.
The content of the invention
In order to solve the above technical problems, 2.5/3D encapsulating structures are fanned out to based on carrier the present invention provides a kind of, should
Encapsulating structure combines the plate technique that is fanned out to and transfers and realizes system in package, is encapsulated compared to traditional 2.5D/3D, reduces thickness,
Reduce production cost, be conducive to reduce warpage, reduce chip offset amount, improve technique feasibility and packaging body it is reliable
Property.
Solve above technical problem the present invention in it is a kind of 2.5/3D encapsulating structures are fanned out to based on carrier, its feature exists
In：Including TSV pinboards, flip-chip, underfill, plastic packaging material, BGA soldered balls, flip-chip flip chip bonding is in TSV pinboards
Front；Plastic packaging material encapsulates flip-chip and TSV pinboards, and exposed TSV switching backs；TSV switching backs plant BGA
Soldered ball, underfill is between flip-chip and TSV pinboards.
The flip-chip is single bare chip, or more bare chips, or single group multiple-level stack chip assembly, or some groups
Multiple-level stack chip assembly, or the combination of bare chip and multiple-level stack chip.
The single bare chip flip chip bonding is on each TSV pinboards；The more bare chips distinguish flip chip bonding each
On TSV pinboards；The single group multiple-level stack chip assembly is assembled on each TSV pinboards；Some groups of multiple-level stacks
Chip assembly is respectively assembled on each TSV pinboards；Bare chip and the multiple-level stack chip is respectively assembled in each TSV and turns
On fishplate bar.
The TSV pinboards are silicon pinboard, and silicon pinboard is equipped with silicon hole, electro-coppering in silicon hole；TSV pinboards
Front and back is respectively equipped with again wiring layer I and II.
There is multilayer wiring layer I again in the TSV pinboards front, then has micro convex point between wiring layer I and flip-chip.
Passivation layer 1, again Seed Layer 1, wiring layer II are also equipped with successively between the TSV switching backs and BGA soldered balls, it is blunt
Change layer 2, Seed Layer 2, UBM bottom metal layers.
The Seed Layer 1, again wiring layer II, Seed Layer 2 and the interconnection of UBM bottom metal layers.
The flip-chip passes through micro convex point, again wiring layer I, again pinboard silicon hole, wiring layer II, UBM bottom metals
Layer and the interconnection of BGA balls.
The passivation material is PI or PBO, seed layer materials Ti/Cu.
The thickness of the wiring layer again is about 3 ~ 5 μm, and material is copper.The front that chips of the present invention pass through TSV pinboards
RDL is interconnected, and is then drawn and is fanned out on following BGA soldered balls by silicon hole, to be welded with pcb board.Make
With TSV pinboards, the occupied space of encapsulation chip is effectively have compressed, makes the plastic-sealed body that plastic packaging is formed be conducive to subtract than relatively thin
Wait a little while,please and encapsulate the chip influence different from plastic packaging isolator CTE.And it is simple in structure, make production cost low.
Structure in the present invention combine wafer level be fanned out to technology and switching plate technique realize system in package, reduce life
Produce cost；Amount of warpage can be reduced, reduces chip offset amount, is conducive to improve the feasibility of technique.
Brief description of the drawings
Fig. 1 is encapsulating structure schematic diagram in the present invention
Fig. 2 is TSV pinboard of the single front with wiring layer again in the present invention
Fig. 3-13 is the structure diagram that encapsulating structure forms in flow in the present invention
Wherein, mark is specially in figure：1.TSV pinboards, 2. flip-chips, 3. underfills, 4. plastic packaging materials,
5.BGA soldered balls, 6. pinboard silicon holes, 7. wiring layer I again, 8. wiring layer II again, 9. micro convex points, 10. passivation layer, 1,11. seed
Layer 1,12. passivation layer, 2., 13. Seed Layer 2,14.UBM bottom metal layers, 15. temporary adhesion glue, 16. support plates
Embodiment
All features disclosed in this specification, or disclosed all methods or during the step of, except mutually exclusive
Feature and/or step beyond, can combine in any way.
This specification（Including any accessory claim, summary）Disclosed in any feature, unless specifically stated,
Replaced by other equivalent or with similar purpose alternative features.I.e., unless specifically stated, each feature is a series of
An example in equivalent or similar characteristics.
Embodiment 1
It is a kind of that 2.5/3D encapsulating structures, including TSV pinboards, flip-chip, underfill, modeling are fanned out to based on carrier
Envelope material, BGA soldered balls, flip-chip flip chip bonding is in the front of TSV pinboards；Plastic packaging material encapsulates flip-chip and TSV pinboards,
And exposed TSV switchings back；TSV switching backs plant BGA soldered balls, and underfill is located at flip-chip and TSV pinboards
Between.
Flip-chip is single bare chip, or more bare chips, or single group multiple-level stack chip assembly, or some groups of multilayers
Stacked chips component.Single bare chip flip chip bonding is on each TSV pinboards；The more bare chips distinguish flip chip bonding each
On TSV pinboards；The single group multiple-level stack chip assembly is assembled on each TSV pinboards；Some groups of multiple-level stacks
Chip assembly is respectively assembled on each TSV pinboards.
TSV pinboards are silicon pinboard, and silicon pinboard is equipped with silicon hole, electro-coppering in silicon hole；TSV pinboards front
1 layer of wiring layer I and wiring layer II again again are respectively equipped with the back side.The thickness of wiring layer I or II is about 3 ~ 5 μm again, and material is copper.
TSV, which transfers also to be equipped with successively between back and BGA soldered balls, is followed successively by passivation layer 1, again Seed Layer 1, wiring layer II,
Passivation layer 2, Seed Layer 2, UBM bottom metal layers.Passivation material is PI or PBO, seed layer materials Ti/Cu.
Seed Layer 1, again wiring layer II, Seed Layer 2 and the interconnection of UBM bottom metal layers.Flip-chip by wiring layer I again,
Pinboard silicon hole, again wiring layer II, UBM bottom metal layers and the interconnection of BGA balls.
Embodiment 2
It is a kind of that 2.5/3D encapsulating structures, including TSV pinboards, flip-chip, underfill, modeling are fanned out to based on carrier
Envelope material, BGA soldered balls, flip-chip flip chip bonding is in the front of TSV pinboards；Plastic packaging material encapsulates flip-chip and TSV pinboards,
And exposed TSV switchings back；TSV switching backs plant BGA soldered balls, and underfill is located at flip-chip and TSV pinboards
Between.
Flip-chip is the combination of bare chip and multiple-level stack chip, and bare chip and multiple-level stack chip are respectively assembled in often
On a TSV pinboards.
TSV pinboards are silicon pinboard, and silicon pinboard is equipped with silicon hole, electro-coppering in silicon hole；TSV pinboards front
3 layers of wiring layer I and wiring layer II again again are respectively equipped with the back side.There is micro convex point between wiring layer I and flip-chip again.Connect up again
The thickness of layer I or II is about 3 ~ 5 μm, and material is copper.
TSV transfers also is equipped with passivation layer 1, again Seed Layer 1, wiring layer II, passivation layer successively between back and BGA soldered balls
2nd, Seed Layer 2, bottom metal layers.Passivation material is PI or PBO, seed layer materials Ti/Cu.
Seed Layer 1, again wiring layer II, Seed Layer 2 and the interconnection of UBM bottom metal layers.Flip-chip passes through micro convex point, again cloth
Line layer I, again pinboard silicon hole, wiring layer II, UBM bottom metal layers and the interconnection of BGA balls.
The formation to the structure in the present invention is described in detail below in conjunction with the accompanying drawings：
（1）Prepare TSV pinboard of the front with multilayer wiring layer again, the thickness of every layer of wiring layer again is about 3 ~ 5 μm, material
For copper, thinning back side is to less than 200 μm, and TSV copper facing and singulation are revealed in the back side, as shown in Figure 4；
（2）2.5D/3D encapsulating structures need support plate in the production process, and support plate shape is square or circular, circular support plate
The optional silicon of material or glass etc.；The optional glass of square support plate or double face copper etc..
（3）Ephemeral key rubber alloy is coated on support plate, bonding is torn open for pasting pinboard and follow-up, as shown in figure 5, described
Circular carrier plate material optional silicon, glass and kovar alloy material etc.；
（4）TSV switching plate arrays are affixed on support plate, are covered with circular support plate, face-up, as shown in Figure 6；
（5）Flip-chip upside-down mounting is soldered on each pinboard, and fills underfill, as shown in Figure 7；
Flip-chip is single bare chip, or more bare chips, or single group multiple-level stack chip assembly, or some groups of multilayers
Stacked chips component, or the combination of bare chip and multiple-level stack chip.
Single bare chip flip chip bonding is on each TSV pinboards；The more bare chips difference flip chip bonding turns in each TSV
On fishplate bar；It is assembled in if single group multiple-level stack chip assembly on each TSV pinboards；If some groups of multiple-level stack chipsets
Part is respectively assembled on each TSV pinboards；Each TSV pinboards are respectively assembled in if bare chip and multiple-level stack chip
On.
（6）By metaideophone shaping or compressing and forming process or other plastic package process by plastic packaging glue seal to each pinboard it
Between, between chip and chip upper surface, and carry out solidify afterwards processing, as shown in Figure 8；
（7）Circular or square support plate is carried out tearing bonding open, circular or square support plate of dismantling, as shown in Figure 9；
（8）180 ° of upset, makes one layer of passivation layer, windowing, passivation material is PI or PBO, sputtering in switching back
One layer of Seed Layer, seed layer materials Ti/Cu, one layer of RDL is made in switching back；One layer of Seed Layer is sputtered, makes UBM
Bottom metal layers, plant BGA soldered balls, cut into slices and tested.As shown in Figure 10-Figure 13；
By above-mentioned steps, system in package is substantially finished.
The invention is not limited in foregoing embodiment.The present invention, which expands to, any in the present specification to be disclosed
New feature or any new combination, and disclose any new method or process the step of or any new combination.
Claims (9)
1. a kind of be fanned out to 2.5D/3D encapsulating structures based on carrier, it is characterised in that：The structure is by TSV pinboards（1）, fall
Cartridge chip（2）, underfill（3）, plastic packaging material（4）, BGA soldered balls（5）Composition, flip-chip（2）Flip chip bonding is in TSV pinboards
（1）Front；Plastic packaging material（4）Encapsulate flip-chip（2）And TSV pinboards（1）, and exposed TSV pinboards（1）The back side；TSV
Pinboard（1）Plant BGA soldered balls in the back side（5）, underfill（3）Positioned at flip-chip（2）With TSV pinboards（1）Between；It is described
TSV pinboards（1）There is multilayer wiring layer I again in front（7）, then wiring layer I（7）With flip-chip（2）Between have micro convex point（9）；
The TSV pinboards（1）For thinning back side to less than 200 μm, TSV copper facing and singulation are revealed in the back side.
A kind of 2.5D/3D encapsulating structures are fanned out to based on carrier 2. according to claim 1, it is characterised in that：It is described fall
Cartridge chip（2）For single bare chip, or more bare chips, or single group multiple-level stack chip assembly, or some groups of multiple-level stack cores
Piece component, or the combination of bare chip and multiple-level stack chip.
A kind of 2.5D/3D encapsulating structures are fanned out to based on carrier 3. according to claim 2, it is characterised in that：The list
Bare chip flip chip bonding is in each TSV pinboards（1）On；The more bare chips distinguish flip chip bonding in each TSV pinboards（1）
On；The single group multiple-level stack chip assembly is assembled in each TSV pinboards（1）On；Some groups of multiple-level stack chipsets
Part is respectively assembled in each TSV pinboards（1）On；Bare chip and the multiple-level stack chip is respectively assembled in each TSV switchings
Plate（1）On.
A kind of 2.5D/3D encapsulating structures are fanned out to based on carrier 4. according to claim 1, it is characterised in that：It is described
TSV pinboards（1）For silicon pinboard, silicon pinboard is equipped with pinboard silicon hole（6）, electro-coppering in pinboard silicon hole；TSV
Pinboard（1）Front and back is respectively equipped with wiring layer I again（7）Wiring layer II again（8）.
A kind of 2.5D/3D encapsulating structures are fanned out to based on carrier 5. according to claim 1, it is characterised in that：It is described
TSV pinboards（1）The back side and BGA soldered balls（5）Between be also equipped with passivation layer 1 successively（10）, Seed Layer 1（11）, wiring layer II again
（8）, passivation layer 2（12）, Seed Layer 2（13）, UBM bottom metal layers（14）.
A kind of 2.5D/3D encapsulating structures are fanned out to based on carrier 6. according to claim 5, it is characterised in that：The kind
Sublayer 1（11）, wiring layer II again（8）, Seed Layer 2（13）With UBM bottom metal layers（14）Interconnection.
A kind of 2.5D/3D encapsulating structures are fanned out to based on carrier 7. according to claim 1, it is characterised in that：It is described fall
Cartridge chip（2）Pass through micro convex point（9）, wiring layer I again（7）, pinboard silicon hole（6）, wiring layer II again（8）, UBM bottom metals
Layer（14）With BGA soldered balls（5）Interconnection.
A kind of 2.5D/3D encapsulating structures are fanned out to based on carrier 8. according to claim 5, it is characterised in that：It is described blunt
Change layer material is PI or PBO, seed layer materials Ti/Cu.
9. a kind of according to any one of claim 1,4-7 is fanned out to 2.5D/3D encapsulating structures based on carrier, it is special
Sign is：Wiring layer I again（7）Or wiring layer II again（8）Thickness be 3 ~ 5 μm, material is copper.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201510969543.9A CN105428331B (en) | 2015-12-22 | 2015-12-22 | It is a kind of that 2.5D/3D encapsulating structures are fanned out to based on carrier |
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|---|---|---|---|
| CN201510969543.9A CN105428331B (en) | 2015-12-22 | 2015-12-22 | It is a kind of that 2.5D/3D encapsulating structures are fanned out to based on carrier |
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| Publication Number | Publication Date |
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| CN105428331A CN105428331A (en) | 2016-03-23 |
| CN105428331B true CN105428331B (en) | 2018-04-20 |
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Families Citing this family (13)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN106783776A (en) * | 2016-12-26 | 2017-05-31 | 华进半导体封装先导技术研发中心有限公司 | Chip-packaging structure and method |
| CN106783760A (en) * | 2016-12-26 | 2017-05-31 | 华进半导体封装先导技术研发中心有限公司 | Chip-packaging structure and method |
| CN106960825A (en) * | 2017-03-08 | 2017-07-18 | 华进半导体封装先导技术研发中心有限公司 | A kind of two-sided fan-out packaging structure and method for packing based on silicon pinboard |
| CN107611045A (en) * | 2017-09-29 | 2018-01-19 | 中芯长电半导体（江阴）有限公司 | A kind of three-dimensional chip encapsulating structure and its method for packing |
| CN109945852B (en) * | 2019-03-22 | 2021-05-28 | 中国科学院微电子研究所 | Packaging structure of gyroscope and manufacturing method |
| CN110071047B (en) * | 2019-04-28 | 2020-12-18 | 北京航天控制仪器研究所 | Method for manufacturing silicon-based adapter plate for micro-system integrated application |
| CN110634832A (en) * | 2019-08-29 | 2019-12-31 | 上海先方半导体有限公司 | Packaging structure based on through silicon via adapter plate and manufacturing method thereof |
| CN110676240A (en) * | 2019-10-16 | 2020-01-10 | 上海先方半导体有限公司 | 2.5D packaging structure and manufacturing method thereof |
| CN114762103A (en) * | 2019-12-16 | 2022-07-15 | 华为技术有限公司 | Chip stacking structure and manufacturing method thereof |
| CN112908946B (en) * | 2021-01-18 | 2023-05-23 | 上海先方半导体有限公司 | Packaging structure for reducing warpage of plastic packaging wafer and manufacturing method thereof |
| CN113066771B (en) * | 2021-03-23 | 2023-12-05 | 浙江集迈科微电子有限公司 | Multilayer stacked microsystem structure |
| CN113192936B (en) * | 2021-04-23 | 2024-02-13 | 泓林微电子（昆山）有限公司 | Double-sided chip packaging structure |
| CN115312496A (en) * | 2022-07-12 | 2022-11-08 | 武汉大学 | Three-dimensional semiconductor integrated packaging structure and process based on rear through hole technology |
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| CN105428331A (en) | 2016-03-23 |
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