CN110379780B - Silicon-based fan-out type wafer level packaging method and structure - Google Patents

Silicon-based fan-out type wafer level packaging method and structure Download PDF

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CN110379780B
CN110379780B CN201910701998.0A CN201910701998A CN110379780B CN 110379780 B CN110379780 B CN 110379780B CN 201910701998 A CN201910701998 A CN 201910701998A CN 110379780 B CN110379780 B CN 110379780B
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layer
silicon
chip
bonding
glass carrier
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CN110379780A (en
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王成迁
明雪飞
吉勇
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CETC 58 Research Institute
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
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    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
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    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
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    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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    • H01L2224/922—Connecting different surfaces of the semiconductor or solid-state body with connectors of different types
    • H01L2224/9222—Sequential connecting processes
    • H01L2224/92242—Sequential connecting processes the first connecting process involving a layer connector
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
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    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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Abstract

The invention discloses a silicon-based fan-out type wafer level packaging method and structure, and belongs to the technical field of integrated circuit packaging. Firstly, providing silicon base, etching a heat dissipation channel on the front surface of the silicon base, and depositing a stop layer; bonding a first glass carrier plate on the cut-off layer; etching a groove on the back surface of the silicon substrate, burying a chip and filling the chip with a dry film material; then, opening the bonding pad of the chip by utilizing photoetching to form a first layer of wiring; sequentially manufacturing a passivation layer, n layers of wiring and micro-salient points on a second glass carrier plate, and bonding the passivation layer, the n layers of wiring and the micro-salient points with the first layer of wiring; disassembling the second glass carrier plate and manufacturing a solder mask layer and salient points; and disassembling the first glass carrier plate, and cutting the first glass carrier plate into single chips to finish packaging.

Description

Silicon-based fan-out type wafer level packaging method and structure
Technical Field
The invention relates to the technical field of integrated circuit packaging, in particular to a silicon-based fan-out type wafer level packaging method and structure.
Background
Currently, integrated circuit packages are developed towards three-dimensional system-in-package, and as the requirements on integration level and performance are higher and higher, the frequency, bandwidth and processing speed of chips are continuously improved, so that the energy consumption of the chip packages is greatly increased, and higher requirements are also put on the heat dissipation capability of the packages. The invention patent with application number 201711364900.4 provides a silicon-based fan-out type packaging and wafer level packaging method of an integrated heat dissipation structure, wherein the etching depth of a groove on the back surface of a silicon substrate and a heat dissipation channel on the front surface of the silicon substrate is difficult to control, the groove of the heat dissipation channel is penetrated due to the excessive etching depth, and the heat dissipation effect is poor due to the excessively small etching depth.
In addition, as the capability of the wafer manufacturing process is continuously enhanced, the number of the chip I/Os is increased, and the demand for the high-integration three-dimensional system-in-package is increased, so that the number of rewiring layers of the wafer-in-package is also increased continuously, the wafer flow difficulty is increased continuously due to warpage caused by multiple wiring, meanwhile, the photoetching precision is seriously influenced by the warpage, and the method becomes a great obstacle for the development of the high-integration three-dimensional system-in-package.
Disclosure of Invention
The invention aims to provide a silicon-based fan-out type wafer level packaging method and a silicon-based fan-out type wafer level packaging structure, which are used for solving the problems that the traditional chip packaging structure is poor in heat dissipation capacity and multi-layer wiring is easy to warp.
In order to solve the above technical problems, the present invention provides a silicon-based fan-out wafer level packaging method, which includes:
providing silicon base, etching a heat dissipation channel on the front surface of the silicon base and depositing a stop layer;
bonding a first glass carrier plate on the cut-off layer;
etching a groove on the back surface of the silicon substrate, embedding a chip and filling the chip with a dry film material;
forming a first layer of wiring by opening a bonding pad of the chip by photolithography;
sequentially manufacturing a passivation layer, n layers of wiring and micro-salient points on a second glass carrier plate, and bonding the passivation layer, the n layers of wiring and the micro-salient points with the first layer of wiring;
disassembling the second glass carrier plate and manufacturing a solder mask layer and salient points;
and disassembling the first glass carrier plate, and cutting the first glass carrier plate into single chips to finish packaging.
Optionally, etching a groove on the back surface of the silicon substrate, embedding the chip and filling with a dry film material includes:
thinning the back surface of the silicon substrate to a target thickness through a grinding or etching process, and etching a groove;
embedding a chip into the groove through heat-conducting adhesive, wherein a bonding pad of the chip faces outwards, and the heat-conducting adhesive is made of polymer materials;
filling the gap between the chip and the silicon substrate with a dry film material by using a vacuum film pressing technology, and making the surface smooth; wherein,
the depth of the groove embedded into the heat dissipation channel is not less than 1 mu m;
and after the chip is embedded, the height error between the height formed by the chip and the height of the silicon-based plane is not more than 5 mu m.
Optionally, the number of the grooves is greater than or equal to 1, and the depth of the grooves is not less than 10 μm; one chip or a plurality of chips are embedded in each groove.
Optionally, the dry film material is a polymer material including resins and polyimides.
Optionally, disassembling the second glass carrier plate, and manufacturing the solder mask layer and the bump includes: .
Optionally, the second glass carrier plate is disassembled in a laser bonding-breaking mode, and a final layer of wiring is manufactured;
and forming a solder mask layer and bumps on the surface.
Optionally, the first glass carrier plate is bonded with the cut-off layer through temporary bonding glue, and the first glass carrier plate and the second glass carrier plate both comprise bonding glass and a temporary bonding laser reaction layer formed on the bonding glass; wherein,
the thickness of the bonding glass is not less than 100 mu m; the thickness of the temporary bonding adhesive is not smaller than 1 mu m, and the thickness of the temporary bonding laser reaction layer is not smaller than 0.1 mu m.
Optionally, the width, length and depth of the heat dissipation channels are not less than 1 μm, and the number of the heat dissipation channels is not less than 1.
Optionally, the material of the stop layer is one or more of inorganic materials or one or more of metal materials, the thickness of the stop layer is not less than 0.1 mu m,
the inorganic material comprises SiO2, siC and SiN;
the metal material includes Al, cu, ni, sn and Au.
The invention also provides a silicon-based fan-out type wafer level packaging structure, which is prepared by the silicon-based fan-out type wafer level packaging method.
The invention provides a silicon-based fan-out type wafer level packaging method and a structure, wherein silicon-based is provided firstly, a heat dissipation channel is etched on the front surface of the silicon-based, and a stop layer is deposited; bonding a first glass carrier plate on the cut-off layer; etching a groove on the back surface of the silicon substrate, burying a chip and filling the chip with a dry film material; then, opening the bonding pad of the chip by utilizing photoetching to form a first layer of wiring; sequentially manufacturing a passivation layer, n layers of wiring and micro-salient points on a second glass carrier plate, and bonding the passivation layer, the n layers of wiring and the micro-salient points with the first layer of wiring; disassembling the second glass carrier plate and manufacturing a solder mask layer and salient points; and disassembling the first glass carrier plate, and cutting the first glass carrier plate into single chips to finish packaging.
According to the invention, the heat dissipation problem of the chip package is solved by directly etching the heat dissipation channel on the silicon substrate, the stop layer is deposited on the surface of the heat dissipation channel, the silicon substrate groove is embedded into the heat dissipation channel, the heat dissipation area is increased, and the heat dissipation capacity is greatly enhanced. In addition, in order to solve the warpage problem of multiple wiring, n layers of wiring are formed by introducing a glass carrier plate, and the n layers of wiring are bonded with a first layer of silicon-based wiring to complete final wiring, so that the warpage problem caused by multiple wiring on the same substrate is avoided. The invention has simple packaging technology and low cost, and is suitable for large-scale mass production.
Drawings
FIG. 1 is a schematic flow diagram of a silicon-based fan-out wafer level packaging method provided by the invention;
FIG. 2 is a schematic illustration of etching a heat dissipation channel in a front side of a silicon substrate;
FIG. 3 is a schematic illustration of the deposition of a cutoff layer on the surface of a heat dissipation channel;
FIG. 4 is a schematic view of a first glass carrier plate;
FIG. 5 is a schematic illustration of a silicon-based surface bonded to a first glass carrier;
FIG. 6 is a schematic illustration of etching a recess in a silicon-based backside;
FIG. 7 is a schematic illustration of a chip being embedded in a recess;
FIG. 8 is a schematic diagram of the fabrication of a dry film material;
FIG. 9 is a schematic diagram of making a first layer of wiring;
FIG. 10 is a schematic view of a multilayer wiring on a second glass carrier plate;
FIG. 11 is a schematic diagram of bonding together the multilayer wiring of the second glass carrier plate with the first layer wiring;
FIG. 12 is a schematic illustration of the final layer of wiring with the second glass carrier removed;
FIG. 13 is a schematic illustration of the fabrication of solder resist layers and bumps;
fig. 14 is a schematic view with the first glass carrier removed and cut into individual packaged chips.
Detailed Description
The following describes a silicon-based fan-out wafer level packaging method according to the present invention in further detail with reference to the accompanying drawings and specific embodiments. Advantages and features of the invention will become more apparent from the following description and from the claims. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
Example 1
The invention provides a silicon-based fan-out type wafer level packaging method, which is shown in a figure 1 and comprises the following steps:
step S11, providing silicon base, etching a heat dissipation channel on the front surface of the silicon base and depositing a stop layer;
step S12, bonding a first glass carrier plate on the cut-off layer;
step S13, etching a groove on the back surface of the silicon substrate, embedding a chip and filling the chip with a dry film material;
step S14, opening at a bonding pad of a chip by utilizing photoetching to form a first layer of wiring;
step S15, sequentially manufacturing a passivation layer, n layers of wiring and micro-salient points on a second glass carrier plate, and bonding the passivation layer, the n layers of wiring and the micro-salient points with the first layer of wiring;
s16, disassembling the second glass carrier plate, and manufacturing a solder mask layer and salient points;
and S17, disassembling the first glass carrier plate, and cutting into single chips to complete packaging.
Specifically, first, a silicon substrate 101 is provided, a heat dissipation channel 102 is etched on the front surface of the silicon substrate 101, as shown in fig. 2, and a stop layer 103 is deposited as shown in fig. 3. Wherein the thickness of the stop layer 103 is not less than 0.1 μm; the material of the stop layer 103 may be one or more of inorganic materials, such as SiO2, siC, siN, etc.; and may be one or more of metallic materials such as Al, cu, ni, sn and Au. The number of the heat dissipation channels 102 is greater than or equal to 1, and the width, the length and the depth of the heat dissipation channels are all more than 1 μm.
A first glass carrier plate is then bonded on the cut-off layer 103, as shown in fig. 4, comprising a bonding glass 201 and a temporary bonding laser reaction layer 202 formed on the bonding glass 201. As shown in fig. 5, the first glass carrier plate is bonded on the cut-off layer 103 by a temporary bonding adhesive 203, and the temporary bonding adhesive 203 is filled into the heat dissipation channel 102. Preferably, the thickness of the bonding glass 201 is 100 μm or more, the temporary bonding glue is 1 μm or more, and the temporary bonding laser reaction layer 202 is 0.1 μm or more.
Then, the back surface of the silicon substrate 101 is thinned to a target thickness by grinding or etching process, and a groove 104 is etched by dry etching, as shown in fig. 6, the depth h1 of the groove 104 embedded into the heat dissipation channel 102 is not less than 1 μm, the size of the groove 104 is determined according to the size of the chip to be embedded, the depth is at least 10 μm, and the number of the grooves 104 is 1 or more.
Referring to fig. 7, the chip 301 is embedded in the groove 104 by the thermally conductive adhesive 303, the bonding pad 302 faces outward, the thermally conductive adhesive 303 is made of a polymer material, and the height error between the height of the chip 301 and the height of the plane of the silicon substrate 101 after the chip 301 is embedded is not more than 5 μm. One or more of the chips 301 are embedded in each recess 104. Because the bottom of the groove 104 is embedded into the heat dissipation channel 102, the heat dissipation area is increased, and the heat dissipation capability is greatly improved.
Filling the gap between the chip 301 and the silicon substrate 101 with a dry film material 106 by using a vacuum film pressing technology, and simultaneously making the surface flat; and then the opening at the bonding pad is opened by using the photoetching technology, and the width and the depth of the opening are more than 1 mu m, as shown in figure 8. Preferably, the dry film material 106 is shown to be a polymeric material including resins and polyimides. The first layer wiring 107 connection pad 302 is then formed as shown in fig. 9.
As shown in fig. 10, a passivation layer 108, n-layer wiring 109 and micro bumps 110 are sequentially fabricated on a second glass carrier; and then bonded to the first layer wiring 107, and the passivation layer 111 is filled in the bonding gap, as shown in fig. 11. The second glass carrier plate is the same as the first glass carrier plate and comprises bonding glass and a temporary bonding laser reaction layer formed on the bonding glass; wherein the thickness of the bonding glass is not less than 100 μm; the thickness of the temporary bonding adhesive is not smaller than 1 mu m, and the thickness of the temporary bonding laser reaction layer is not smaller than 0.1 mu m.
The second glass carrier is detached by laser bonding and a final layer of wiring 114 is formed as shown in fig. 12.
A solder resist layer 112 and bumps 113 are formed on the surface as shown in fig. 13. Finally, the first glass carrier plate is disassembled by a laser bonding-breaking mode, the temporary bonding glue 203 is cleaned, and the temporary bonding glue is cut into single chips, so that the package shown in fig. 14 is completed.
Example two
The second embodiment provides a silicon-based fan-out wafer level package structure, which is manufactured by the method of the first embodiment, and the structure of the silicon-based fan-out wafer level package structure is shown in fig. 14. The silicon-based fan-out type wafer level packaging structure comprises a silicon substrate 101, wherein a heat dissipation channel 102 is etched on a first surface of the silicon substrate 101, the width, the length and the depth of the heat dissipation channel 102 are not less than 1 mu m, and the number of the heat dissipation channels 102 is not less than 1. A cut-off layer 103 is deposited on the heat dissipation channel 102. Preferably, the material of the stop layer 103 is one or more of inorganic materials, or one or more of metal materials, and the thickness of the stop layer is not less than 0.1 μm; wherein the inorganic material comprises SiO2, siC and SiN; the metal material includes Al, cu, ni, sn and Au.
The second surface of the silicon substrate 101 is etched with one or more grooves 104, and the depth of the grooves is not less than 10 μm; the depth of the groove 104 embedded into the heat dissipation channel 102 is not less than 1 μm. Each recess 104 has a chip or chips embedded therein. Specifically, the chip 301 is embedded into the groove 104 by the heat-conducting adhesive 303, and after the chip 301 is embedded, the height error between the height formed by the chip 301 and the plane of the silicon substrate 101 is not more than 5 μm. Further, the gap between the chip 301 and the silicon substrate 101 is filled with a dry film material 106; further, the dry film material 106 is a polymer material including resins and polyimides. The bonding pad 302 of the chip 301 is connected with the n-layer wiring 109 through the first-layer wiring 107 and the micro bump 110; passivation layer 111 is filled among first layer wiring 107, micro bump 110 and n layer wiring 109.
The n-layer wiring 109 is connected with a last-layer wiring 114, a solder mask layer 112 and a bump 113 are manufactured on the last-layer wiring 114, and the solder mask layer 112 completely wraps the last-layer wiring 114.
The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.

Claims (8)

1. A silicon-based fan-out wafer level packaging method, comprising:
providing a silicon substrate, etching a heat dissipation channel on the front surface of the silicon substrate, and depositing a stop layer on the front surface of the silicon substrate and the surface of the heat dissipation channel;
bonding a first glass carrier plate on the cut-off layer;
etching a groove on the back surface of the silicon substrate, embedding a chip and filling the chip with a dry film material;
forming a first layer of wiring by opening a bonding pad of the chip by photolithography;
sequentially manufacturing a passivation layer, n layers of wiring and micro-salient points on a second glass carrier plate, and bonding the passivation layer, the n layers of wiring and the micro-salient points with the first layer of wiring;
disassembling the second glass carrier plate and manufacturing a solder mask layer and salient points;
disassembling the first glass carrier plate, cutting into single chips, and finishing packaging;
etching a groove on the back surface of the silicon substrate, embedding a chip and filling the chip with a dry film material, wherein the method comprises the following steps:
thinning the back surface of the silicon substrate to a target thickness through a grinding or etching process, and etching a groove;
embedding a chip into the groove through heat-conducting adhesive, wherein a bonding pad of the chip faces outwards, and the heat-conducting adhesive is made of polymer materials;
filling the gap between the chip and the silicon substrate with a dry film material by using a vacuum film pressing technology, and making the surface smooth; wherein,
the depth of the groove embedded into the heat dissipation channel is not less than 1 mu m;
and after the chip is embedded, the height error between the height formed by the chip and the height of the silicon-based plane is not more than 5 mu m.
2. The silicon-based fan-out wafer level package method of claim 1, wherein the number of grooves is greater than or equal to 1 and the depth is not less than 10 μm; one chip or a plurality of chips are embedded in each groove.
3. The method of silicon-based fan-out wafer level packaging of claim 1, wherein the dry film material is a polymer material including resins and polyimides.
4. The method of silicon-based fan-out wafer level packaging of claim 1, wherein disassembling the second glass carrier and fabricating solder resist layers and bumps comprises:
the second glass carrier plate is disassembled in a laser bonding-breaking mode, and a final layer of wiring is manufactured;
and forming a solder mask layer and bumps on the surface.
5. The silicon-based fan-out wafer level packaging method of claim 1, wherein the first glass carrier is bonded to the cutoff layer by a temporary bonding glue, the first glass carrier and the second glass carrier each comprising a bonding glass and a temporary bonding laser reaction layer formed on the bonding glass; wherein,
the thickness of the bonding glass is not less than 100 mu m; the thickness of the temporary bonding adhesive is not smaller than 1 mu m, and the thickness of the temporary bonding laser reaction layer is not smaller than 0.1 mu m.
6. The silicon-based fan-out wafer level package method of claim 1, wherein the heat dissipation channels have a width, a length and a depth of not less than 1 μm, and the number of heat dissipation channels is not less than 1.
7. The method of claim 1, wherein the material of the stop layer is one or more of inorganic materials or one or more of metal materials, and the thickness of the stop layer is not less than 0.1 μm,
the inorganic material comprises SiO2, siC and SiN;
the metal material includes Al, cu, ni, sn and Au.
8. A silicon-based fan-out wafer level package structure, which is characterized by being manufactured by the silicon-based fan-out wafer level package method according to any one of claims 1 to 7.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110911291A (en) * 2019-12-17 2020-03-24 中国电子科技集团公司第五十八研究所 Resin type wafer level fan-out integrated packaging method and structure
CN111725154B (en) * 2020-06-29 2022-06-10 上海先方半导体有限公司 Packaging structure of embedded device and manufacturing method
CN112530813A (en) * 2020-11-30 2021-03-19 复旦大学 Temporary bonding method
CN112786448B (en) * 2021-03-15 2022-05-31 绍兴同芯成集成电路有限公司 Processing technology of IGBT wafer
CN113035756A (en) * 2021-03-24 2021-06-25 绍兴同芯成集成电路有限公司 Method for radiating substrate in ultrathin wafer processing by using glass carrier plate
CN115799184B (en) * 2023-02-13 2023-04-28 江西萨瑞半导体技术有限公司 Semiconductor packaging method

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101350338A (en) * 2007-07-17 2009-01-21 南亚电路板股份有限公司 Embedded type chip substrate structure
CN105023900A (en) * 2015-08-11 2015-11-04 华天科技（昆山）电子有限公司 Embedded silicon substrate fan-out type packaging structure and manufacturing method thereof
CN204885147U (en) * 2015-08-11 2015-12-16 华天科技（昆山）电子有限公司 Bury silicon substrate fan -out type packaging structure
CN107452689A (en) * 2017-09-14 2017-12-08 厦门大学 The embedded fan-out-type silicon pinboard and preparation method of three-dimensional systematic package application
CN107946254A (en) * 2017-12-18 2018-04-20 华天科技（昆山）电子有限公司 The silicon substrate fan-out package and wafer-level packaging method of integrated heat dissipation structure
CN210224007U (en) * 2019-07-31 2020-03-31 中国电子科技集团公司第五十八研究所 Silicon-based fan-out type wafer level packaging structure

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7208344B2 (en) * 2004-03-31 2007-04-24 Aptos Corporation Wafer level mounting frame for ball grid array packaging, and method of making and using the same

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101350338A (en) * 2007-07-17 2009-01-21 南亚电路板股份有限公司 Embedded type chip substrate structure
CN105023900A (en) * 2015-08-11 2015-11-04 华天科技（昆山）电子有限公司 Embedded silicon substrate fan-out type packaging structure and manufacturing method thereof
CN204885147U (en) * 2015-08-11 2015-12-16 华天科技（昆山）电子有限公司 Bury silicon substrate fan -out type packaging structure
WO2017024892A1 (en) * 2015-08-11 2017-02-16 华天科技（昆山）电子有限公司 Embedded silicon substrate fan-out type packaging structure and manufacturing method therefor
CN107452689A (en) * 2017-09-14 2017-12-08 厦门大学 The embedded fan-out-type silicon pinboard and preparation method of three-dimensional systematic package application
CN107946254A (en) * 2017-12-18 2018-04-20 华天科技（昆山）电子有限公司 The silicon substrate fan-out package and wafer-level packaging method of integrated heat dissipation structure
CN210224007U (en) * 2019-07-31 2020-03-31 中国电子科技集团公司第五十八研究所 Silicon-based fan-out type wafer level packaging structure

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
《硅基密封气密性及结构强度研究》;吉勇;《电子与封装》;20140831(8);第15-17页 *

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