CN201886122U - PXI (PCI extension for instrumentation) bus-based digital testing module - Google Patents
PXI (PCI extension for instrumentation) bus-based digital testing module Download PDFInfo
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Abstract
The utility model relates to a PXI (PCI extension for instrumentation) bus-based digital testing module. An FPGA (Field Programmable Gate Array) functional circuit part consists of a bus interface control unit, a central coding control unit, an address generation unit, a clock selection unit, a ZBTRAM control unit, a multi-module synchronous control unit and a trigger control unit; data is transmitted to the FPGA functional circuit by a PXI interface circuit through a PXI bus and then is stored into a data output SRAM (Static Random Access Memory) and a data input and output control SRAM; a control command defined by a user is transmitted to the digital testing module by the PXI bus; finally, a data input SRAM, the input and output control SRAM and the data output SRAM cooperatively work in the same clock rhythm, data is sent to a designated digital circuit by an output driver and a signal connector, and simultaneously the collected response data is stored in the data input SRAM by an input driver; and after testing completion, the data in the data input SRAM is uploaded on an upper computer.
Description
Technical field
The utility model relates to a kind of test module, relates in particular to a kind of testing digital module based on the PXI bus.
Background technology
Along with the development of computing machine and ultra-large system, the test of integrated circuit is also more and more difficult.Traditional method of testing is difficult to effective work, and the data field measuring technology has appearred in field tests.Traditional time domain, frequency domain test mainly with mimic channel and system as research and application, data field is tested then at digital circuit and computer logic.In fact, the data field test is carried out fault diagnosis, location, analysis and diagnosis to digital circuit and digital display circuit exactly.The data field test is adopted digital signal generator that excitation is provided usually and is used logic analyser to gather response data, that this method of testing exists is bulky, be not easy extended channel, cost an arm and a leg, the difficult problem of setting up complicated logical relation between excitation and response, so need function powerful high digital testing apparatus more in the modern Auto-Test System.
The utility model content
Technical matters to be solved:
At above problem the utility model provide that a kind of volume is little, low price, expansion easily, the flexible testing digital module of control based on the PXI bus.
Technical scheme:
A kind of testing digital module based on the PXI bus comprises PXI interface circuit/EEPROM, FPGA functional circuit part, DDS module, data input SRAM, input and output control SRAM, data output SRAM, output driver, enter drive, the signal connector of realizing with PXI bus reliable communicating;
The PXI interface circuit utilizes PCI9030 chip structure PXI interface, is responsible for the data on the PXI bus and orders the FPGA functional circuit that is sent to module, and be sent to the PXI bus the data in the module with to the request of processor; The address bus of PXI bus, data bus, control bus are reduced to simple local control logic output local address bus, data bus, control bus and FPGA functional circuit and carry out communication through after the PCI9030;
EEPROM is used to store the initialization information of PXI interface circuit, and is the PXI interface circuit initialization information of packing into, the configuration register of initialization PXI interface circuit after system reset;
The PXI backboard triggers bus and the star-like triggering line of PXI is sent to the FPGA functional circuit;
The FPGA functional circuit partly comprises bus interface control module, central encoded control unit, address-generation unit, clock selecting unit, ZBT RAM control module, multimode synchronous control unit, trigger control unit;
The DDS module receives data and the reference clock that the FPGA functional circuit provides, for system works provides adjustable output clock;
Data input SRAM, input and output control SRAM, data output SRAM finish the storage and the transmitting-receiving of input data, output data, position control data; The clock control line of three SRAM, data line, address wire all are to be produced by the ZBT RAM control module in the FPGA functional circuit part;
Output driver and enter drive are used to guarantee to encourage output to have bigger drive current and the high speed between the exciter response to switch;
Signal connector is used for the input and output of signal;
Control Software is moved on main control computer, and test data and position control data are edited on computers or generated by the waveform Core Generator; Data send the FPGA functional circuit by the PXI bus to through the PXI interface circuit, deposit in then among data output SRAM and the data input and output control SRAM; The control command of user's established data transmission rate, data length, data content and output reference position, triggering mode sends to testing digital module by the PXI bus; Final data input SRAM, input and output control SRAM, data output SRAM collaborative work under same timeticks, data are dealt in the digital circuit of appointment through output driver and signal connector, meanwhile gather response data and are stored among the data input SRAM through enter drive; Test finish the back the data upload among the data inputs SRAM to host computer.
Described bus interface control module receives address wire, data line, the control line of PXI bus and realizes user interface logic, comprises that address/data signal, I/O read-write and latent period produce logic and bus control logic;
Central authorities encoded control unit is used for receiving chip selection signal, write signal, read signal, address signal and the data-signal that is sent by the bus interface control module, produce the read-write control signal of each function register according to these signals, and then control address generation unit, clock selecting unit, ZBT RAM control module;
Address-generation unit receives the read-write control signal of central encoded control unit, for ZBT RAM control module provides the address.Number, zero clearing, turn function are put in the address-generation unit support, thereby testing digital module is possessed from arbitrary initial address inputoutput data, periodic duty inputoutput data, the function of designated length inputoutput data;
The clock selecting unit is used to guarantee that testing digital module is with motor-driven mode output data;
ZBT RAM control module inside comprises interface signal transport module, streamline time-delay control module, address date output module, data memory module; In these four functional modules. what play control action is streamline time-delay control module and data memory module; Streamline time-delay control module will import data delay 2 clock period, simultaneously also with read-write control signal time-delay two clock period with delay time after the input data sync; Read-write control signal after the time-delay will offer the two-way control that data memory module carries out reading and writing data; The address signal that ZBT RAM control module receiver address generation unit provides, the clock signal that the clock selecting unit provides, trigger pip that trigger control unit provides form the control signal that meets the SRAM work schedule, the work of control sram chip through the processing of interface signal transport module, streamline time-delay control module, address date output module, data memory module;
The multimode synchronous control unit is used for when a plurality of PXI bus numeral set of test modules become a digital test subsystems, in inner hyperchannel expansion, synchronous working, the real-time function of gathering of realizing of FPGA;
Trigger control unit is trigger pip to be passed to the trigger action of ZBT RAM control module and then control SRAM.
Described testing digital module based on the PXI bus is provided with and imports the output synchronous clock that external clock, PXI base plate synchronous clock, the controlled clock of DDS and the output data of data sync synchronous can be used for circuit-under-test.
Described PXI base plate synchronous clock is the clock of a 10M, a reference clock that provides when being the multimode synchronous working.
The controlled clock of described DDS is the input clock that a stepping of DDS chip output reaches 0.002Hz.
Described triggering line comprises that the PXI backboard triggers bus and the star-like triggering line of PXI.
Described signal connector is bilayer 68 pins, can realize the signal connector of 48 road signal input and output.
Beneficial effect:
The utility model adopt the PXI bus as with the bus of computing machine and other integrated circuit board communications, greatly improved the reliability of testing digital module, can the multimode collaborative work, realize multichannel data transmit-receive.Adopt Direct Digital Frequency Synthesizers (DDS) to produce the changeable frequency clock, make module carry out test assignment with flexible and changeable data rate, it is 0.04Hz that clock changes resolution.Utilize the function of DDS controllable phase to realize adjusting in the one-period of sampling clock simultaneously.Utilize the cooperation of PXI backboard reference clock and DDS to realize the synchronous of multimode different clock frequencies.Realized data transmission rate up to 50M.Realize the I/O of 48 passage digital quantity signals, each I/O passage is separate and each clock period is controlled; Every passage all has and is provided with high capacity (the 1M vector degree of depth) storer separately.Need realize flexile triggering control at different tests.The utility model is realized interface respectively by adopting fpga chip, control module, and circuit complexity reduces, and whole test module volume greatly reduces, and is convenient to the system integration, and adopts the PXI bus structure, can be integrated in the Computer Automatic Test System easily.
Description of drawings
Fig. 1 is a theory structure block diagram of the present utility model;
Fig. 2 is the structural drawing of the FPGA functional unit in the utility model.
Embodiment
Below in conjunction with the drawings and specific embodiments the utility model is done explanation in further detail.
As shown in Figure 1, this is based on the testing digital module of PXI bus: comprise that the PXI interface circuit, EEPROM, FPGA functional circuit part, DDS module, data input SRAM, input and output control SRAM, the data that realize with PXI bus reliable communicating export SRAM, output driver, enter drive, signal connector;
The PXI interface circuit of this digital test module utilizes PCI9030 chip structure PXI interface, be responsible for the data on the PXI bus and order the FPGA functional circuit that is sent to module, and be sent to the PXI bus the data in the testing digital module with to the request of processor.The address bus of PXI bus, data bus, control bus are reduced to simple local control logic output local address bus, data bus, control bus and FPGA functional circuit and carry out communication through after the PCI9030;
EEPROM is used to store the initialization information of PXI interface circuit, and is pack into the configuration register of initialization information initialization interface circuit of PXI interface circuit after system reset;
The PXI backboard triggers bus and the star-like triggering line of PXI is sent to the FPGA functional circuit, handles the synchronous triggering work that is used for multimode through internal logic circuit.
The FPGA functional circuit partly comprises bus interface control module, central encoded control unit, address-generation unit, clock selecting unit, ZBT RAM control module, multimode synchronous control unit, trigger control unit, as shown in Figure 2;
The DDS module receives data and the reference clock that the FPGA functional circuit partly provides, for system works provides accurate adjustable output clock; Comprise data input SRAM, input and output control SRAM, data output SRAM, three SRAM finish the storage and the transmitting-receiving of input data, output data, position control data.The clock control line of three SRAM, data line, address wire all are to be produced by the ZBT RAM control module in the FPGA functional circuit;
Output driver and enter drive have guaranteed that excitation output has bigger drive current and the high speed between the exciter response to switch;
Signal connector is a bilayer 68 pin high density signal connectors, has realized the input and output of 48 road signals.
The course of work is as follows: Control Software is moved on main control computer, and test data and position control data are edited on computers or generated by the waveform Core Generator; Data send the FPGA functional circuit by the PXI bus to through the PXI interface circuit, deposit in then among the data output SRAM and data input and output control SRAM of module; The user as required, specified data transmission rate, data length, data content and output reference position, triggering mode control command send to testing digital module by the PXI bus; Last three SRAM collaborative works under same timeticks of testing digital module, data stream is dealt in the digital circuit of appointment through output driver and signal connector, meanwhile gathers response data and is stored among the data input SRAM through enter drive.Test finish the back the data upload among the data inputs SRAM to host computer, handle and analyze.
As shown in Figure 2, the design of PXI bus interface control module strictly observes the PXI bus specification.Interface control unit receives address wire, data line, the control line of PXI bus and realizes user interface logic, comprises that address/data signal, I/O read-write and latent period produce logic and bus control logic.
Central authorities encoded control unit is used for receiving chip selection signal, write signal, read signal, address signal and the data-signal that is sent by the PXI interface control unit, produce the read-write control signal of each function register according to these signals, and then control address generation unit, clock selecting unit, ZBT RAM control module carry out work with certain working method.
Address-generation unit receives the read-write control signal of central encoded control unit, for ZBT RAM control module provides the address.Number, zero clearing, turn function are put in the address-generation unit support, thereby testing digital module is possessed from arbitrary initial address inputoutput data, periodic duty inputoutput data, the function of designated length inputoutput data.
In order to guarantee that module can design the clock selecting unit with the Flexible Ways output data.This digital test module is supported the clock input preference pattern of external clock, PXI base plate synchronous clock, the controlled clock of DDS and is exported the output mode of a module work synchronous clock.External clock be one and the input data sync clock, can make module accurately gather the input data.PXI base plate synchronous clock is the clock of a 10M, a reference clock that provides when being the multimode synchronous working; The controlled clock of DDS is the high precision input clock that a stepping of DDS chip output reaches 0.002Hz.The output synchronous clock be with output data synchronous can be for a clock of circuit-under-test use.
Its inside of ZBT RAM control module has comprised following 4 functional modules: interface signal transport module, streamline time-delay control module, address date output module, data memory module.In these 4 functional modules. what play control action is streamline time-delay control module and data memory module.Streamline time-delay control module will import data delay 2 clock period, simultaneously also with read-write control signal time-delay two clock period with delay time after the input data sync.Read-write control signal after the time-delay will offer the two-way control that data memory module carries out reading and writing data.The address signal that ZBT RAM control module receiver address generation unit provides, the clock signal that the clock selecting unit provides, trigger pip that trigger control unit provides form the control signal control sram chip that meets the SRAM work schedule through the processing of inner 4 modules and carry out work with certain pattern.
The multimode synchronous control unit is in inner hyperchannel expansion, synchronous working, the real-time function of gathering of realizing of FPGA.Because digital test may run into the many situations of port number, the support of PXI testing digital module comes the ability of extended channel quantity with modular combination, and like this, if user's number of channels deficiency in actual applications, the module of expanding respective number on demand gets final product.A plurality of PXI bus numeral set of test modules become a digital test subsystems.Each PXI bus testing digital module must synchronous working, and PXI cabinet backboard provides the reference clock of a 10M and each testing digital module work clock is that DDS produce as reference clock by Direct Digital Frequency Synthesizers by the backboard reference clock.Because each module adopts the DDS chip of oneself, the stationary problem of multi-disc DDS chip output multipath clock signal has so just appearred.Synchronous in order to realize multi-disc DDS chip signal output waveform phase, must guarantee that all DDS chips work under same system clock beat, when the DDS chip is carried out control programming, the data that write the DDS chip at first are buffered in the inner I/O buffer register, can not have influence on the duty of DDS chip; Have only when the rising edge of the refresh clock signal of DDS chip arrives, trigger the I/O buffer register data are sent to the duty that the internal control register just changes the DDS chip later on.The refresh clock signal can provide outside refresh clock by the user.Need to select a module as primary module under this test case, other modules are from module.The PC control primary module produces a refresh clock signal, and the refresh clock signal triggers line through PXI cabinet backboard and passes to each from module, thereby realizes the clock synchronization of each module.After clock synchronization was finished, primary module triggered bus by the PXI backboard and sends an accurate trigger pip, thereby had realized the synchronous working of multimode.
Trigger control unit is trigger pip to be passed to the trigger action of ZBT RAM control module and then control SRAM.This digital test module is supported multiple triggering mode, is respectively external input signal triggering, PXI backboard triggering bus triggering and the star-like triggering line of PXI and triggers.Wherein external input signal triggers and can be divided into external input signal level triggers, the triggering of external input signal rising edge, the triggering of external input signal negative edge, input signal triggering sequence trigger again.Trigger ability flexibly accurately, the moment startup module of wanting of can in officely what is the need for is carried out work, send the test and excitation sequence and gather the response vector sequence that system under test (SUT) returns to system under test (SUT), this has important meaning to the current logic state of catching and analyze system under test (SUT).
Claims (6)
1. the testing digital module based on the PXI bus is characterized in that: comprise PXI interface circuit, EEPROM, FPGA functional circuit part, DDS module, data input SRAM, input and output control SRAM, data output SRAM, output driver, enter drive, the signal connector realized with PXI bus reliable communicating;
The PXI interface circuit utilizes PCI9030 chip structure PXI interface, is responsible for the data on the PXI bus and orders the FPGA functional circuit that is sent to module, and be sent to the PXI bus the data in the module with to the request of processor; The address bus of PXI bus, data bus, control bus are reduced to simple local control logic output local address bus, data bus, control bus and FPGA functional circuit and carry out communication through after the PCI9030;
EEPROM is used to store the initialization information of PXI interface circuit, and is the PXI interface circuit initialization information of packing into, the configuration register of initialization PXI interface circuit after system reset;
The PXI backboard triggers bus and the star-like triggering line of PXI is sent to the FPGA functional circuit;
The FPGA functional circuit partly comprises bus interface control module, central encoded control unit, address-generation unit, clock selecting unit, ZBT RAM control module, multimode synchronous control unit, trigger control unit;
The DDS module receives data and the reference clock that the FPGA functional circuit provides, for system works provides adjustable output clock;
Data input SRAM, input and output control SRAM, data output SRAM finish the storage and the transmitting-receiving of input data, output data, position control data; The clock control line of three SRAM, data line, address wire all are to be produced by the ZBT RAM control module in the FPGA functional circuit part;
Output driver and enter drive are used to guarantee to encourage output to have bigger drive current and the high speed between the exciter response to switch;
Signal connector is used for the input and output of signal;
Control Software is moved on main control computer, and test data and position control data are edited on computers or generated by the waveform Core Generator; Data send the FPGA functional circuit by the PXI bus to through the PXI interface circuit, deposit in then among data output SRAM and the data input and output control SRAM; The control command of user's established data transmission rate, data length, data content and output reference position, triggering mode sends to testing digital module by the PXI bus; Final data input SRAM, input and output control SRAM, data output SRAM collaborative work under same timeticks, data are dealt in the digital circuit of appointment through output driver and signal connector, meanwhile gather response data and are stored among the data input SRAM through enter drive; Test finish the back the data upload among the data inputs SRAM to host computer.
2. a kind of testing digital module according to claim 1 based on the PXI bus, it is characterized in that: described bus interface control module receives address wire, data line, the control line of PXI bus and realizes user interface logic, comprises that address/data signal, I/O read-write and latent period produce logic and bus control logic;
Central authorities encoded control unit is used for receiving chip selection signal, write signal, read signal, address signal and the data-signal that is sent by the bus interface control module, produce the read-write control signal of each function register according to these signals, and then control address generation unit, clock selecting unit, ZBT RAM control module;
Address-generation unit receives the read-write control signal of central encoded control unit, for ZBT RAM control module provides the address,
Number, zero clearing, turn function are put in the address-generation unit support, thereby testing digital module is possessed from arbitrary initial address inputoutput data, periodic duty inputoutput data, the function of designated length inputoutput data;
The clock selecting unit is used to guarantee that testing digital module is with motor-driven mode output data;
ZBT RAM control module inside comprises interface signal transport module, streamline time-delay control module, address date output module, data memory module; In these four functional modules. what play control action is streamline time-delay control module and data memory module; Streamline time-delay control module will import data delay 2 clock period, simultaneously also with read-write control signal time-delay two clock period with delay time after the input data sync; Read-write control signal after the time-delay will offer the two-way control that data memory module carries out reading and writing data; The address signal that ZBT RAM control module receiver address generation unit provides, the clock signal that the clock selecting unit provides, trigger pip that trigger control unit provides form the control signal that meets the SRAM work schedule, the work of control sram chip through the processing of interface signal transport module, streamline time-delay control module, address date output module, data memory module;
The multimode synchronous control unit is used for when a plurality of PXI bus numeral set of test modules become a digital test subsystems, in inner hyperchannel expansion, synchronous working, the real-time function of gathering of realizing of FPGA;
Trigger control unit is trigger pip to be passed to the trigger action of ZBT RAM control module and then control SRAM.
3. a kind of testing digital module based on the PXI bus according to claim 1 is characterized in that: be provided with and import the output synchronous clock that external clock, PXI base plate synchronous clock, the controlled clock of DDS and the output data of data sync synchronous can be used for circuit-under-test.
4. a kind of testing digital module based on the PXI bus according to claim 3 is characterized in that: described PXI base plate synchronous clock is the clock of a 10M, a reference clock that provides when being the multimode synchronous working.
5. a kind of testing digital module based on the PXI bus according to claim 3 is characterized in that: the controlled clock of described DDS is the input clock that a stepping of DDS chip output reaches 0.002Hz.
6. a kind of testing digital module based on the PXI bus according to claim 1 is characterized in that: described signal connector is bilayer 68 pins, can realize the signal connector of 48 road signal input and output.
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| CN111505593A (en) * | 2020-04-30 | 2020-08-07 | 北京无线电测量研究所 | Frequency synthesis comprehensive test system and test method |
| CN111505593B (en) * | 2020-04-30 | 2022-03-29 | 北京无线电测量研究所 | Frequency synthesis comprehensive test system and test method |
| CN112067979A (en) * | 2020-09-15 | 2020-12-11 | 中电科仪器仪表有限公司 | Integrated circuit test system based on PXIe bus |
| CN112255533A (en) * | 2020-09-25 | 2021-01-22 | 杭州加速科技有限公司 | Device and method for improving synchronous trigger real-time performance of semiconductor tester |
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