CN110188415B - Method and system for verifying universal cyclic redundancy check circuit IP (Internet protocol) card - Google Patents
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
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- G—PHYSICS
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- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
- G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
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- G06F2115/00—Details relating to the type of the circuit
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The invention discloses a method and a system for realizing an IP core of a universal cyclic redundancy check circuit, wherein the method comprises the following steps of; address counting and data bit counting are carried out according to the length of externally configured data to be checked, and input data reading enabling signals, address and input data bit start enabling checking process control signals are generated; and determining a cyclic redundancy check circuit form according to the configuration information, and generating output check data and output interruption according to the control signal shift register. The invention has the advantages that: the implementation is simple, the cyclic redundancy check is carried out on the data through the on-line configuration parameters of the processor, the method is simple and flexible, the required check code can be quickly generated on the basis of not changing hardware, the method can adapt to two common cyclic redundancy check circuit forms, repeated design is avoided, and the design cost is saved; meanwhile, compared with software cyclic redundancy check, the method and the device remarkably improve check efficiency.
Description
Technical Field
The invention belongs to the field of cyclic redundancy check circuits, and particularly relates to a method and a system for realizing an IP core of a universal cyclic redundancy check circuit.
Background
In the field of data storage and data communication, in order to ensure the correctness of data, an error detection means is required, wherein a cyclic redundancy code (CRC code) is the most commonly used error check code, and is characterized in that the lengths of an information field and a check field can be arbitrarily selected. The CRC code is divided into the following criteria according to the application environment: CRC_12 code, CRC_16 code, CRC-32 code, etc. In addition, CRC standards of other code lengths can be formulated in the special field.
In practical applications, the data storage and communication system has CRC codes of different standards, different forms and different generator polynomials. The designer would waste a lot of time and effort if designing and verifying each standard. Particularly in ASIC, SOC chip designs or FPGA related designs, the circuit architecture is fixed and the use limitations are great if the design is directed to specific CRC criteria and generator polynomials.
Disclosure of Invention
The invention aims to provide a design realization method of a general cyclic redundancy check circuit IP core, which solves the problem that cyclic redundancy check circuits need to be repeatedly designed under different check requirements in the fields of data storage and communication.
In view of this, the technical scheme provided by the invention is as follows: a method for verifying a universal cyclic redundancy check (crc) circuit IP address, comprising:
address counting and data bit counting are carried out according to the length of externally configured data to be checked, and input data reading enabling signals, address and input data bit start enabling checking process control signals are generated;
and determining a cyclic redundancy check circuit form according to the configuration information, and generating output check data and output interruption according to the control signal shift register.
Further, the method further comprises the following steps: and carrying out real-time modification on the cyclic redundancy check circuit path on line according to application requirements.
Further, the information of the configuration includes: and configuring corresponding check code length, generating polynomial and shifting register initial value according to the selected cyclic redundancy check circuit form.
Further, the method further comprises the following steps: the length of the input data, the order in which the input data is read from the memory, and the order in which the check codes are output are configured.
Further, determining a cyclic redundancy check circuit path from the configured information comprises: and starting to perform check code calculation on the input data according to the configured information.
Further, the method further comprises the following steps: and outputting check codes according to the configured output sequence when the calculation is finished, and sending out a calculation completion interrupt.
Further, the verification requirements of the system include: different forms of cyclic redundancy check requirements are made on data from different sources.
Another object of the present invention is to provide a general cyclic redundancy check circuit IP verification system, comprising:
the counting module is used for performing address counting and data bit counting according to the length of externally configured data to be checked, and generating input data reading enabling signals, address and input data bit start enabling checking process control signals;
and the shift register module is used for determining the form of the cyclic redundancy check circuit according to the configured information, and generating output check data and output interrupt according to the shift register of the control signal.
Further, the cyclic redundancy check circuit is in the form of: the highest bit of the shift register is firstly exclusive-ored with the input data, and then is fed back to other bits participating in exclusive-ored in the generator polynomial.
Further, the cyclic redundancy check circuit is in the form of: the highest bit of the shift register is directly fed back to other bits participating in exclusive or in the generator polynomial.
The invention realizes the following remarkable beneficial effects:
the realization is simple, including: address counting and data bit counting are carried out according to the length of externally configured data to be checked, and input data reading enabling signals, address and input data bit start enabling checking process control signals are generated; and determining a cyclic redundancy check circuit form according to the configuration information, and generating output check data and output interruption according to the control signal shift register. The characteristic of the cyclic redundancy check circuit is changed through the online configuration parameters of the processor, the cyclic redundancy check circuit is simple and flexible, the real-time change can be carried out online, the required cyclic redundancy check circuit can be quickly generated on the basis of not changing hardware, the repeated design is avoided, the design cost is saved, and the designed hardware module has reusability.
Drawings
FIG. 1 is a schematic diagram of a design method of a general Cyclic Redundancy Check (CRC) circuit IP core according to the present invention;
FIG. 2 is a schematic diagram of a first embodiment of a cyclic redundancy check circuit of the present invention;
FIG. 3 is a schematic diagram of a second embodiment of a cyclic redundancy check circuit according to the present invention;
FIG. 4 is a schematic diagram of a second embodiment of a first cyclic redundancy check circuit of the present invention;
fig. 5 is a schematic diagram of a second embodiment of a cyclic redundancy check circuit of the present invention.
Reference numerals indicate
1. Counting module 2 shift register module
3. Cyclic redundancy check circuit form one 4. Cyclic redundancy check circuit form two
Detailed Description
The advantages and features of the present invention will become more fully apparent from the following description and appended claims, taken in conjunction with the accompanying drawings and detailed description. It should be noted that the drawings are in a very simplified form and are adapted to non-precise proportions, merely for the purpose of facilitating and clearly aiding in the description of embodiments of the invention.
It should be noted that, in order to clearly illustrate the present invention, various embodiments of the present invention are specifically illustrated by the present embodiments to further illustrate different implementations of the present invention, where the various embodiments are listed and not exhaustive. Furthermore, for simplicity of explanation, what has been mentioned in the previous embodiment is often omitted in the latter embodiment, and therefore, what has not been mentioned in the latter embodiment can be referred to the previous embodiment accordingly.
While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and are herein described in detail. It should be understood that the invention is not to be limited to the particular embodiments disclosed, but on the contrary, the invention is to cover all modifications, equivalents, and alternatives falling within the spirit or scope of the invention as defined by the appended claims. The same component numbers may be used throughout the drawings to refer to the same or like parts.
Referring to fig. 1, a method for implementing an IP block of a universal cyclic redundancy check circuit according to the present invention includes: address counting and data bit counting are carried out according to the length of externally configured data to be checked, and input data reading enabling signals, address and input data bit start enabling checking process control signals are generated; and determining a cyclic redundancy check circuit form according to the configuration information, and generating output check data and output interruption according to the control signal shift register.
Preferably, the method further comprises: and carrying out real-time modification on the cyclic redundancy check circuit path on line according to application requirements.
Preferably, the information of the configuration includes: and configuring corresponding check code length, generating polynomial and shifting register initial value according to the selected cyclic redundancy check circuit form.
Preferably, the method further comprises: the length of the input data, the order in which the input data is read from the memory, and the order in which the check codes are output are configured.
Preferably, determining the cyclic redundancy check circuit path from the configured information comprises: and starting to perform check code calculation on the input data according to the configured information.
Preferably, the method further comprises: and outputting check codes according to the configured output sequence when the calculation is finished, and sending out a calculation completion interrupt.
Preferably, the verification requirement of the system includes: different forms of cyclic redundancy check requirements are made on data from different sources.
As a specific embodiment, the method for implementing the universal cyclic redundancy check circuit IP core of the present invention includes the following specific steps:
the first step: and constructing each sub-module of the IP core of the universal cyclic redundancy check circuit.
Each sub-module of the general cyclic redundancy check circuit IP core comprises a counting module and a shift register module.
The counting module has the functions of: generating verification process control signals such as input data reading enabling signals, addresses, input data bit start enabling signals and the like;
the shift register module has the functions of: and determining a cyclic redundancy check circuit path according to the configuration information, and generating output check data and output interruption according to the control signal shift register.
And a second step of: the configurable items of the general cyclic redundancy check circuit IP core are configured by a processor.
After the system is powered on and reset, the processor firstly configures the configurable item of the IP core of the general cyclic redundancy check circuit, and firstly selects a first cyclic redundancy check circuit form 3 or a second cyclic redundancy check circuit form 4 according to the check requirement of the system; then configuring corresponding check code length, generating polynomial and shifting register initial value according to the selected circuit form; meanwhile, the length of input data, the reading sequence of the input data from a memory, the output sequence of check codes and the like can be configured; after the processor has configured all the configurable items, the system can start to calculate the check code of the input data according to the configured parameters, output the check code according to the configured output sequence when the calculation is finished, and send out the calculation completion interrupt.
And a third step of: online real-time modification according to specific needs and applications
When the characteristics of the cyclic redundancy check circuit need to be changed in the running process of the system, the processor is required to reconfigure the general cyclic redundancy check circuit IP core, and the system can start to work according to the new configuration.
So far, the design of the general cyclic redundancy check circuit IP core is realized.
Referring to fig. 1 to 5, the universal cyclic redundancy check circuit IP verification system of the present invention includes: the counting module 1 is used for performing address counting and data bit counting according to the length of externally configured data to be checked, and generating input data reading enabling signals, address and input data bit start enabling verification process control signals; and the shift register module 2 is used for determining the form of a cyclic redundancy check circuit according to the configuration information and generating output check data and output interrupt according to the shift register of the control signal.
Preferably, the cyclic redundancy check circuit is in the form of: the highest bit of the shift register is firstly exclusive-ored with the input data, and then is fed back to other bits participating in exclusive-ored in the generator polynomial.
Preferably, the cyclic redundancy check circuit is in the form of: the highest bit of the shift register is directly fed back to other bits participating in exclusive or in the generator polynomial.
In one embodiment, the method for implementing the design of the universal cyclic redundancy check circuit IP core comprises the following specific steps:
the first step: each submodule for constructing universal Cyclic Redundancy Check (CRC) circuit IP core
As shown in fig. 1, each sub-module of the general cyclic redundancy check circuit IP core includes a counting module 1 and a shift register module 2.
The counting module 1 has the following functions: generating verification process control signals such as input data reading enabling signals, addresses, input data bit start enabling signals and the like according to the input data length of external configuration; for example, checking the input data with the length of 64 bits, wherein each address of the external memory stores 32bit data, and two data reading enabling addresses and corresponding addresses are generated in cascade through an internal counter of the IP core, so that two 32bit data are read from the external memory; and outputting the two 32-bit data according to the count value to form 64-bit serial data to be verified, and generating an input data bit start enabling signal when the first-bit serial data to be verified is output.
The shift register module 2 has the following functions: determining a cyclic redundancy check circuit path according to the configuration information, and generating output check data and output interruption according to the control signal shift register; for example, the external configuration selects a circuit form of a cyclic redundancy check circuit form one 3, and according to the start enabling signal generated by the counting module, 64bit serial data to be checked are shifted and registered one by one according to the circuit form of the cyclic redundancy check circuit form one 3, so as to generate output check data and output interrupt. The main difference between the first cyclic redundancy check circuit form 3 and the second cyclic redundancy check circuit form 4 is that: the highest bit of the shift register in the first 3 of the cyclic redundancy check circuit forms is firstly xored with input data and then fed back to other bit participating in the xored in the generator polynomial; and the highest bit of the cyclic redundancy check circuit type two 4 shift register is directly fed back to other bits participating in exclusive OR in the generator polynomial.
And a second step of: configuration of configurable items of a universal cyclic redundancy check (crc) circuit IP core by a processor
As shown in fig. 2 to 5, wherein a first embodiment of the cyclic redundancy check circuit form one of fig. 2 is shown to generate a polynomial G (X) =x 16 +X 12 +X 5 +1 is an example. Fig. 3 shows a first embodiment of a cyclic redundancy check circuit form two to generate a polynomial G (X) =x 16 +X 12 +X 5 +1 is an example. Fig. 4 shows a second embodiment of a form one cyclic redundancy check circuit to generate a polynomial G (X) =x 8 +X 7 +X 6 +X 4 +X 2 +1 is an example. Fig. 5 shows a second embodiment of the cyclic redundancy check circuit form two to generate a polynomial G (X) =x 8 +X 7 +X 6 +X 4 +X 2 +1 is an example.
After the system is powered on and reset, the processor firstly configures configurable items of the general cyclic redundancy check circuit IP core, and firstly selects a first cyclic redundancy check circuit form 3 or a second cyclic redundancy check circuit form 4 according to check requirements of the system, as shown in fig. 2 and 3, wherein a processor configuration check circuit form selection signal of 1'b1 represents selecting the first cyclic redundancy check circuit form 3, and a processor configuration check circuit form selection signal of 1' b0 represents selecting the second cyclic redundancy check circuit form 4; then other configuration items are configured according to the selected circuit form, such as the configuration check code length is 16bit, and the configuration generating polynomial is G (X) =X 16 +X 12 +X 5 +1, configuring an initial value of a shift register to be 16' hABCD, configuring the length of input data to be 64 bits, and configuring the reading sequence of the input data from a memory and the output sequence of check codes to be from high order to low order; after the processor has configured all the configurable items, the system will shift and register the serial data to be checked one by one according to the cyclic redundancy check circuit form corresponding to the configuration according to the cooperation of the counting module 1 and the shift register module 2 in the first step, and generate output check data and output interrupt.
And a third step of: online real-time modification according to specific needs and applications
During operation of the systemWhen the characteristics of the crc circuit need to be changed, the processor is required to reconfigure the IP core of the crc circuit, and the system starts to operate according to the new configuration. For example, when the system performs verification for the first time, the length of the configuration input data is 64 bits, and the configuration verification circuit is in the form of the first 3 cyclic redundancy verification circuit; and secondly, checking the other group of input data with the length of 128 bits according to the cyclic redundancy check circuit type II 4, and then configuring the length of the input data of the IP core to be 128 bits again, and configuring the check circuit type to be the cyclic redundancy check circuit type II 4. For another example, the system needs to modify the CRC code length to 8 bits for the third time, and correspondingly configures the generator polynomial to be G (X) =x 8 +X 7 +X 6 +X 4 +X 2 And +1, configuring the initial value of the shift register to be 8' h5A, and configuring the check circuit form to be the first cyclic redundancy check circuit form 3 or the second cyclic redundancy check circuit form 4 according to requirements, wherein the shift register can start working according to new configurations as shown in a fourth drawing and a fifth drawing.
Thus, the specific implementation of the general cyclic redundancy check circuit IP core is completed.
The invention realizes the following remarkable beneficial effects:
the realization is simple, including: address counting and data bit counting are carried out according to the length of externally configured data to be checked, and input data reading enabling signals, address and input data bit start enabling checking process control signals are generated; and determining a cyclic redundancy check circuit form according to the configuration information, and generating output check data and output interruption according to the control signal shift register. The characteristic of the cyclic redundancy check circuit is changed through the online configuration parameters of the processor, the cyclic redundancy check circuit is simple and flexible, the real-time change can be carried out online, the required cyclic redundancy check circuit can be quickly generated on the basis of not changing hardware, the repeated design is avoided, the design cost is saved, and the designed hardware module has reusability.
While the foregoing is directed to embodiments of the present invention, other and further details of the invention may be had by the present invention, it should be understood that the foregoing description is merely illustrative of the present invention and that various modifications, equivalents, improvements and changes may be made without departing from the spirit and principles of the invention.
Claims (2)
1. A method for verifying a universal cyclic redundancy check (crc) circuit IP address, comprising:
address counting and data bit counting are carried out according to the length of externally configured data to be checked, and input data reading enabling signals, address and input data bit start enabling checking process control signals are generated;
determining a cyclic redundancy check circuit form according to the configured information, and generating output check data and output interruption according to the control signal shift register;
after the system is powered on and reset, the processor firstly configures the configurable item of the IP core of the general cyclic redundancy check circuit, and firstly selects a first cyclic redundancy check circuit form 3 or a second cyclic redundancy check circuit form 4 according to the check requirement of the system; the verification requirements of the system include: performing different forms of cyclic redundancy check requirements on data from different sources; then configuring corresponding check code length, generating polynomial and shifting register initial value according to the selected circuit form; meanwhile, the length of the input data, the reading sequence of the input data from the memory and the output sequence of the check codes can be configured; after the processor has configured all the configurable items, determining the cyclic redundancy check circuit path according to the configured information includes: the system can start to calculate check codes of the input data according to the configured parameters; outputting check codes according to the configured output sequence when the calculation is finished, and sending out a calculation completion interrupt; the cyclic redundancy check circuit is in the form of: the highest bit of the shift register is firstly exclusive-ored with the input data, and then is fed back to other bit participating in exclusive-ored in the generator polynomial; the highest bit of the shift register is directly fed back to other bits participating in exclusive OR in the generator polynomial;
when the characteristics of the cyclic redundancy check circuit need to be changed in the running process of the system, the processor is required to reconfigure the general cyclic redundancy check circuit IP core, and the system can start to work according to the new configuration.
2. A universal cyclic redundancy check circuit IP verification system comprising:
the counting module is used for performing address counting and data bit counting according to the length of externally configured data to be checked, and generating input data reading enabling signals, address and input data bit start enabling checking process control signals;
the shift register module is used for determining the form of a cyclic redundancy check circuit according to the configured information and generating output check data and output interruption according to the shift register of the control signal;
after the system is powered on and reset, the processor firstly configures the configurable item of the IP core of the general cyclic redundancy check circuit, and firstly selects a first cyclic redundancy check circuit form 3 or a second cyclic redundancy check circuit form 4 according to the check requirement of the system; the verification requirements of the system include: performing different forms of cyclic redundancy check requirements on data from different sources; then configuring corresponding check code length, generating polynomial and shifting register initial value according to the selected circuit form; meanwhile, the length of the input data, the reading sequence of the input data from the memory and the output sequence of the check codes can be configured; after the processor has configured all the configurable items, determining the cyclic redundancy check circuit path according to the configured information includes: the system can start to calculate check codes of the input data according to the configured parameters; outputting check codes according to the configured output sequence when the calculation is finished, and sending out a calculation completion interrupt; the cyclic redundancy check circuit is in the form of: the highest bit of the shift register is firstly exclusive-ored with the input data, and then is fed back to other bit participating in exclusive-ored in the generator polynomial; the highest bit of the shift register is directly fed back to other bits participating in exclusive OR in the generator polynomial;
when the characteristics of the cyclic redundancy check circuit need to be changed in the running process of the system, the processor is required to reconfigure the general cyclic redundancy check circuit IP core, and the system can start to work according to the new configuration.
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| CN115549854B (en) * | 2021-06-30 | 2024-07-12 | 上海寒武纪信息科技有限公司 | Cyclic redundancy check method and device, storage medium and electronic equipment |
| CN116756082B (en) * | 2023-08-16 | 2023-10-27 | 沐曦集成电路(上海)有限公司 | Configurable function module file generation method and system |
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