CN113645023B - Chaotic signal steady-state circuit and memristor device - Google Patents
Chaotic signal steady-state circuit and memristor device Download PDFInfo
- Publication number
- CN113645023B CN113645023B CN202110923980.2A CN202110923980A CN113645023B CN 113645023 B CN113645023 B CN 113645023B CN 202110923980 A CN202110923980 A CN 202110923980A CN 113645023 B CN113645023 B CN 113645023B
- Authority
- CN
- China
- Prior art keywords
- circuit
- state
- steady
- resistor
- memristor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
- 230000000739 chaotic effect Effects 0.000 title claims abstract description 108
- 239000003990 capacitor Substances 0.000 claims abstract description 65
- 238000013016 damping Methods 0.000 claims description 16
- 230000000737 periodic effect Effects 0.000 claims description 8
- 238000011160 research Methods 0.000 abstract description 4
- 238000010587 phase diagram Methods 0.000 description 26
- 238000010586 diagram Methods 0.000 description 17
- 230000004044 response Effects 0.000 description 11
- 238000000354 decomposition reaction Methods 0.000 description 6
- 238000000034 method Methods 0.000 description 5
- 238000009499 grossing Methods 0.000 description 4
- 238000001514 detection method Methods 0.000 description 3
- 230000002441 reversible effect Effects 0.000 description 3
- 241000234295 Musa Species 0.000 description 2
- 235000018290 Musa x paradisiaca Nutrition 0.000 description 2
- 230000006399 behavior Effects 0.000 description 2
- 230000002427 irreversible effect Effects 0.000 description 2
- 238000010923 batch production Methods 0.000 description 1
- 239000003086 colorant Substances 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000009434 installation Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 238000005312 nonlinear dynamic Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 229920006395 saturated elastomer Polymers 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 238000012360 testing method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
- H04L9/001—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols using chaotic signals
Landscapes
- Engineering & Computer Science (AREA)
- Computer Security & Cryptography (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Amplifiers (AREA)
- Control Of Voltage And Current In General (AREA)
Abstract
The invention discloses a chaotic signal steady-state circuit and a memristor device, and relates to the technical field of nonlinear electronic circuits, wherein the chaotic signal steady-state circuit comprises: the memory comprises a steady-state memristor model circuit and a Chua's circuit, wherein the steady-state memristor model circuit comprises a memristor circuit and a steady-state resistor, the memristor circuit comprises an integrator provided with a first capacitor, and the steady-state resistor is connected in parallel with the end part of the first capacitor so as to change the phase delay of the input voltage and the output voltage of the integrator; the steady-state memristor model circuit replaces a nonlinear resistor in the Chua's circuit to form a chaotic signal steady-state circuit. The chaotic signal steady-state circuit provided by the invention is not easy to fall into a fixed-point state, and the parameter adjusting range of elements in the chaotic signal steady-state circuit is enlarged, so that the chaotic signal steady-state circuit is convenient to research and apply.
Description
Technical Field
The embodiment of the invention relates to the technical field of nonlinear electronic circuits, in particular to a chaotic signal steady-state circuit and a memristor device.
Background
Chaos is a new subject in the 19 th century, and the phenomenon of chaos is a fundamental feature of nonlinear dynamics systems. The chaos phenomenon is a random and uncertainty-like process and has wide application in various fields. The result of the chaos phenomenon research breaks the boundaries of certainty and randomness, and is clear: for systems and models that did not contain any external random factors, their long-term behavior exhibited both randomness and microscopic unpredictability, as well as overall stability and ordering of the macrostructures. The Chua's circuit is a window for knowing the characteristics of a nonlinear system because of simple circuit and easy implementation of experiments, the volt-ampere characteristic of the nonlinear resistor of the traditional Chua's circuit is a three-section piecewise linear curve, the nonlinear characteristic is more obvious because the phase diagram of the input voltage and the output voltage of the memristor is an 8-shaped, the memristor is used for replacing the nonlinear resistor of the Chua's circuit, and the chaotic system built on the basis of the memristor and the Chua's circuit has more complex dynamic behaviors under different initial conditions.
However, the chaotic system built based on the existing memristor and Chua's circuit is very sensitive, is extremely easy to sink into a fixed point state, is irreversible in the adjusting process, can only be readjusted by a power supply of a switching system once the system is in a fixed state, and is extremely unfavorable to the research and application of the system due to the narrow parameter adjusting range of elements in the system.
In view of the foregoing, it is desirable to provide a chaotic signal steady-state circuit and a memristor device that address the above-mentioned drawbacks.
Disclosure of Invention
The embodiment of the invention provides a chaotic signal steady-state circuit and a memristor device, and aims to solve the problems that a chaotic system built based on the existing memristor and Chua's circuit is easy to fall into a fixed-point state, the parameter adjusting range of elements in the system is narrow, and research and application of the system are not facilitated.
In order to solve the above technical problems, the present invention provides a chaotic signal steady-state circuit, which includes: the circuit comprises a steady-state memristor model circuit and a Chua's circuit, wherein the steady-state memristor model circuit comprises a memristor circuit and a steady-state resistor, the memristor circuit comprises an integrator provided with a first capacitor, and the steady-state resistor is connected in parallel with the end part of the first capacitor so as to change the phase delay of the input voltage and the output voltage of the integrator; and the steady-state memristor model circuit replaces a nonlinear resistor in the Chua's circuit to form the chaotic signal steady-state circuit.
In a further aspect, the output voltage V of the integrator in the steady state memristor model circuit 0 And input voltage V i Phase difference betweenThe following relationship is satisfied:
wherein C is the capacitance value of the first capacitor, R x For the steady-state resistance, ω is the input voltage V i A kind of electronic device angular frequency.
In a further scheme, the memristor circuit is a cubic smooth magnetic control memristor circuit, and the memristor circuit is a cubic smooth magnetic control memristor circuitThe expression of (2) is:
wherein the coefficients alpha and beta are constants,and q is the charge quantity accumulated by the cubic smooth magnetic control memristor circuit.
In a further aspect, the steady state memristor model circuit includes a voltage follower, the integrator, a first analog multiplier, a second analog multiplier, and a negative resistance circuit, the voltage follower includes a first operational amplifier, the integrator includes a sixth resistor, a second operational amplifier, and the first capacitor, the negative resistance circuit includes a third operational amplifier, a first resistor, a second resistor, and the steady state memristor model circuit further includes a third resistor, a fourth resistor, and a fifth resistor; the inverting input end of the first operational amplifier is connected with the output end of the first operational amplifier, the output end of the first operational amplifier is connected with one end of the sixth resistor, the other end of the sixth resistor is connected with the inverting input end of the second operational amplifier, the non-inverting input end of the second operational amplifier is grounded, the first capacitor is connected between the inverting input end and the output end of the second operational amplifier, the steady-state resistor is connected in parallel with the two ends of the first capacitor, the output end of the second operational amplifier is respectively connected with the two input ends of the first analog multiplier, the output end of the first analog multiplier is connected with the first input end of the second analog multiplier, the second input end of the second analog multiplier is connected with the non-inverting input end of the first operational amplifier, the third input end of the second analog multiplier is grounded through the fifth resistor, the output end of the second analog multiplier is connected with one end of the third resistor, the other end of the third resistor is connected with the non-inverting input end of the third analog multiplier, the third input end of the second analog multiplier is connected with the non-inverting input end of the third analog amplifier, and the non-inverting input end of the second analog multiplier is connected with the non-inverting input end of the second analog amplifier; the Chua's circuit comprises an inductor, a second capacitor, a third capacitor and a damping resistor; the inductor is connected with the second capacitor in parallel, one end of the inductor is grounded, the other end of the inductor is connected with one end of the damping resistor, the other end of the damping resistor is connected with one end of the third capacitor and the non-inverting input end of the first operational amplifier, and the other end of the third capacitor is grounded.
In a further scheme, when the resistance value of the steady-state resistor is 99999 omega and the input voltage is 0.01V-3V, the steady-state memristor model circuit has memristance.
In a further scheme, when the resistance value of the steady-state resistor is 99999 Ω and the input frequency corresponding to the input voltage is 10Hz-5000Hz, the steady-state memristor model circuit has memristance characteristics.
In a further scheme, when the chaotic signal steady-state circuit presents a periodic state or an attractor state, the adjustment range of the steady-state resistor is as follows: 2160Ω -99999 Ω.
In a further scheme, when the chaotic signal steady-state circuit presents a periodic state or an attractor state, the adjusting range of the damping resistor is as follows: 2300 Ω -7850Ω.
The embodiment of the invention also provides a memristor device, which comprises a mounting panel, a wire and a plurality of circuit modules, wherein the mounting panel is provided with mounting sockets corresponding to the circuit modules, and the circuit modules are connected to the corresponding mounting sockets through the wire to form the steady-state memristor model circuit in the chaotic signal steady-state circuit.
In a further scheme, the plurality of circuit modules include two analog operational amplifier modules, three operational amplifier modules, six resistors, a first capacitor and a power supply module, wherein the model of the analog operational amplifier modules is AD633JN, and the model of the operational amplifier modules is AD711KN.
The embodiment of the invention provides a chaotic signal steady-state circuit which comprises a steady-state memristor model circuit and a Chua's circuit, wherein the steady-state memristor model circuit replaces a nonlinear resistor in the Chua's circuit to form the chaotic signal steady-state circuit, the steady-state memristor model circuit comprises an integrator provided with a first capacitor, and the steady-state resistor is connected in parallel with the end part of the first capacitor to change the phase delay of the input voltage and the output voltage of the integrator. According to the chaotic signal steady-state circuit, the end part of the first capacitor is connected with the steady-state resistor in parallel to change the phase delay of the input voltage and the output voltage of the integrator, so that the chaotic signal steady-state circuit is not easy to fall into a fixed-point state, the parameter adjusting range of elements in the chaotic signal steady-state circuit is enlarged, and the chaotic signal steady-state circuit is convenient to study and apply.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a chaotic signal steady-state circuit according to an embodiment of the present invention;
FIG. 2 (a) is a schematic structural diagram of a cubic smooth magnetic control memristor circuit in a chaotic signal steady-state circuit according to an embodiment of the present invention;
FIG. 2 (b) is a schematic diagram of an equivalent structure of a cubic smooth magnetic control memristor circuit in a chaotic signal steady-state circuit according to the embodiment of the present invention;
fig. 3 is a schematic circuit structure diagram of a zeiss chaotic system;
fig. 4 is a phase diagram of the zeiss chaotic system shown in fig. 3, which shows an attractor state;
fig. 5 is a timing chart of voltages across the second capacitor and voltages across the third capacitor in the zeiss chaotic system shown in fig. 4;
fig. 6 is a fourier decomposition diagram of voltages across the second capacitor and voltages across the third capacitor in the zeiss chaotic system shown in fig. 5;
fig. 7 is a phase diagram of the zeiss chaotic system shown in fig. 3, which is shown in a three-cycle state;
fig. 8 is a timing chart of voltages across the second capacitor and voltages across the third capacitor in the zeiss chaotic system shown in fig. 7;
fig. 9 is a fourier decomposition diagram of voltages across the second capacitor and voltages across the third capacitor in the zeiss chaotic system shown in fig. 8;
fig. 10 is a schematic structural diagram of an integrator in the zeiss chaotic system shown in fig. 3;
fig. 11 is a schematic structural diagram of an integrator in a chaotic signal steady-state circuit according to an embodiment of the present invention;
fig. 12 is a phase diagram of an input voltage and an output voltage of an integrator in the zeiss chaotic system shown in fig. 3, and a phase diagram of an input voltage and an output voltage of an integrator in a chaotic signal steady-state circuit provided by an embodiment of the present invention;
fig. 13 is a timing chart of output voltage of an integrator in a chaotic signal steady-state circuit according to an embodiment of the present invention, which shows a comparison with output voltage of the integrator in a zeiss chaotic system;
FIG. 14 is a phase diagram of the response of the cubic smooth magnetically controlled memristor circuit in the Chua's chaotic system shown in FIG. 3 to an input voltage;
FIG. 15 is a phase diagram of a steady-state memristor model circuit in a chaotic signal steady-state circuit according to an embodiment of the present invention responding to an input voltage;
FIG. 16 is a phase diagram of a cubic smooth magnetically controlled memristor circuit in the Chua's chaotic system shown in FIG. 3 versus an input frequency response;
FIG. 17 is a phase diagram of a steady-state memristor model circuit in a chaotic signal steady-state circuit according to an embodiment of the present invention for response to an input frequency;
fig. 18 is a phase diagram of a chaotic signal steady-state circuit according to an embodiment of the present invention, which shows a state in a period state;
fig. 19 is a phase diagram of a chaotic signal steady-state circuit according to an embodiment of the present invention, which shows an attractor state;
FIG. 20 is a Fourier decomposition diagram of the input voltage and the output voltage of the chaotic signal steady-state circuit shown in FIG. 19;
FIG. 21 is a further phase diagram of a chaotic signal steady-state circuit according to an embodiment of the present invention, illustrating the chaotic signal steady-state circuit in an attractor state;
FIG. 22 is a Fourier decomposition diagram of the input voltage and the output voltage of the chaotic signal steady-state circuit shown in FIG. 21;
FIG. 23 is another phase diagram of a chaotic signal steady-state circuit according to an embodiment of the present invention, which illustrates an attractor state;
FIG. 24 is a Fourier decomposition diagram of the input voltage and the output voltage of the chaotic signal steady-state circuit shown in FIG. 23;
FIG. 25 is a further phase diagram of a chaotic signal steady-state circuit according to an embodiment of the present invention, illustrating the chaotic signal steady-state circuit in an attractor state;
FIG. 26 is a Fourier decomposition diagram of the input voltage and the output voltage of the chaotic signal steady-state circuit shown in FIG. 25;
FIG. 27 is another phase diagram of a chaotic signal steady-state circuit according to an embodiment of the present invention, which illustrates an attractor state;
FIG. 28 is a further phase diagram of a chaotic signal steady-state circuit according to an embodiment of the present invention, which illustrates an attractor state;
fig. 29 is a schematic diagram of a mounting panel in a chaotic signal steady-state device according to an embodiment of the present invention;
fig. 30 is a schematic diagram of aperture processing of a mounting panel in a chaotic signal steady-state device according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be understood that the terms "comprises" and "comprising," when used in this specification and the appended claims, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It is also to be understood that the terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.
It should be further understood that the term "and/or" as used in the present specification and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations. As used in this specification and the appended claims, the term "if" may be interpreted as "when..once" or "in response to a determination" or "in response to detection" depending on the context. Similarly, the phrase "if a determination" or "if a [ described condition or event ] is detected" may be interpreted in the context of meaning "upon determination" or "in response to determination" or "upon detection of a [ described condition or event ]" or "in response to detection of a [ described condition or event ]".
The embodiment of the invention provides a chaotic signal steady-state circuit 100, as shown in fig. 1, 2 and 10 to 11, the chaotic signal steady-state circuit 100 comprises: the circuit comprises a steady-state memristor model circuit 1 and a Chua's circuit 2, wherein the steady-state memristor model circuit 1 comprises a memristor circuit and a steady-state resistor R7, the memristor circuit comprises an integrator provided with a first capacitor C1, and the steady-state resistor R7 is connected in parallel with the end part of the first capacitor C1 so as to change the phase delay of the input voltage and the output voltage of the integrator; the steady-state memristor model circuit 1 replaces the nonlinear resistor in the zeiss circuit 2 to form the chaotic signal steady-state circuit 100.
Compared with the prior art, the embodiment of the invention provides a chaotic signal steady-state circuit which comprises a steady-state memristor model circuit and a Chua circuit, wherein the steady-state memristor model circuit replaces a nonlinear resistor in the Chua circuit to form the chaotic signal steady-state circuit, the steady-state memristor model circuit comprises an integrator provided with a first capacitor, and the steady-state resistor is connected in parallel with the end part of the first capacitor to change the phase delay of the input voltage and the output voltage of the integrator. According to the chaotic signal steady-state circuit, the end part of the first capacitor is connected with the steady-state resistor in parallel to change the phase delay of the input voltage and the output voltage of the integrator, so that the chaotic signal steady-state circuit is not easy to fall into a fixed-point state, the parameter adjusting range of elements in the chaotic signal steady-state circuit is enlarged, and the chaotic signal steady-state circuit is convenient to study and apply.
In some embodiments, for example, in this embodiment, the memristor circuit is a cubic smooth magnetic control memristor circuit 3, fig. 2 (a) shows a schematic circuit structure of the cubic smooth magnetic control memristor circuit 3, and fig. 2 (b) shows an equivalent circuit structure of the cubic smooth magnetic control memristor circuit 3. As shown in fig. 1 to 2, the equivalent circuit of the cubic smooth magnetic memristor circuit 3 includes a voltage follower, an integrator, a first analog multiplier U2, a second analog multiplier U1 and a negative resistance circuit, the voltage follower includes a first operational amplifier U3, which can effectively prevent a load phenomenon, the integrator includes a sixth resistor R6, a second operational amplifier U4 and a first capacitor C1, the negative resistance circuit includes a third operational amplifier U5, a first resistor R1 and a second resistor R2, and the steady state memristor model circuit 1 further includes a third resistor R3, a fourth resistor R4 and a fifth resistor R5; the reverse input end of the first operational amplifier U3 is connected with the output end of the first operational amplifier U3, the output end of the first operational amplifier U3 is connected with one end of a sixth resistor R6, the other end of the sixth resistor R6 is connected with the reverse input end of a second operational amplifier U4, the non-inverting input end of the second operational amplifier U4 is grounded, a first capacitor C1 is connected between the reverse input end and the output end of the second operational amplifier U4, a steady-state resistor R7 is connected in parallel with two ends of the first capacitor C1, the output end of the second operational amplifier U4 is respectively connected with two input ends of a first analog multiplier U2, the output end of the first analog multiplier U2 is connected with the first input end of the second analog multiplier U1, the third input end of the second analog multiplier U1 is grounded through a fifth resistor R5, the output end of the second analog multiplier U1 is connected with one end of a third resistor R3, the other end of the third resistor R3 is connected with the non-inverting input end of the third operational amplifier U5 through the third input end of the third resistor R5; as shown in fig. 1, two ends of a first capacitor C1 in the cubic smooth magnetic control memristor circuit 3 are connected in parallel with a steady-state resistor R7 to form a steady-state memristor model circuit 1; the Chua's circuit 2 comprises an inductor L, a second capacitor C2, a third capacitor C3 and a damping resistor R10, wherein the damping resistor R10 comprises an eighth resistor R8 and a ninth resistor R9 which are connected in series, the eighth resistor R8 is a coarse tuning resistor, the ninth resistor R9 is a fine tuning resistor, the inductor L is connected with the second capacitor C2 in parallel, one end of the inductor L is grounded, the other end of the inductor L is connected with one end of the eighth resistor R8, the other end of the eighth resistor R8 is connected with one end of the third capacitor C3 and the non-inverting input end of the first operational amplifier U3 through the ninth resistor R9, and the other end of the third capacitor C3 is grounded.
In the case of no steady-state resistor R7, the equivalent circuit schematic diagram of the cubic smooth magnetically controlled memristor circuit 3 is shown in fig. 2, and the memristor circuit 3 is memristor circuit 3The expression of (2) is:
wherein the coefficients alpha and beta are constants,for the magnetic flux passing through the cubic smoothing memristor circuit 3, q is the charge amount accumulated through the cubic smoothing memristor circuit 3.
Fig. 3 shows a schematic circuit structure of a zeiss chaotic system 4 formed based on a traditional three-time smooth magnetic control memristor circuit 3, and an attractor state shown in fig. 4 and a three-period two-state shown in fig. 7 can be observed through an oscilloscope. As shown in fig. 4 to 6, when the inductance l=17mh, the second capacitance c2=47 nF, the third capacitance c3=4.7nf, and the damping resistance r10=2140Ω, the zeiss chaotic system 4 assumes an attractor state, as shown in fig. 8 to 9, when the inductance l=17mh, the second capacitance c2=47 nF, the third capacitance c3=4.7nf, and the damping resistance r10=2240Ω, U C1 And U C2 The zeiss chaotic system 4 presents a three-period state with the main frequency multiple of three.
However, under the condition that the steady-state resistor R7 is not installed, a circuit of the Chua's chaotic system 4 formed based on the traditional three-time smooth magnetic control memristor circuit 3 is too sensitive and is quite easy to crash, the adjusting range of the damping resistor R10 between the second capacitor C2 and the third capacitor C3 in the Chua's circuit 2 is 2120Ω -2470Ω, and when the damping resistor R10 is greater than 2470Ω, the Chua's chaotic system 4 crashes, namely the Chua's chaotic system 4 falls into a fixed point and does not oscillate any more; when the resistance of the damping resistor R10 is less than 2120Ω, the zeiss chaotic system 4 diverges.
In the case that the first capacitor C1 is not connected in parallel with the steady-state resistor R7, a schematic diagram of the circuit structure of the integrator in the cubic smoothing memristor circuit 3 is shown in fig. 10, and the output voltage V of the integrator 0 And input voltage V i The relation of (2) is:
let-down input voltage V i Is sine wave：
Output voltage V 0 The method comprises the following steps:
wherein U is m For the amplitude of the input voltage, D t Is an integral constant.
FIG. 11 shows a schematic circuit configuration of the integrator with the steady state resistor R7 connected in parallel to the first capacitor C1, wherein the first capacitor C1 of the integrator has the steady state resistor R7 connected in parallel to the output voltage V of the integrator in the steady state memristor model circuit 1 0 The method comprises the following steps:
output voltage V of integrator in steady-state memristor model circuit 1 0 And input voltage V i Phase difference betweenThe following relationship is satisfied:
wherein C is 1 Is the capacitance value of the first capacitor C1, R 7 Is the resistance value of the steady-state resistor R7, omega is the angular frequency of the input voltage, U m For the magnitude of the input voltage, dt' is the integration constant. Output voltage V of integrator 0 V between input voltage and i and the capacitance C of the first capacitor C1 1 Resistance R of steady-state resistor R7 7 Input voltage V i Is related to the angular frequency ω of the circuit, the phase delay is a variable.
Fig. 12 (a) shows the three-time smooth magnetic memristor circuit 3 measured by an oscilloscope without the parallel steady-state resistance R7Output voltage V of integrator 0 And input voltage V i Is a graph of the relationship of (1). Output voltage V of integrator 0 And input voltage V i Phase difference is pi/2, when the input frequency is changed, the output voltage V of the integrator 0 V between input voltage and i there is no phase delay. Fig. 12 (b) shows the output voltage V of the integrator in the three-time smoothing memristor circuit 3 by an oscilloscope with the steady-state resistor R7 connected in parallel to the first capacitor C1 0 And input voltage V i As can be seen from (b) of fig. 12, in the case where the first capacitor C1 is connected in parallel with the steady-state resistor R7, when the input frequency ω is changed, the output voltage V of the integrator 0 And input voltage V i The phase delay between which changes, the output voltage V of the integrator 0 And input voltage V i Between V i Is related to the input frequency ω. Namely, the integrator of the three-time smooth magnetic control memristor circuit 3 is connected with the steady-state resistor R7 in parallel, the phase delay of the integrator is changed, so that the time constant is increased, the first capacitor C1 is not easy to enter a saturated state, the three-time smooth magnetic control ideal memristor circuit in the Chua's chaotic system 4 formed by the traditional three-time smooth magnetic control memristor circuit 3 is changed, the element parameter is irreversible when the element parameter is adjusted, once the element parameter is in the fixed-point state, the Chua chaotic system 4 can only be adjusted again by the switching power supply to return to the state of the original experimental state, and the embodiment of the invention realizes the 11 chaotic signal steady-state circuit 100 which does not enter the fixed-point state, and can obtain the more abundant chaotic state than the Chua chaotic system 4 formed by the traditional three-time smooth magnetic control memristor circuit 3 when the element parameter is adjusted, so that the experimental study and application of the chaotic signal steady-state circuit 100 are convenient.
FIG. 13 shows the output voltage V to the integrator 0 Is a study of the offset condition of (a). After the steady state resistor R7 is connected in parallel, the input voltage V of the integrator is changed as shown in FIG. 13 i In the case of (2), the output voltage V 0 The equilibrium positions of (a) are all 0V, i.e. the output voltage V 0 All pass through the origin point to lead the parallel steady-state resistor R7 to beThe phase diagram of the input voltage and the input current of the three-time smooth magnetic control memristor circuit 3 is like an inclined 8 shape. When the steady-state resistor R7 is not connected in parallel, the balance position of the output voltage is moved under the condition of changing the input voltage of the integrator, namely the output voltage does not pass through the origin, and the phase diagram of the input voltage and the input current of the three-time smooth magnetic control memristor circuit 3 after the steady-state resistor R7 is not connected in parallel cannot show the same inclined 8 shape.
Fig. 14 to 17 show performance testing of the integrator improved steady-state memristor model circuit 1. FIGS. 14-15 illustrate the response of the steady-state memristor model circuit 1 to voltage, and FIGS. 16-17 illustrate the response of the steady-state memristor model circuit 1 to frequency. In some embodiments, for example, in this embodiment, (a) in fig. 14 and (b) in fig. 14 show that the input frequency is 100Hz, the volt-ampere characteristic of the cubic smooth memristor circuit 3 is responsive to the input voltage when the steady state resistance R7 is not connected in parallel, while (a) in fig. 15 and (b) in fig. 15 show that the input frequency is 100Hz, when the resistance value of the parallel steady state resistance R7 is 99999 Ω, the volt-ampere characteristic of the steady state memristor model circuit 1 is responsive to the input voltage, and compared with fig. 14 and 15, it is found that when the input voltage is greater than 1V, the phase diagrams of the input voltage and the output voltage of the cubic smooth memristor circuit 3 and the steady state memristor model circuit 1 all show an "8" shape ", but when the input voltage is less than 0.6V, the phase diagram of the input voltage and the output voltage of the cubic smooth memristor circuit 3 does not have a parallel steady state resistance R7 becomes a straight line, and the phase diagram of the steady state resistance of the cubic smooth memristor circuit 3 can maintain the input voltage of the" 9901 "V" when the input voltage is equal to the steady state resistance value of the steady state resistance of the memristor circuit "9901". That is, when the parallel steady-state resistor R7, for example, the resistance value of the parallel steady-state resistor R7 is 99999 Ω, and the input voltage is 0.01V-3V, the steady-state memristor model circuit 1 still has 12 memristance characteristics, so that the adjustment range of the input voltage of the integrator is improved, the adjustment range of the element parameters in the chaotic signal steady-state circuit 100 is improved, and the experimental study on the chaotic signal steady-state circuit 100 is facilitated.
In some embodiments, such as the present embodiment, FIG. 16 shows the volt-ampere characteristic of the three times smooth magnetically controlled memristor circuit 3 versus the input frequency, and FIG. 17 shows the volt-ampere characteristic of the steady state memristor model circuit 1 versus the input frequency. As shown in fig. 16 (a) and fig. 16 (b), when the steady-state resistor R7 is not connected in parallel, the volt-ampere characteristic of the cubic smooth magnetic control memristor circuit 3 is basically in an 8 shape when the input voltage is 1V and the input frequency is less than 100Hz, so that the memristor characteristic is well maintained, but when the input frequency is increased to 500Hz, the phase diagram of the input voltage and the output voltage of the cubic smooth magnetic control memristor circuit 3 is a straight line, the memristance is degraded into a resistor, and when the input frequency reaches 2000Hz, the phase diagram of the input voltage and the output voltage of the cubic smooth magnetic control memristor circuit 3 is a closed ellipse, so that the memristance characteristic is lost. As shown in fig. 17 (a) and 17 (b), when the input voltage is 1V and the resistance of the parallel steady-state resistor R7 is 99999 Ω, the volt-ampere characteristics of the steady-state memristor model circuit 1 are all kept in the same inclined "8" shape in the process of changing the input frequency from 10Hz to 5000Hz, and the steady-state memristor model circuit 1 perfectly maintains the "memristor" characteristic. In summary, based on the connected steady-state resistance R7, the steady-state memristor model circuit 1 improves the frequency response and the voltage response of the steady-state memristor model circuit 1 under the condition that the basic characteristics of the three-time smooth magnetic control memristor circuit 3 are maintained, so as to realize the chaotic signal steady-state circuit 100 which is not in a 'fixed-point state'.
Fig. 18 to 28 show a case where the chaotic characteristics of the chaotic signal steady-state circuit 100 are tested by an oscilloscope. Fig. 18 shows the chaotic signal steady-state circuit 100 with rich periodic states. The element parameters in the periodic state and the corresponding phase diagram are shown in the following table:
fig. 19 to 28 show phase diagrams of the chaotic signal steady-state circuit 100 with rich attractor states and corresponding fourier exploded diagrams. The parameters of the elements in the presence of the attractor state and the corresponding phase diagram are shown in the following table:
based on the chaotic signal steady-state circuit 100, when the periodic state or the attractor state is realized, the adjustment range of the steady-state resistor R7 is as follows: 2160Ω -99999kΩ, when realizing the periodic state or the attractor state, the adjustment range of the damping resistor R10 is: 2300 Ω -7850Ω.
The embodiment of the invention also provides a memristor device (not shown), which comprises a mounting panel, wires and a plurality of circuit modules, wherein the mounting panel is provided with mounting sockets corresponding to the circuit modules, and the circuit modules are connected to the corresponding mounting sockets through the wires to form the steady-state memristor model circuit 1 in the chaotic signal steady-state circuit 100. In some embodiments, for example, as shown in fig. 29, the plurality of circuit modules includes two analog op-amp modules, three op-amp modules, six resistors, a first capacitor C1 and a power supply module, where the analog op-amp modules are AD633JN and the op-amp modules are AD711KN. In this embodiment, the power module is Vcc of ±15v and Vee power, and the installation socket can be designed into different colors according to the need, for example, all Vcc adopts red banana socket with diameter of 4mm, vee adopts banana socket with diameter of 4mm, and the difficulty in connecting wires and conducting circuit inspection is reduced. Based on the design of this structure, be convenient for build and improve chaotic signal steady-state circuit 100, be convenient for operate, be convenient for carry out batch production simultaneously.
The chaotic signal steady-state circuit comprises a steady-state memristor model circuit and a Chua's circuit, wherein the steady-state memristor model circuit replaces a nonlinear resistor in the Chua's circuit to form the chaotic signal steady-state circuit, the steady-state memristor model circuit comprises an integrator provided with a first capacitor, and the steady-state resistor is connected in parallel with the end part of the first capacitor to change the phase delay of the input voltage and the output voltage of the integrator. According to the chaotic signal steady-state circuit, the end part of the first capacitor is connected with the steady-state resistor in parallel to change the phase delay of the input voltage and the output voltage of the integrator, so that the chaotic signal steady-state circuit is not easy to fall into a fixed-point state, the parameter adjusting range of elements in the chaotic signal steady-state circuit is enlarged, and the chaotic signal steady-state circuit is convenient to study and apply.
While the invention has been described with reference to certain preferred embodiments, it will be understood by those skilled in the art that various changes and substitutions of equivalents may be made and equivalents will be apparent to those skilled in the art without departing from the scope of the invention. Therefore, the protection scope of the invention is subject to the protection scope of the claims.
Claims (8)
1. A chaotic signal steady-state circuit, comprising: a steady state memristor model circuit, and a Chua's circuit, wherein,
the steady-state memristor model circuit comprises a memristor circuit and a steady-state resistor, wherein the memristor circuit comprises an integrator provided with a first capacitor, and the steady-state resistor is connected in parallel with the end part of the first capacitor to change the phase delay of the input voltage and the output voltage of the integrator;
the steady-state memristor model circuit replaces a nonlinear resistor in the Chua's circuit to form the chaotic signal steady-state circuit;
the memristor circuit is a cubic smooth magnetic control memristor circuit, and memristor circuit is a cubic smooth magnetic control memristor circuitThe expression of (2) is:
wherein the coefficients alpha and beta are constants,q is the charge quantity accumulated by the cubic smooth magnetic control memristor circuit;
the steady-state memristor model circuit comprises a voltage follower, the integrator, a first analog multiplier, a second analog multiplier and a negative resistance circuit, wherein the voltage follower comprises a first operational amplifier, the integrator comprises a sixth resistor, a second operational amplifier and the first capacitor, the negative resistance circuit comprises a third operational amplifier, a first resistor and a second resistor, and the steady-state memristor model circuit further comprises a third resistor, a fourth resistor and a fifth resistor;
the inverting input end of the first operational amplifier is connected with the output end of the first operational amplifier, the output end of the first operational amplifier is connected with one end of the sixth resistor, the other end of the sixth resistor is connected with the inverting input end of the second operational amplifier, the non-inverting input end of the second operational amplifier is grounded, the first capacitor is connected between the inverting input end and the output end of the second operational amplifier, the steady-state resistor is connected in parallel with the two ends of the first capacitor, the output end of the second operational amplifier is respectively connected with the two input ends of the first analog multiplier, the output end of the first analog multiplier is connected with the first input end of the second analog multiplier, the second input end of the second analog multiplier is connected with the non-inverting input end of the first operational amplifier, the third input end of the second analog multiplier is grounded through the fifth resistor, the output end of the second analog multiplier is connected with one end of the third resistor, the other end of the third resistor is connected with the non-inverting input end of the third analog multiplier, the third input end of the second analog multiplier is connected with the non-inverting input end of the third analog amplifier, and the non-inverting input end of the second analog multiplier is connected with the non-inverting input end of the second analog amplifier;
the Chua's circuit comprises an inductor, a second capacitor, a third capacitor and a damping resistor;
the inductor is connected with the second capacitor in parallel, one end of the inductor is grounded, the other end of the inductor is connected with one end of the damping resistor, the other end of the damping resistor is connected with one end of the third capacitor and the non-inverting input end of the first operational amplifier, and the other end of the third capacitor is grounded.
2. The chaotic signal steady-state circuit of claim 1, wherein the output voltage V of the integrator in the steady-state memristor model circuit 0 And input voltage V i Phase difference betweenThe following relationship is satisfied:
wherein C is the capacitance value of the first capacitor, R x For the steady-state resistance, ω is the input voltage V i A kind of electronic device angular frequency.
3. The chaotic signal steady-state circuit of claim 1, wherein the steady-state memristor model circuit has a memristance characteristic when the steady-state resistance has a resistance value of 99999 Ω and the input voltage is 0.01V-3V.
4. The chaotic signal steady-state circuit of claim 1, wherein the steady-state memristor model circuit has memristance characteristics when the steady-state resistor has a resistance of 99999 Ω and the input voltage corresponds to an input frequency of 10Hz-5000 Hz.
5. The chaotic signal steady-state circuit of claim 1, wherein when the chaotic signal steady-state circuit presents a periodic state or an attractor state, an adjustment range of the steady-state resistance is: 2160Ω -99999 Ω.
6. The chaotic signal steady-state circuit of claim 1, wherein when the chaotic signal steady-state circuit presents a periodic state or an attractor state, an adjustment range of the damping resistor is: 2300 Ω -7850Ω.
7. A memristor device, characterized in that the memristor device comprises a mounting panel, a wire and a plurality of circuit modules, wherein mounting sockets corresponding to the plurality of circuit modules are arranged on the mounting panel, and the plurality of circuit modules are connected to the corresponding mounting sockets through the wire to form a steady-state memristor model circuit in the chaotic signal steady-state circuit according to any one of claims 1 to 6.
8. The memristor device of claim 7, wherein the plurality of circuit blocks includes two analog op-amp blocks, three op-amp blocks, six resistors, a first capacitor, and a power supply block, wherein the analog op-amp blocks are of a model AD633JN and the op-amp blocks are of a model AD711KN.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110923980.2A CN113645023B (en) | 2021-08-12 | 2021-08-12 | Chaotic signal steady-state circuit and memristor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110923980.2A CN113645023B (en) | 2021-08-12 | 2021-08-12 | Chaotic signal steady-state circuit and memristor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113645023A CN113645023A (en) | 2021-11-12 |
| CN113645023B true CN113645023B (en) | 2023-11-21 |
Family
ID=78421087
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110923980.2A Active CN113645023B (en) | 2021-08-12 | 2021-08-12 | Chaotic signal steady-state circuit and memristor device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113645023B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110147597A (en) * | 2019-05-10 | 2019-08-20 | 山东科技大学 | A kind of multistable magnetic control memristor equivalent simulation circuit |
| CN111404660A (en) * | 2020-03-12 | 2020-07-10 | 华东交通大学 | Four-order memristor chaotic signal source circuit |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US10153729B2 (en) * | 2016-04-28 | 2018-12-11 | Hewlett Packard Enterprise Development Lp | Nano-scale oscillator exhibiting chaotic oscillation |
| FR3074390B1 (en) * | 2017-11-30 | 2020-05-15 | IPception | ULTRA LOW LATENCY DATA ENCRYPTION / DECRYPTION METHOD AND SYSTEM FOR SECURED DATA STORAGE AND / OR COMMUNICATION |
-
2021
- 2021-08-12 CN CN202110923980.2A patent/CN113645023B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110147597A (en) * | 2019-05-10 | 2019-08-20 | 山东科技大学 | A kind of multistable magnetic control memristor equivalent simulation circuit |
| CN111404660A (en) * | 2020-03-12 | 2020-07-10 | 华东交通大学 | Four-order memristor chaotic signal source circuit |
Non-Patent Citations (1)
| Title |
|---|
| 林毅."五阶压控忆阻蔡氏混沌电路的双稳定性".《物理学报》.2018,参见正义第2节. * |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113645023A (en) | 2021-11-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| DE19701262C2 (en) | Method for recognizing the approach of passing magnetic articles | |
| DE60306604T2 (en) | Accurate frequency measurement circuit by time-difference-strain and two counters, as well as resonance-pressure transducer Transmitter | |
| Yang et al. | Modeling and analysis of a fractional-order generalized memristor-based chaotic system and circuit implementation | |
| CN113645023B (en) | Chaotic signal steady-state circuit and memristor device | |
| WO2002019523A1 (en) | Filter system and method for filtering an analog signal | |
| DE102007011121A1 (en) | Binarising circuit for e.g. swinging analog signal, has selecting circuit providing input of output signals of comparator circuits, where output signal is returned from selecting circuit, when comparator circuits return output signal | |
| CN114974358B (en) | Novel third-order charge-controlled memristor equivalent circuit and memristor testing method | |
| DE3940537A1 (en) | ARRANGEMENT FOR PROCESSING SENSOR SIGNALS | |
| EP0207086A1 (en) | Circuit for monitoring the electric current supply of a consumer. | |
| CN109831190B (en) | Time delay regulating circuit | |
| Kyprianidis et al. | Crisis-induced intermittency in a third-order electrical circuit | |
| Yener et al. | Analysis of filter characteristics based on PWL Memristor | |
| CN108021175A (en) | A kind of regulator circuit | |
| Parodi et al. | Static and dynamic hysteretic features in a PWL circuit | |
| CN111786769B (en) | Chaotic circuit structure based on S-shaped local active memristor | |
| CN106782648B (en) | Memristor equivalent circuit realized based on voltage doubling rectifying circuit | |
| CN107194099B (en) | Memristor equivalent realization circuit based on passive filtering and bridge type rectification | |
| CN207074986U (en) | A kind of biasing circuit, clock circuit, chip and electronic equipment | |
| CN109446647A (en) | Voltage fractional order integration control formula recalls rank member | |
| CN109271742A (en) | Magnetic control recalls rank member | |
| CN218276652U (en) | Clock circuit and electronic device | |
| CN216290686U (en) | Wide input voltage constant current control circuit | |
| CN217741702U (en) | Vehicle-mounted ECU input signal level conversion circuit | |
| RU209039U1 (en) | Generator of high-amplitude current pulses | |
| Chen et al. | A random sequence generator based on chaotic circuits |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |