CN107195685B - Method for manufacturing super junction device - Google Patents
Method for manufacturing super junction device Download PDFInfo
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- CN107195685B CN107195685B CN201710519206.9A CN201710519206A CN107195685B CN 107195685 B CN107195685 B CN 107195685B CN 201710519206 A CN201710519206 A CN 201710519206A CN 107195685 B CN107195685 B CN 107195685B
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 21
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- 229920005591 polysilicon Polymers 0.000 claims abstract description 92
- 239000004065 semiconductor Substances 0.000 claims abstract description 37
- 238000005530 etching Methods 0.000 claims abstract description 21
- 238000000151 deposition Methods 0.000 claims abstract description 14
- 239000012535 impurity Substances 0.000 claims abstract description 13
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- 238000009826 distribution Methods 0.000 claims abstract description 10
- 238000005468 ion implantation Methods 0.000 claims description 29
- 210000000746 body region Anatomy 0.000 claims description 19
- 238000002513 implantation Methods 0.000 claims description 19
- 239000002184 metal Substances 0.000 claims description 15
- 239000000758 substrate Substances 0.000 claims description 14
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 8
- 238000001259 photo etching Methods 0.000 claims description 8
- 229910052710 silicon Inorganic materials 0.000 claims description 8
- 239000010703 silicon Substances 0.000 claims description 8
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 5
- 229910052796 boron Inorganic materials 0.000 claims description 5
- 150000004767 nitrides Chemical class 0.000 claims description 5
- 238000003384 imaging method Methods 0.000 claims description 2
- 150000002500 ions Chemical class 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 abstract description 6
- 238000002347 injection Methods 0.000 abstract description 3
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- 238000000206 photolithography Methods 0.000 description 4
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005429 filling process Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
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- 238000004088 simulation Methods 0.000 description 1
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- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
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- H01L29/063—Reduced surface field [RESURF] pn-junction structures
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Abstract
The invention discloses a manufacturing method of a super junction device, which comprises the following steps: providing an N-type semiconductor epitaxial layer and forming a plurality of periodically arranged super junction grooves; filling the super junction groove to form a P-type column, wherein the filling is realized by multiple times of polysilicon deposition, etching after deposition to remove side polysilicon and multiple times of injection, and the injection dosage is gradually reduced from bottom to top; and step three, carrying out thermal propulsion to diffuse the P-type impurities of the P-type column so as to realize uniform concentration gradient distribution in the P-type column and match the doping amount of the P-type column and the N-type column at each longitudinal position. The concentration gradient distribution in the P-type column formed by the method can offset the adverse effect of the inverted trapezoidal super-junction groove formed by the limitation of the etching process on the charge matching between the P-type column and the N-type column, and can improve the charge matching degree between the P-type column and the N-type column, thereby improving the breakdown voltage of the device.
Description
Technical Field
The present invention relates to a method for manufacturing a semiconductor integrated circuit, and more particularly, to a method for manufacturing a super junction device.
Background
The principle of the withstand voltage of the power device is to dope a drift region (drift region) of the device low, so that the device can generate a large-area depletion region at high voltage to achieve the effect of withstand voltage. Vertical type devices are preferred in high voltage applications because they have a thicker drift region.
The Super Junction (Super Junction) device combines the advantages of low loss of a VDMOS during switching and low loss of an IGBT in a conducting state, and is widely applied with excellent performance.
The super junction in the super junction device is composed of P-type columns and N-type columns which are alternately arranged, and is generally realized by forming a super junction groove in an N-type epitaxial layer such as an N-type silicon epitaxial layer and then filling a P-type epitaxial layer such as a P-type silicon epitaxial layer in the super junction groove.
FIG. 1 is an ideal structural diagram of a super junction device; an N-type epitaxial layer 102 is formed on the surface of an N-type semiconductor substrate 101, a super junction trench is formed in the N-type epitaxial layer 102, a P-type epitaxial layer 103a is filled in the super junction trench, and in the existing structure, the P-type epitaxial layer 103a is a single crystal structure formed by an epitaxial process; the P-type columns 103a are formed by the P-type epitaxial layer 103a filled in the super junction trenches, only one P-type column 103a is shown in fig. 1, and in practice, a super junction structure includes a plurality of P-type columns 103a arranged at intervals, and the N-type columns 102 are formed by the N-type epitaxial layer 102 between the P-type columns 103 a. A P-type body region 104 is formed on the surface of the P-type column 103a, and a planar gate structure is formed on the surface of the P-type body region 104, wherein the planar gate structure comprises gate dielectric layers such as a gate oxide layer 105 and a polysilicon gate 106 which are sequentially overlapped; the gate structure can also be a trench gate structure, which is not described in detail. The polysilicon gate 106 also extends to the surface of the N-type column 102, a source region 107 composed of an N + region is formed on the surface of the P-type body region 104, and the source region 107 is self-aligned with one side of the polysilicon gate 106. The N-type semiconductor substrate 101 is thinned and heavily doped to form a drain region, and a drain 108 formed of a back metal layer is formed on the back surface of the drain region. A front metal layer 108 is formed on the front surface, and a source electrode and a gate electrode are led out from the front metal layer, the gate electrode is connected with the polysilicon gate 06 through a contact hole, and the source electrode is simultaneously connected with the source region 107 and the P-type body region 104 through the contact hole.
The structure shown in fig. 1 is an ideal structure, which is mainly considered that the super junction trench is a completely vertical structure, and the cross section of the super junction trench is a rectangular structure, so that the widths of the P-type column 103a at each longitudinal position are consistent, and good charge balance can be achieved between the P-type column 103a and the N-type column 102 at any position in the longitudinal direction.
However, in practice, due to the limitation of the trench etching process, it is impossible to obtain a super junction trench with a completely vertical side surface, and the side surface of the super junction trench is inclined, as shown in fig. 2, which is a schematic view of the actual structure of the conventional super junction device; the difference between the structure shown in fig. 2 and the structure shown in fig. 1 is that the cross section of the super junction trench has an inverted trapezoid shape with a wide top and a narrow bottom, which makes the P-type pillar 103b shown in fig. 2 also have an inverted trapezoid shape, in the conventional structure, the P-type pillar 103b is formed by a P-type epitaxy process at one time, so the doping concentrations of the P-type pillar 103b at each longitudinal position are consistent, but the total doping amount of the P-type pillar 103b at the bottom is smaller than that of the P-type pillar 103b at the top because the width of the P-type pillar 103b at the bottom is narrowed; likewise, the total amount of doping at each longitudinal position of the N-type column 102 is also different. Since the charge balance between the P-type column 103b and the adjacent N-type column 102 is the balance between the total amount of P-type doping and the total amount of N-type doping, the total amount of doping of the P-type column 103b at each longitudinal position is different, which may cause that the P-type column 103b and the N-type column 102 may not achieve good charge matching, so that the maximum depletion region, i.e., the maximum breakdown voltage, may not be achieved.
Disclosure of Invention
The invention aims to provide a manufacturing method of a super junction device, which can improve the charge matching degree between a P-type column and an N-type column, thereby improving the breakdown voltage of the device.
In order to solve the above technical problem, the method for manufacturing a super junction device provided by the present invention comprises the following steps:
step one, providing an N-type semiconductor epitaxial layer, defining by adopting photoetching and etching to form a plurality of super junction grooves which are periodically arranged in the N-type semiconductor epitaxial layer; the side face of the super junction groove deviates from an ideal vertical structure by the limit of an etching process and has an inclination angle of less than 90 degrees, and the cross section structure of the super junction groove in the width direction is in an inverted trapezoid shape with a wide upper part and a narrow lower part.
And step two, filling the super junction groove to form a P-type column, wherein the filling is realized by depositing a plurality of layers of undoped polysilicon.
And after the deposition of each layer of the undoped polysilicon is finished, removing the undoped polysilicon on the side surface of the super junction groove and the surface outside the super junction groove by adopting an isotropic etching process, and only retaining the undoped polysilicon on the bottom surface of the super junction groove.
Then, carrying out P-type ion implantation on the undoped polysilicon reserved on the bottom surface of the super junction groove to convert the corresponding undoped polysilicon into P-type doped polysilicon, gradually reducing the P-type ion implantation dosage corresponding to each layer of the P-type doped polysilicon from bottom to top, and forming the P-type column by each layer of the P-type doped polysilicon; the N-type semiconductor epitaxial layer between the P-type columns forms N-type columns, and the P-type columns and the N-type columns are alternately arranged to form a super junction structure.
And thirdly, thermally propelling to diffuse the P-type impurities of the P-type doped polysilicon in each layer, and utilizing the good impurity diffusivity of the polysilicon to realize uniform concentration gradient distribution in the P-type column after thermal propelling, wherein the concentration gradient distribution is gradually reduced from bottom to top, so that the influence of the gradual increase of the width of the inverted trapezoidal P-type column from bottom to top on the doping amount of each position of the P-type column is compensated, and the doping amounts of the P-type column and the N-type column at each longitudinal position are matched.
In a further improvement, the N-type semiconductor epitaxial layer is formed on the surface of the N-type semiconductor substrate.
The further improvement is that the N-type semiconductor substrate is an N-type silicon substrate, and the N-type semiconductor epitaxial layer is an N-type silicon epitaxial layer.
The further improvement is that the process parameters of the P-type ion implantation corresponding to the P-type doped polysilicon in each layer are as follows: the implantation impurity is boron, the implantation energy is 50-500 kev, and the implantation dosage is 1e12cm-2～1e16cm-2。
In a further improvement, the method further comprises the following steps after the third step:
and step four, forming a P-type body region by adopting photoetching definition and a P-type ion implantation process, wherein the P-type body region is positioned on the top surface of the P-type column and extends into the surfaces of the N-type columns at two sides.
And fifthly, forming a grid structure, wherein the grid structure comprises a grid oxide layer and a polysilicon grid, the polysilicon grid covers the P-shaped body area, and the surface of the P-shaped body area covered by the polysilicon grid is used for forming a channel.
And sixthly, performing N-type heavily doped ion implantation to form a source region.
And seventhly, forming a front metal layer and carrying out imaging on the front metal layer to lead out a source electrode and a grid electrode.
And step eight, forming a drain region consisting of an N-type heavily doped region on the back surface of the N-type semiconductor epitaxial layer.
And step nine, forming a back metal layer and leading out the drain electrode from the back metal layer.
In the fifth step, the grid structure is a plane grid structure, and the grid oxide layer and the polysilicon grid are overlapped on the surface of the P-type body region and extend to the surface of the N-type column.
The gate structure in the fifth step is a trench gate structure and comprises a gate trench formed at the top of the N-type column, the gate oxide layer is formed on the side surface and the bottom surface of the gate trench, the polysilicon gate is filled in the gate trench, and the polysilicon gate covers the P-type body region from the side surface.
The method comprises a step of forming a hard mask layer on the surface of the N-type semiconductor epitaxial layer before the photoetching process in the step one, wherein after the forming region of the super junction groove is defined by the photoetching process, the hard mask layer in the forming region of the super junction groove is removed by an etching process, and then the N-type semiconductor epitaxial layer is etched by taking the hard mask layer as a mask to form the super junction groove.
In a further refinement, the hard mask layer is removed after the thermal drive is completed in step three.
In a further improvement, the hard mask layer is an oxide film or a nitride film.
The further improvement is that the thickness of the first layer of the undoped polysilicon deposited in the step two is 0.5-2 μm; the thickness of each layer of the non-doped polycrystalline silicon above the second layer is 1-4 mu m.
The invention combines the limit function of the etching process on the super junction groove to ensure that the side surface of the super structure groove is of an inclined structure and the section is of an inverted trapezoid after the super junction groove is etched, the invention makes special design for the super structure groove filling process, the invention adopts multiple times of non-doped polysilicon deposition, polysilicon etching after deposition and P-type ion implantation after polysilicon etching to realize the filling of the super junction groove, the implantation dosage of each P-type ion implantation is set to be gradually reduced from the corresponding implantation dosage of each layer of polysilicon from bottom to top, and utilizes the characteristic that P-type impurities are easy to thermally promote and diffuse in the polysilicon to form a P-type column with uniform concentration gradient distribution from bottom to top in the body after thermal promotion, the P-type column with gradually changed longitudinal concentration can realize the doping dosage matching of the P-type column and the N-type column at each longitudinal position by combining the structure with the inverted trapezoid section, the charge matching degree between the P-type columns and the N-type columns can be improved, and thus the breakdown voltage of the device is improved.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
FIG. 1 is an idealized structural schematic of a super junction device;
FIG. 2 is a schematic diagram of the actual structure of a prior art super junction device;
FIG. 3 is a flow chart of a method of fabricating a super junction device according to an embodiment of the present invention;
FIGS. 4A-4H are schematic views of the device structure in various sub-steps during super junction trench filling in a method according to an embodiment of the present invention;
fig. 5A-5D are schematic views of device structures in steps after filling the super junction trench in the method according to the embodiment of the invention.
Detailed Description
FIG. 3 is a flow chart of a method of fabricating a super junction device according to an embodiment of the present invention; FIGS. 4A to 4E are schematic views of device structures in respective sub-steps during super junction trench filling in the method according to the embodiment of the present invention; fig. 5A to 5D are schematic views of device structures in the steps after filling the super junction trench in the method according to the embodiment of the present invention, and the method for manufacturing the super junction device according to the embodiment of the present invention includes the following steps:
step one, as shown in fig. 4A, providing an N-type semiconductor epitaxial layer 102, defining and etching by photolithography to form a plurality of periodically arranged super junction trenches in the N-type semiconductor epitaxial layer 102; the side face of the super junction groove deviates from an ideal vertical structure by the limit of an etching process and has an inclination angle of less than 90 degrees, and the cross section structure of the super junction groove in the width direction is in an inverted trapezoid shape with a wide upper part and a narrow lower part.
The N-type semiconductor epitaxial layer 102 is formed on the surface of the N-type semiconductor substrate 101. In the embodiment of the present invention, the N-type semiconductor substrate 101 is an N-type silicon substrate, and the N-type semiconductor epitaxial layer 102 is an N-type silicon epitaxial layer.
In the embodiment of the invention, a step of forming a hard mask layer 201 on the surface of the N-type semiconductor epitaxial layer 102 is further included before the photolithography process in the first step, and after the photolithography process defines the formation region of the super junction trench, the hard mask layer 201 in the formation region of the super junction trench is removed through an etching process, and then the N-type semiconductor epitaxial layer 102 is etched by using the hard mask layer 201 as a mask to form the super junction trench. In the embodiment of the present invention, the hard mask layer 201 is a stack of an oxide film 201a and silicon nitride 201 b. In other embodiments can also be: the hard mask layer 201 is an oxide film.
And step two, filling the super junction groove to form a P-type column 103b, wherein the filling is realized by depositing a plurality of layers of undoped polysilicon.
And after the deposition of each layer of the undoped polysilicon is finished, removing the undoped polysilicon on the side surface of the super junction groove and the surface outside the super junction groove by adopting an isotropic etching process, and only retaining the undoped polysilicon on the bottom surface of the super junction groove.
Then, performing P-type ion implantation on the undoped polysilicon reserved on the bottom surface of the super junction groove to convert the corresponding undoped polysilicon into P-type doped polysilicon, gradually reducing the P-type ion implantation dosage corresponding to each layer of the P-type doped polysilicon from bottom to top, and forming the P-type column 103b by each layer of the P-type doped polysilicon; the N-type semiconductor epitaxial layer 102 between the P-type columns 103b forms N-type columns, and the P-type columns 103b and the N-type columns are alternately arranged to form a super junction structure.
The filling process of the super junction trench in the second step of the embodiment of the present invention is now described by the polysilicon deposition and P-type ion implantation 3 times shown in fig. 4A to 4H:
as shown in fig. 4A, a first layer of undoped polysilicon 1031 is filled first; a first layer of undoped polysilicon 1031 is formed on the bottom surface, on the sides, and on the surface extending outside the super junction trench, i.e., on the surface of nitride film 201 b. As shown in fig. 4B, after the deposition of the first layer of undoped polysilicon 1031 is completed, an isotropic etching process is used to remove the first layer of undoped polysilicon 1031 on the side surface of the super junction trench and on the surface outside the super junction trench, and only the first layer of undoped polysilicon 1031 on the bottom surface of the super junction trench is remained.
As shown in fig. 4B, a P-type ion implantation 202a is performed, and the first layer of undoped polysilicon 1031 after the P-type ion implantation 202a is converted into a first layer of P-type doped polysilicon 1031. The P-type ion implantation 202a has the process parameters that the implantation impurity is boron, the implantation energy is 50 kev-500 kev, and the implantation dosage is 1e12cm-2～1e16cm-2. The thickness of the first layer of the undoped polysilicon 1031 is 0.5 to 2 μm.
As shown in fig. 4C, a second layer of undoped polysilicon 1032 is filled, and the second layer of undoped polysilicon 1032 is formed on the bottom surface of the super junction trench, i.e., the surface of the first layer of undoped polysilicon 1031 at the bottom, on the side surfaces, and on the surface extending to the outside of the super junction trench, i.e., the surface of the nitride film 201 b.
As shown in fig. 4D, after the deposition of the second layer of undoped polysilicon 1032 is completed, an isotropic etching process is used to remove the second layer of undoped polysilicon 1032 on the side surface of the super junction trench and on the surface outside the super junction trench, and only the second layer of undoped polysilicon 1032 on the bottom surface of the super junction trench is remained.
As shown in fig. 4D, a P-type ion implantation 202b is performed, and the second layer of undoped polysilicon 1032 is converted into a second layer of P-type doped polysilicon 1032 after the P-type ion implantation 202 b. Under the condition that the implantation dose of the P-type ion implantation 202b is less than that of the P-type ion implantation 202a, the process parameters of the P-type ion implantation 202b are as follows: the implantation impurity is boron, the implantation energy is 50-500 kev, and the implantation dosage is 1e12cm-2～1e16cm-2. The second layer is undopedThe thickness of the crystalline silicon 1032 is 1 μm to 4 μm.
As shown in fig. 4E, a third layer of undoped polysilicon 1033 is filled, and the third layer of undoped polysilicon 1033 is formed on the bottom surface of the super junction trench, i.e., the bottom surface of the second layer of undoped polysilicon 1032, on the side surfaces, and on the surface extending outside the super junction trench, i.e., the surface of the nitride film 201 b.
As shown in fig. 4F, after the deposition of the third layer of undoped polysilicon 1033 is completed, an isotropic etching process is used to remove the third layer of undoped polysilicon 1033 on the side surface of the super junction trench and on the surface outside the super junction trench, and only the third layer of undoped polysilicon 1033 on the bottom surface of the super junction trench is remained.
As shown in fig. 4F, a P-type ion implantation 202c is performed, and the third layer of undoped polysilicon 1033 after the P-type ion implantation 202c is converted into a third layer of P-type doped polysilicon 1033. Under the condition that the implantation dose of the P-type ion implantation 202c is smaller than that of the P-type ion implantation 202b, the process parameters of the P-type ion implantation 202c are as follows: the implantation impurity is boron, the implantation energy is 50-500 kev, and the implantation dosage is 1e12cm-2～1e16cm-2. The thickness of the third layer of undoped polysilicon 1033 is 1 μm to 4 μm.
The hard mask layer 201 is then removed, as shown in fig. 4G.
And thirdly, performing thermal drive to diffuse the P-type impurities of the P-type doped polysilicon in each layer, and forming the P-type columns 103b after the thermal drive of the polysilicon 1031, 1032 and 1033 as shown in fig. 4H, as described above with reference to fig. 4G. The polysilicon has good impurity diffusivity, so that uniform concentration gradient distribution is realized in the P-type column 103b after thermal propulsion, and the concentration gradient distribution is gradually reduced from bottom to top, thereby making up for the influence of the gradual increase of the width of the inverted trapezoidal P-type column 103b from bottom to top on the doping amount of each position of the P-type column 103b, and enabling the doping amounts of the P-type column 103b and the N-type column at each longitudinal position to be matched.
In a further improvement, the method further comprises the following steps after the third step:
step four, as shown in fig. 5A, a P-type body region 104 is formed by using photolithography definition and a P-type ion implantation process, and the P-type body region 104 is located on the top surface of the P-type pillar 103b and extends into the N-type pillar surfaces on both sides.
Step five, as shown in fig. 5B, a gate structure is formed, the gate structure includes a gate oxide layer 105 and a polysilicon gate 106, the polysilicon gate 106 covers the P-type body region 104, and the surface of the P-type body region 104 covered by the polysilicon gate is used for forming a channel.
In the embodiment of the present invention, in the fifth step, the gate structure is a planar gate structure, and the gate oxide layer 105 and the polysilicon gate 106 are stacked on the surface of the P-type body region 104 and extend to the surface of the N-type pillar.
In other embodiments can also be: the gate structure is a trench gate structure and comprises a gate trench formed at the top of the N-type column, the gate oxide layer 105 is formed on the side surface and the bottom surface of the gate trench, the polysilicon gate 106 is filled in the gate trench, and the polysilicon gate 106 covers the P-type body region 104 from the side surface.
Step six, as shown in fig. 5C, performing N-type heavily doped ion implantation to form a source region 107. And then also a P + doped body extraction region formed through the source region 107.
Step seven, as shown in fig. 5D, forming a front metal layer 108 and patterning the front metal layer 108 to lead out a source and a gate. The gate is connected to the polysilicon gate 106 through a contact hole, and the source is simultaneously connected to the source region 107 and the P-type body region 104 through a contact hole.
Step eight, as shown in fig. 5D, a drain region formed by an N-type heavily doped region is formed on the back surface of the N-type semiconductor epitaxial layer 102. In the embodiment of the invention, the N-type semiconductor substrate 101 is heavily doped N-type, and a drain region is formed by thinning the back surface of the N-type semiconductor substrate 101, and in other embodiments, a drain region can also be formed by performing back surface N + injection after thinning the back surface of the N-type semiconductor substrate 101.
Step nine, as shown in fig. 5D, a back metal layer 109 is formed and the drain is led out from the back metal layer 109.
The method of the embodiment of the invention can form the P-type column 103b with uniform concentration gradient distribution which is gradually reduced from bottom to top in the body, the doping amount matching of the P-type column 103b and the N-type column 102 at each longitudinal position can be realized by combining the structure with the inverted trapezoid cross section of the P-type column 103b with gradually changed longitudinal concentration, so that the charge matching degree between the P-type column 103b and the N-type column 102 can be improved, the breakdown voltage of the device is improved, and the breakdown voltage of the super-junction device obtained by the method of the embodiment of the invention can reach 654V through simulation.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.
Claims (11)
1. A method for manufacturing a super junction device is characterized by comprising the following steps:
step one, providing an N-type semiconductor epitaxial layer, defining by adopting photoetching and etching to form a plurality of super junction grooves which are periodically arranged in the N-type semiconductor epitaxial layer; the side surface of the super junction groove deviates from an ideal vertical structure by the limitation of an etching process and has an inclination angle of less than 90 degrees, and the cross section structure of the super junction groove in the width direction is in an inverted trapezoid shape with a wide upper part and a narrow lower part;
filling the super junction groove to form a P-type column, wherein the filling is realized by depositing a plurality of layers of undoped polysilicon;
each layer of the undoped polysilicon is formed on the bottom surface, the side surface and the surface extending out of the super junction groove, the undoped polysilicon on the side surface of the super junction groove and the surface outside the super junction groove is removed by adopting an isotropic etching process after the deposition of each layer of the undoped polysilicon is finished, and only the undoped polysilicon on the bottom surface of the super junction groove is reserved;
then, carrying out P-type ion implantation on the undoped polysilicon reserved on the bottom surface of the super junction groove to convert the corresponding undoped polysilicon into P-type doped polysilicon, gradually reducing the P-type ion implantation dosage corresponding to each layer of the P-type doped polysilicon from bottom to top, and forming the P-type column by each layer of the P-type doped polysilicon; the N-type semiconductor epitaxial layer between the P-type columns forms N-type columns, and the P-type columns and the N-type columns are alternately arranged to form a super junction structure;
and thirdly, thermally propelling to diffuse the P-type impurities of the P-type doped polysilicon in each layer, and utilizing the good impurity diffusivity of the polysilicon to realize uniform concentration gradient distribution in the P-type column after thermal propelling, wherein the concentration gradient distribution is gradually reduced from bottom to top, so that the influence of the gradual increase of the width of the inverted trapezoidal P-type column from bottom to top on the doping amount of each position of the P-type column is compensated, and the doping amounts of the P-type column and the N-type column at each longitudinal position are matched.
2. The method of manufacturing a super junction device of claim 1, wherein: the N-type semiconductor epitaxial layer is formed on the surface of the N-type semiconductor substrate.
3. The method of manufacturing a super junction device of claim 2, wherein: the N-type semiconductor substrate is an N-type silicon substrate, and the N-type semiconductor epitaxial layer is an N-type silicon epitaxial layer.
4. The method of manufacturing a super junction device of claim 1, wherein: the technological parameters of the P-type ion implantation corresponding to each layer of the P-type doped polycrystalline silicon are as follows: the implantation impurity is boron, the implantation energy is 50-500 kev, and the implantation dosage is 1e12cm-2～1e16cm-2。
5. The method of manufacturing a super junction device of claim 1, wherein: the method also comprises the following steps after the third step:
step four, forming a P-type body region by adopting photoetching definition and a P-type ion implantation process, wherein the P-type body region is positioned on the top surface of the P-type column and extends into the surfaces of the N-type columns at two sides;
fifthly, forming a grid structure, wherein the grid structure comprises a grid oxide layer and a polysilicon grid, the polysilicon grid covers the P-shaped body area, and the surface of the P-shaped body area covered by the polysilicon grid is used for forming a channel;
sixthly, injecting N-type heavily doped ions to form a source region;
forming a front metal layer and carrying out imaging on the front metal layer to lead out a source electrode and a grid electrode;
forming a drain region consisting of an N-type heavily doped region on the back surface of the N-type semiconductor epitaxial layer;
and step nine, forming a back metal layer and leading out the drain electrode from the back metal layer.
6. The method of manufacturing a super junction device of claim 5, wherein: and fifthly, the grid structure is a planar grid structure, and the grid oxide layer and the polysilicon grid are overlapped on the surface of the P-type body region and extend to the surface of the N-type column.
7. The method of manufacturing a super junction device of claim 5, wherein: and fifthly, the grid electrode structure is a trench grid structure and comprises a grid electrode trench formed at the top of the N-shaped column, the grid electrode oxide layers are formed on the side surface and the bottom surface of the grid electrode trench, the polycrystalline silicon grid is filled in the grid electrode trench, and the polycrystalline silicon grid covers the P-shaped body region from the side surface.
8. The method of manufacturing a super junction device of claim 1, wherein: and step one, before the photoetching process, a hard mask layer is formed on the surface of the N-type semiconductor epitaxial layer, after the forming area of the super junction groove is defined by the photoetching process, the hard mask layer in the forming area of the super junction groove is removed by an etching process, and then the N-type semiconductor epitaxial layer is etched by taking the hard mask layer as a mask to form the super junction groove.
9. The method of manufacturing a super junction device of claim 8, wherein: removing the hard mask layer after completing the thermal drive in step three.
10. The method of manufacturing a super junction device of claim 8, wherein: the hard mask layer is an oxide film or a nitride film.
11. The method of manufacturing a super junction device of claim 1, wherein: the thickness of the first layer of the undoped polysilicon deposited in the second step is 0.5-2 microns; the thickness of each layer of the non-doped polycrystalline silicon above the second layer is 1-4 mu m.
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