CN110134175B - 基准电压电路以及半导体装置 - Google Patents

基准电压电路以及半导体装置 Download PDF

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CN110134175B
CN110134175B CN201811633844.4A CN201811633844A CN110134175B CN 110134175 B CN110134175 B CN 110134175B CN 201811633844 A CN201811633844 A CN 201811633844A CN 110134175 B CN110134175 B CN 110134175B
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坂口薰
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Abstract

本发明涉及基准电压电路以及半导体装置。一种基准电压电路，具有串联连接的耗尽型MOS晶体管和增强型MOS晶体管，并从增强型MOS晶体管的漏极输出基准电压，耗尽型MOS晶体管和增强型MOS晶体管的栅极被共同连接在一起，其中，耗尽型MOS晶体管至少具有串联连接的第一耗尽型MOS晶体管和第二耗尽型MOS晶体管，该基准电压电路具有电容器，该电容器的一端与第一耗尽型MOS晶体管的漏极连接，另一端与第一耗尽型MOS晶体管的源极连接。

Description

基准电压电路以及半导体装置
技术领域
本发明涉及生成恒定电压的基准电压电路。
背景技术
以往，作为在半导体集成电路中生成基准电压的单元，使用了ED型的基准电压电路(例如，参照专利文献1)。图5示出基本的ED型基准电压电路。图5的ED型基准电压电路50由串联连接的耗尽型的MOS晶体管51和增强型的MOS晶体管52构成。以这样的方式构成的ED型基准电压电路50虽然是简单的电路，但能够生成电源电压依赖性小且温度依赖性小的基准电压Vref。
专利文献1：日本特开2007-266715号公报
但是，在现有的ED型基准电压电路中，在为了实现低消耗电流而减小了耗尽型MOS晶体管的电流的情况下，电路的启动花费时间。特别是，在容性的负载与输出端子3连接的情况下，启动所需的时间的增加变得显著。
发明内容
本发明的目的在于提供一种即使在消耗电流低的同时容性负载与输出端连接的情况下也能够快速地启动的基准电压电路。
本发明的一个方式的基准电压电路具有串联连接的耗尽型MOS晶体管和增强型MOS晶体管，并从增强型MOS晶体管的漏极输出基准电压，耗尽型MOS晶体管和增强型MOS晶体管的栅极被共同连接在一起，该基准电压电路的特征在于，耗尽型MOS晶体管至少具有串联连接的第一耗尽型MOS晶体管和第二耗尽型MOS晶体管，该基准电压电路具有电容器，该电容器的一端与第一耗尽型MOS晶体管的漏极连接，另一端与第一耗尽型MOS晶体管的源极连接。
根据本发明的基准电压电路，由于能够将多个耗尽型MOS晶体管串联连接，并在其连接点与输出端子之间具有电容器，因此，即使在消耗电流低的同时容性负载与输出端连接的情况下，也能够快速地启动。
附图说明
图1是用于说明本发明的第1实施方式的基准电压电路的电路图。
图2是用于说明本发明的第2实施方式的基准电压电路的电路图。
图3是用于说明本发明的第3实施方式的基准电压电路的电路图。
图4是用于说明第3实施方式的基准电压电路的其它例子的电路图。
图5是用于说明现有的基准电压电路的电路图。
标号说明
10、20、30、40：基准电压电路；11、11a、11b、31：耗尽型NMOS晶体管；12：增强型NMOS晶体管；13：电容器；24、25：PMOS晶体管。
具体实施方式
以下，参照附图来说明本发明的实施方式。
[第1实施方式]
图1是用于说明本发明的第1实施方式的基准电压电路10的电路图。基准电压电路10是向输出端子3输出以基准端子2为基准的恒定的基准电压Vref的电路。
基准电压电路10具有耗尽型NMOS晶体管11a及11b、增强型NMOS晶体管12和电容器13。
耗尽型NMOS晶体管11a的漏极与电源端子1连接，源极与耗尽型NMOS晶体管11b的漏极连接，栅极与耗尽型NMOS晶体管11b的栅极连接。耗尽型NMOS晶体管11b的栅极和源极与增强型NMOS晶体管12的栅极和漏极连接。增强型NMOS晶体管12的源极与基准端子2连接。电容器13的一个端子与耗尽型NMOS晶体管11b的漏极连接，另一个端子与耗尽型NMOS晶体管11b的源极连接。输出端子3与耗尽型NMOS晶体管11b的源极和增强型NMOS晶体管12的漏极的连接节点连接。
下面，对本实施方式的基准电压电路10的动作进行说明。
关于基准电压电路10，在对电源端子1施加了足以进行动作的电源电压的情况下，耗尽型NMOS晶体管11a和增强型NMOS晶体管12在饱和区域中动作，耗尽型NMOS晶体管11b在非饱和区域中动作。而且，由于栅极与源极间电压大于阈值电压，所以耗尽型NMOS晶体管11a和11b均导通。因此，由于耗尽型NMOS晶体管11a和11b的漏极电流流过增强型NMOS晶体管12，因此，增强型NMOS晶体管12在栅极处产生基准电压Vref。
在稳态下，电容器13被充电，流过耗尽型NMOS晶体管11a的源极的电流全部流入耗尽型NMOS晶体管11b的漏极。此外，由于与输出端子3连接的负载电容也被充电，所以流过耗尽型NMOS晶体管11b的源极的电流全部流入增强型NMOS晶体管12的漏极。这里，关于负载电容，虽然未图示，但设为与输出端子3连接的容性负载、以及与输出端子3连接的栅极、结、布线的电容的总和。
在该状态下，耗尽型NMOS晶体管11a和11b作为1个耗尽型NMOS晶体管11发挥功能。即，耗尽型NMOS晶体管11a和11b的栅极宽度W相等，当设各自的栅极长度为L11a、L11b时，耗尽型NMOS晶体管11作为栅极宽度为W、栅极长度为L11a+L11b的耗尽型NMOS晶体管发挥功能。因此，在耗尽型NMOS晶体管11中流过与栅极宽度W和栅极长度L11a+L11b对应的电流。
接着，说明从未对电源端子1施加电源电压的状态起施加电源电压而使基准电压电路10启动的情况下的动作。
在未对电源端子1施加电源电压的状态下，电容器13和负载电容被放电，基准电压Vref为0V。当对电源端子1施加了电源电压时，从耗尽型NMOS晶体管11a向电容器13过渡性地流过电流，电容器13被开始充电。此外，在电容器13中过渡地流动的电流流过增强型NMOS晶体管12的漏极和负载电容，负载电容被充电而使基准电压Vref启动。
即，在启动时直到电容器13的充电完成为止的期间，能够利用从耗尽型NMOS晶体管11a向电容器13流动的电流对负载电容进行充电。因此，能够减小稳态下的基准电压电路10的消耗电流，并且能够高速地提高基准电压Vref。
在该结构中，更加高速地提高基准电压Vref，因此，优选使耗尽型NMOS晶体管11a的栅极长度(L11a)比耗尽型NMOS晶体管11b的栅极长度(L11b)短。当设与耗尽型NMOS晶体管11a的源极、耗尽型NMOS晶体管11b的漏极和电容器13的一个端子连接的节点的电位为Vc时，通过上述的方式，能够通过增大启动时的充电电流并且提高电压VC的达到电压而高速地提高基准电压Vref，从而能够减小稳态的消耗电流。耗尽型NMOS晶体管11a的电流供给能力比耗尽型NMOS晶体管11b高。
[第2实施方式]
图2是用于说明第2实施方式的基准电压电路20的电路图。另外，对与图1所示的第1实施方式的基准电压电路10相同的结构要素标注相同标号，并适当省略重复说明。
基准电压电路20针对第1实施方式的基准电压电路10，如图所示地配置耗尽型NMOS晶体管11a、11b、增强型NMOS晶体管12和电容器13，并追加了由PMOS晶体管24和PMOS晶体管25构成的电流镜电路。
以下，对以上述这样的方式构成的基准电压电路20的动作进行说明。
在稳态下，电容器13和负载电容被充电，在耗尽型NMOS晶体管11a中流过的电流被电流镜电路复制而流过增强型NMOS晶体管12，由此，产生基准电压Vref。以上的动作与基准电压电路10相同。
接着，说明从未对电源端子1施加电源电压的状态起施加电源电压而使基准电压电路20启动的情况下的动作。
在未对电源端子1施加电源电压的状态下，电容器13和负载电容被放电，基准电压Vref为0V。当对电源端子1施加了电源电压时，电容器13被开始充电。在耗尽型NMOS晶体管11中，在过渡地对电容器13进行了充电的期间，耗尽型NMOS晶体管11a成为主导，栅极长度短，因此，流过的电流比稳态大。该电流由电流镜流入增强型NMOS晶体管12的漏极和负载电容。因此，负载电容被充电而使基准电压Vref启动。根据以上的动作，基准电压电路20能够获得与基准电压电路10相同的效果。
即使以上述这样的方式具有电流镜电路而构成的基准电压电路20是使用P型衬底的廉价的CMOS工艺，NMOS晶体管也具有不容易受到背栅效果的影响的效果。
[第3实施方式]
图3是用于说明本发明的第3实施方式的基准电压电路30的电路图。另外，对与图1所示的第1实施方式的基准电压电路10相同的结构要素标注相同标号，并适当省略重复说明。
第3实施方式的基准电压电路30针对第1实施方式的基准电压电路10，追加了共源共栅连接(cascode-connected)在耗尽型NMOS晶体管11a与电源端子1之间的耗尽型NMOS晶体管31。具体而言，耗尽型NMOS晶体管31的栅极与耗尽型NMOS晶体管11a的源极连接，漏极与电源端子1连接，源极与耗尽型NMOS晶体管11a的漏极连接。除此以外，都成为与基准电压电路10相同的结构。耗尽型NMOS晶体管31的电流供给能力比耗尽型NMOS晶体管11a和耗尽型NMOS晶体管11b高，耗尽型NMOS晶体管31的栅极与漏极间耐压以及源极与漏极间耐压比耗尽型NMOS晶体管11a高。
基准电压电路30的稳态和启动时的动作与基准电压电路10相同，并且，效果也相同。根据本实施方式的基准电压电路30，除了第1实施方式中所说明的效果以外，还具有能够获得相对于电源端子1的电源电压的变动更加稳定的基准电压Vref的效果。
图4是用于说明第3实施方式的另一例的电路图。基准电压电路40针对基准电压电路30，变更了电容器13的连接位置。具体而言，电容器13的一个端子与输出端子3连接，另一个端子与耗尽型NMOS晶体管31的源极连接。其它方面成为与基准电压电路30相同的结构。
关于基准电压电路40的稳态的动作，与基准电压电路10相同。关于基准电压电路40的启动时的动作，构成为仅经由耗尽型NMOS晶体管31而对电容器13进行充电，因此，基准电压Vref从基准电压电路30更加高速地启动。
即，根据基准电压电路40，除了基准电压电路30的效果以外，还具有能够使基准电压Vref的启动更加高速的效果。
如以上所说明那样，本发明的基准电压电路将多个耗尽型MOS晶体管串联连接，并在其连接点与输出端子3之间具有电容器，因此，虽然是低消耗电流，但是即使在包含容性负载在内的负载电容与输出端连接的情况下，也能够快递地启动。
以上，对本发明的实施方式进行了说明，但本发明并不受上述实施方式限定，当然能够在不脱离本发明的宗旨的范围内进行各种变更。
例如，在面向电源电压较高的应用的半导体集成电路中，也可以替代耗尽型NMOS晶体管11a，由高耐压耗尽型NMOS晶体管构成。耗尽型NMOS晶体管11a的栅极与漏极间耐压以及源极与漏极间耐压比耗尽型NMOS晶体管11b高。
并且，例如，说明为使耗尽型NMOS晶体管11a和耗尽型NMOS晶体管11b的栅极宽度相等，但也可以适当调整栅极宽度以发挥本发明的效果。
并且，例如，在第2实施方式中，还可以采用如第3实施方式中的耗尽型NMOS晶体管31那样将共源共栅连接晶体管追加到耗尽型NMOS晶体管11a与PMOS晶体管24之间的电路结构。
并且，例如，还可以采用替代耗尽型NMOS晶体管而使用耗尽型PMOS晶体管且替代增强型NMOS晶体管而使用增强型PMOS晶体管的电路结构。

Claims (11)

1.一种基准电压电路，其具有串联连接的耗尽型MOS晶体管和增强型MOS晶体管，并从所述增强型MOS晶体管的漏极输出基准电压，所述耗尽型MOS晶体管和所述增强型MOS晶体管的栅极被共同连接在一起，该基准电压电路的特征在于，
所述耗尽型MOS晶体管至少由第一耗尽型MOS晶体管和第二耗尽型MOS晶体管构成，所述第一耗尽型MOS晶体管的栅极和源极与所述增强型MOS晶体管的栅极和漏极连接，所述第二耗尽型MOS晶体管的栅极与所述第一耗尽型MOS晶体管的栅极连接，所述第二耗尽型MOS晶体管的源极与所述第一耗尽型MOS晶体管的漏极连接，
该基准电压电路具有电容器，该电容器的一端与所述第一耗尽型MOS晶体管的漏极连接，另一端与所述第一耗尽型MOS晶体管的源极连接。
2.根据权利要求1所述的基准电压电路，其特征在于，
所述基准电压电路具有第三耗尽型MOS晶体管，
所述第三耗尽型MOS晶体管的栅极与所述第二耗尽型MOS晶体管的源极连接，所述第三耗尽型MOS晶体管的源极与所述第二耗尽型MOS晶体管的漏极连接。
3.一种基准电压电路，其具有耗尽型MOS晶体管、增强型MOS晶体管和电流镜电路，并从所述增强型MOS晶体管的漏极输出基准电压，该基准电压电路的特征在于，
所述耗尽型MOS晶体管至少由第一耗尽型MOS晶体管和第二耗尽型MOS晶体管构成，所述第一耗尽型MOS晶体管的栅极和源极与所述增强型MOS晶体管的源极连接，所述第二耗尽型MOS晶体管的栅极与所述第一耗尽型MOS晶体管的栅极连接，所述第二耗尽型MOS晶体管的源极与所述第一耗尽型MOS晶体管的漏极连接，
该基准电压电路具有电容器，该电容器的一端与所述第一耗尽型MOS晶体管的漏极连接，另一端与所述第一耗尽型MOS晶体管的源极连接，
所述电流镜电路的输入端子与所述耗尽型MOS晶体管连接，所述电流镜电路的输出端子与所述增强型MOS晶体管的栅极和漏极连接，所述电流镜电路使与所述耗尽型MOS晶体管流出的电流成比例的电流流到所述增强型MOS晶体管的漏极。
4.根据权利要求1或3所述的基准电压电路，其特征在于，
所述第二耗尽型MOS晶体管的电流供给能力比所述第一耗尽型MOS晶体管高。
5.根据权利要求1或3所述的基准电压电路，其特征在于，
所述第二耗尽型MOS晶体管的栅极与漏极间耐压以及源极与漏极间耐压比所述第一耗尽型MOS晶体管高。
6.根据权利要求3所述的基准电压电路，其特征在于，
所述基准电压电路具有第三耗尽型MOS晶体管，
所述第三耗尽型MOS晶体管的栅极与所述第二耗尽型MOS晶体管的源极连接，所述第三耗尽型MOS晶体管的源极与所述第二耗尽型MOS晶体管的漏极连接，所述第三耗尽型MOS晶体管的漏极与所述电流镜电路的输入端子连接。
7.一种基准电压电路，其具有串联连接的耗尽型MOS晶体管和增强型MOS晶体管，并从所述增强型MOS晶体管的漏极输出基准电压，所述耗尽型MOS晶体管和所述增强型MOS晶体管的栅极被共同连接在一起，该基准电压电路的特征在于，
所述耗尽型MOS晶体管至少由第一耗尽型MOS晶体管和第二耗尽型MOS晶体管构成，所述第一耗尽型MOS晶体管的栅极和源极与所述增强型MOS晶体管的栅极和漏极连接，所述第二耗尽型MOS晶体管的栅极与所述第一耗尽型MOS晶体管的栅极连接，所述第二耗尽型MOS晶体管的源极与所述第一耗尽型MOS晶体管的漏极连接，
该基准电压电路具有：
第三耗尽型MOS晶体管，该第三耗尽型MOS晶体管的栅极与所述第二耗尽型MOS晶体管的源极连接，该第三耗尽型MOS晶体管的源极与所述第二耗尽型MOS晶体管的漏极连接；以及
电容器，该电容器的一端与所述第三耗尽型MOS晶体管的源极连接，另一端与所述第一耗尽型MOS晶体管的源极连接。
8.一种基准电压电路，其具有耗尽型MOS晶体管、增强型MOS晶体管和电流镜电路，并从所述增强型MOS晶体管的漏极输出基准电压，该基准电压电路的特征在于，
所述耗尽型MOS晶体管至少由第一耗尽型MOS晶体管和第二耗尽型MOS晶体管构成，所述第一耗尽型MOS晶体管的栅极和源极与所述增强型MOS晶体管的源极连接，所述第二耗尽型MOS晶体管的栅极与所述第一耗尽型MOS晶体管的栅极连接，所述第二耗尽型MOS晶体管的源极与所述第一耗尽型MOS晶体管的漏极连接，
该基准电压电路具有：
第三耗尽型MOS晶体管，该第三耗尽型MOS晶体管的栅极与所述第二耗尽型MOS晶体管的源极连接，该第三耗尽型MOS晶体管的源极与所述第二耗尽型MOS晶体管的漏极连接；以及
电容器，该电容器的一端与所述第三耗尽型MOS晶体管的源极连接，另一端与所述第一耗尽型MOS晶体管的源极连接，
所述电流镜电路的输入端子与所述第三耗尽型MOS晶体管的漏极连接，所述电流镜电路的输出端子与所述增强型MOS晶体管的栅极和漏极连接，所述电流镜电路使与所述耗尽型MOS晶体管流出的电流成比例的电流流到所述增强型MOS晶体管的漏极。
9.根据权利要求2、6、7、8中的任意一项所述的基准电压电路，其特征在于，
所述第三耗尽型MOS晶体管的电流供给能力比所述第一耗尽型MOS晶体管和所述第二耗尽型MOS晶体管高。
10.根据权利要求2、6、7、8中的任意一项所述的基准电压电路，其特征在于，
所述第三耗尽型MOS晶体管的栅极与漏极间耐压以及源极与漏极间耐压比所述第二耗尽型MOS晶体管高。
11.一种半导体装置，该半导体装置具有权利要求1至3及6至8中的任意一项所述的基准电压电路。
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Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2020035307A (ja) * 2018-08-31 2020-03-05 エイブリック株式会社 定電流回路
JP6887457B2 (ja) * 2019-03-01 2021-06-16 力晶積成電子製造股▲ふん▼有限公司Ｐｏｗｅｒｃｈｉｐ Ｓｅｍｉｃｏｎｄｕｃｔｏｒ Ｍａｎｕｆａｃｔｕｒｉｎｇ Ｃｏｒｐｏｒａｔｉｏｎ 基準電圧発生回路及び不揮発性半導体記憶装置
CN115202430B (zh) * 2021-04-13 2024-05-24 拓尔微电子股份有限公司 基准电压产生电路和振荡器
CN114115420B (zh) * 2021-11-25 2022-11-29 合肥宽芯电子技术有限公司 一种e/d_nmos基准电压源
FR3131481A1 (fr) * 2021-12-23 2023-06-30 Wise Integration Circuit de reference de tension

Citations (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4644182A (en) * 1984-11-13 1987-02-17 Fujitsu Limited Delay circuit having delay time period determined by discharging operation
CN1159656A (zh) * 1995-12-11 1997-09-17 三菱电机株式会社 半导体集成电路
US6005378A (en) * 1998-03-05 1999-12-21 Impala Linear Corporation Compact low dropout voltage regulator using enhancement and depletion mode MOS transistors
CN101667050A (zh) * 2009-08-14 2010-03-10 西安龙腾微电子科技发展有限公司 高精度电压基准电路
CN101963819A (zh) * 2009-07-24 2011-02-02 精工电子有限公司 基准电压电路和电子设备
CN102200797A (zh) * 2010-03-23 2011-09-28 精工电子有限公司 基准电压电路
CN102576738A (zh) * 2009-10-16 2012-07-11 株式会社半导体能源研究所 逻辑电路和半导体器件
CN102915070A (zh) * 2011-08-04 2013-02-06 拉碧斯半导体株式会社 半导体集成电路
CN103309389A (zh) * 2012-03-12 2013-09-18 精工电子有限公司 低通滤波电路和电压调节器
CN204166421U (zh) * 2014-09-10 2015-02-18 成都星芯微电子科技有限公司 一种低功耗低噪声高电源电压抑制比的电压基准源电路

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56108258A (en) * 1980-02-01 1981-08-27 Seiko Instr & Electronics Ltd Semiconductor device
JPH08335122A (ja) * 1995-04-05 1996-12-17 Seiko Instr Inc 基準電圧用半導体装置
JP4084872B2 (ja) * 1997-08-28 2008-04-30 株式会社リコー ボルテージレギュレータ
JP2002328732A (ja) * 2001-05-07 2002-11-15 Texas Instr Japan Ltd 基準電圧発生回路
JP4761458B2 (ja) 2006-03-27 2011-08-31 セイコーインスツル株式会社 カスコード回路および半導体装置
JP2008234584A (ja) * 2007-03-23 2008-10-02 Toshiba Corp 基準電圧発生回路
US7948220B2 (en) * 2007-04-11 2011-05-24 International Rectifier Corporation Method and apparatus to reduce dynamic Rdson in a power switching circuit having a III-nitride device
JP5438477B2 (ja) 2009-11-26 2014-03-12 トレックス・セミコンダクター株式会社 基準電圧回路
US9184243B2 (en) * 2013-07-12 2015-11-10 Infineon Technologies Americas Corp. Monolithic composite III-nitride transistor with high voltage group IV enable switch

Patent Citations (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4644182A (en) * 1984-11-13 1987-02-17 Fujitsu Limited Delay circuit having delay time period determined by discharging operation
CN1159656A (zh) * 1995-12-11 1997-09-17 三菱电机株式会社 半导体集成电路
US6005378A (en) * 1998-03-05 1999-12-21 Impala Linear Corporation Compact low dropout voltage regulator using enhancement and depletion mode MOS transistors
CN101963819A (zh) * 2009-07-24 2011-02-02 精工电子有限公司 基准电压电路和电子设备
CN101667050A (zh) * 2009-08-14 2010-03-10 西安龙腾微电子科技发展有限公司 高精度电压基准电路
CN102576738A (zh) * 2009-10-16 2012-07-11 株式会社半导体能源研究所 逻辑电路和半导体器件
CN104992980A (zh) * 2009-10-16 2015-10-21 株式会社半导体能源研究所 逻辑电路和半导体器件
CN102200797A (zh) * 2010-03-23 2011-09-28 精工电子有限公司 基准电压电路
CN102915070A (zh) * 2011-08-04 2013-02-06 拉碧斯半导体株式会社 半导体集成电路
CN103309389A (zh) * 2012-03-12 2013-09-18 精工电子有限公司 低通滤波电路和电压调节器
CN204166421U (zh) * 2014-09-10 2015-02-18 成都星芯微电子科技有限公司 一种低功耗低噪声高电源电压抑制比的电压基准源电路

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