CN110112160B - Array substrate, preparation method thereof and display device - Google Patents
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- CN110112160B CN110112160B CN201910394109.0A CN201910394109A CN110112160B CN 110112160 B CN110112160 B CN 110112160B CN 201910394109 A CN201910394109 A CN 201910394109A CN 110112160 B CN110112160 B CN 110112160B
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Abstract
The invention relates to the field of display, and discloses an array substrate, a preparation method thereof and a display device, wherein the array substrate comprises: a plurality of photosensitive structures; each photosensitive structure comprises a PIN device and a first TFT; the first TFT includes: a first electrode provided over the substrate; a first insulating layer provided over the first electrode; a second electrode provided on the first insulating layer; an active layer disposed on the second electrode, the active layer penetrating the first insulating layer to contact the first electrode, and the active layer having a channel region connected between the first electrode and the second electrode; a second insulating layer disposed on the active layer; a gate electrode disposed on the second insulating layer, the gate electrode covering the channel region; the PIN device is disposed on the first TFT and electrically connected to the gate. The first TFT in the array substrate is small in size, the structure between the first TFT and the PIN device is compact, the occupied area on the substrate parallel to the substrate is small, the pixel density of a product can be effectively improved, and the production of the product with high PPI is facilitated.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate, a preparation method of the array substrate and a display device.
Background
At present, PIN (photo diode P-I-N) devices are increasingly integrated into a screen due to good photosensitive characteristics and compatibility with a panel process, and are used in the fields of fingerprint identification, pulse detection and the like, wherein the use of the PIN devices is beneficial to increasing the integration level of the screen, and meanwhile, the functions of the screen can be enriched, and the additional value of the screen is improved. However, in the conventional PIN photosensitive sensor device, the TFT device and the PIN unit are independent and parallel units, and the structure occupies a large area, which is not favorable for the production of high PPI (pixel density) products.
Disclosure of Invention
The invention discloses an array substrate, a preparation method thereof and a display device.
In order to achieve the purpose, the invention provides the following technical scheme:
an array substrate, comprising: the photosensitive structure comprises a substrate and a plurality of photosensitive structures arranged on the substrate; each photosensitive structure comprises a PIN device and a first TFT; wherein the first TFT includes:
a first electrode provided on the substrate;
a first insulating layer provided over the first electrode;
a second electrode provided on the first insulating layer;
an active layer disposed on the second electrode, the active layer contacting the first electrode through the first insulating layer, and the active layer having a channel region connected between the first electrode and the second electrode, the channel region including a first contact region contacting the first electrode, a second contact region contacting the second electrode, and a connection region between the first contact region and the second contact region;
a second insulating layer disposed on the active layer;
a gate electrode disposed on the second insulating layer, the gate electrode covering the channel region in a direction perpendicular to the substrate;
the PIN device is disposed on the first TFT and electrically connected to the gate.
In the above array substrate, for convenience of description, the direction parallel to the substrate is a horizontal direction, and the direction perpendicular to the substrate is a vertical direction, in the structure of the array substrate, the substrate is provided with a plurality of photosensitive structures, and the plurality of photosensitive structures may be distributed in an array or other distribution manners, and are mainly set according to the functional requirements to be realized by the photosensitive structures, each photosensitive structure may include a PIN device and a first TFT electrically connected to the PIN device, wherein the first TFT includes a first electrode, a first insulating layer and a second electrode sequentially stacked on the substrate, an active layer directly contacting the second electrode on the second electrode, and the active layer is connected to the first electrode through the first insulating layer, and the active layer has a channel region connected between the first electrode and the second electrode, the channel region includes a first contact region where the active layer contacts the first electrode, a second contact region where the active layer contacts the second electrode, and a connection region located between and connecting the first contact region and the second contact region, the connection region of the active layer being non-parallel to the substrate, wherein the connection region may be disposed perpendicular to the substrate; the active layer is provided with a second insulating layer, the second insulating layer is provided with a grid electrode, the grid electrode covers a channel region of the active layer in a direction vertical to the substrate, namely, the orthographic projection of the channel region on the substrate is positioned in the orthographic projection of the grid electrode on the substrate, wherein, the PIN device is positioned above the first TFT and is electrically connected with the grid electrode, in the first TFT electrically connected with the PIN device, the first electrode and the second electrode are arranged along the direction vertical to the substrate and are connected through the active layer, namely, relative to the substrate, the first TFT is a vertical TFT in structure, the structure is compact, the device size is smaller, the occupied area is smaller, in addition, the PIN device is positioned above the first TFT, namely, the PIN device and the first TFT are arranged in the vertical direction, the structure is compact with the first TFT, and the PIN device and the TFT connected with the PIN device are different from the prior art in that the PIN device and the TFT connected with the PIN device, the arrangement mode of the PIN device and the first TFT saves the occupied area of the substrate in the horizontal direction, is favorable for improving the pixel density of a product, and is favorable for the production of the product with high PPI.
Therefore, the first TFT in the array substrate is small in size, the structure between the first TFT and the PIN device is compact, the occupied area on the substrate parallel to the substrate is small, the pixel density of a product can be effectively improved, and the production of the product with high PPI is facilitated.
Preferably, an orthographic projection of the first electrode on the substrate protrudes from the second electrode on two sides; the number of the first contact region, the second contact region, the connection region and the gate is two; wherein one gate is electrically connected to the PIN device and the other gate is used to apply a fixed potential.
Preferably, the photosensitive structure further comprises: a signal line electrically connected to the PIN device; the signal line is arranged on the metal layer above the PIN device and is not overlapped with the PIN device; the signal line is conducted with the PIN device through a transparent bridging line; the transparent bridging line is arranged on the PIN device and the film layer on the metal layer.
Preferably, the array substrate further includes a plurality of sub-pixels arranged in an array on the substrate, and each of the sub-pixels includes a light emitting device and a second TFT.
Preferably, the gate electrode of the second TFT is disposed on the same layer as the gate electrode of the first TFT.
Preferably, the active layer of the second TFT is disposed in the same layer as the active layer of the first TFT.
Preferably, the source-drain electrode of the second TFT is disposed in the same layer as the signal line.
Preferably, the anode of the light emitting device and the transparent bridge line are disposed in the same layer.
Based on the same invention concept, the invention also provides a preparation method of the array substrate, which comprises the following steps:
sequentially forming a first electrode, a first insulating layer, a second electrode, an active layer, a second insulating layer and a gate electrode which form a first TFT on a substrate; wherein the active layer contacts the first electrode through the first insulating layer, and the active layer has a channel region connected between the first electrode and the second electrode, the channel region including a first contact region contacting the first electrode, a second contact region contacting the second electrode, and a connection region between the first contact region and the second contact region;
forming a PIN device electrically connected to the gate electrode on the first TFT.
Preferably, the preparation method further comprises:
forming an active layer of a second TFT simultaneously with forming an active layer of the first TFT;
forming a gate electrode of the second TFT simultaneously with forming a gate electrode of the first TFT;
carrying out a doping process on the exposed part of the active layer of the second TFT by utilizing the grid shielding of the second TFT;
after the PIN device is formed, simultaneously forming a signal line and a source drain electrode of the second TFT;
and forming a transparent bridging line for conducting the PIN device and the signal line, and forming an anode of the light-emitting device.
Based on the same inventive concept, the present invention further provides a display device, including any one of the array substrates provided in the above technical solutions.
Drawings
Fig. 1 to 7 are schematic diagrams illustrating structural changes of a film layer in a manufacturing process of an array substrate according to an embodiment of the invention;
fig. 8 is a schematic view illustrating a film structure of an array substrate according to an embodiment of the present invention;
FIG. 9 is a schematic structural diagram of a photosensitive structure according to an embodiment of the present invention;
icon: 1-a substrate; 2-PIN devices; 3-a first TFT; 4-a signal line; 5-transparent bridge connection lines; 6-a second TFT; 7-an anode; 31-a first electrode; 32-a first insulating layer; 33-a second electrode; 34, 62-active layer; 35-a second insulating layer; 36,37, 61-gate; 63-source drain electrodes; 341, 342-channel region.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Fig. 7 is a schematic view illustrating a film structure of an array substrate according to an embodiment of the present invention, and fig. 8 is a schematic view illustrating a film structure of an array substrate according to an embodiment of the present invention; referring to fig. 7, 8 and 9, an embodiment of the present invention provides an array substrate, including: a substrate 1, a plurality of photosensitive structures provided on the substrate; each photosensitive structure includes a PIN device 2 and a first TFT 3; wherein the first TFT includes: a first electrode 31 provided over the substrate; a first insulating layer 32 provided on the first electrode 31;
a second electrode 33 provided over the first insulating layer; an active layer 34 disposed on the second electrode 33, the active layer 34 contacting the first electrode 31 through the first insulating layer 32, and the active layer 34 having a channel region 341 connected between the first electrode and the second electrode, the channel region 341 including a first contact region contacting the first electrode, a second contact region contacting the second electrode, and a connection region between the first contact region and the second contact region; a second insulating layer 35 provided on the active layer 34; a gate electrode 36 provided on the second insulating layer 35, the gate electrode 36 covering the channel region in a direction perpendicular to the substrate; a PIN device is provided on the first TFT3 and is electrically connected to the gate electrode 36.
In the array substrate, for convenience of illustration, the direction parallel to the substrate 1 is a horizontal direction, and the direction perpendicular to the substrate 1 is a vertical direction, in the structure of the array substrate, the substrate 1 is provided with a plurality of photosensitive structures, and the plurality of photosensitive structures may be distributed in an array, or in other distribution manners, and are mainly arranged according to the functional requirements that the photosensitive structures are required to implement, each photosensitive structure may include a PIN device 2 and a first TFT3 electrically connected to the PIN device 2, wherein the first TFT3 includes a first electrode 31, a first insulating layer 32, and a second electrode 33 sequentially stacked on the substrate 1, an active layer 34 disposed on the second electrode 33 and directly contacting the second electrode, and the active layer 34 is connected to the first electrode 31 through the first insulating layer 31, and the active layer 34 has a channel region 341 connected between the first electrode 31 and the second electrode 33, the channel region 341 includes a first contact region where the active layer contacts the first electrode, a second contact region where the active layer 34 contacts the second electrode 33, and a connection region located between and connecting the first contact region and the second contact region, the connection region of the active layer being not parallel to the substrate, wherein the connection region may be disposed perpendicular to the substrate; a second insulating layer 35 is disposed on the active layer 34, and a gate electrode 36 is disposed on the second insulating layer 35, in a direction perpendicular to the substrate, the gate electrode 36 covers a channel region 341 of the active layer, that is, an orthographic projection of the channel region 341 on the substrate 1 is located within an orthographic projection of the gate electrode 36 on the substrate 1, wherein the PIN device 2 is located above the first TFT3 and electrically connected to the gate electrode 36, in the first TFT3 electrically connected to the PIN device 2, the first electrode 31 and the second electrode 33 are arranged in a direction perpendicular to the substrate 1, and are connected through the active layer 34, that is, the first TFT3 is a vertical TFT in structure with respect to the substrate 1, and is compact in structure, small in device size, and small in occupied area, and further, the PIN device 2 is located above the first TFT3, that is, the PIN device 2 and the first TFT3 are arranged in a vertical direction, and is compact in structure with the first TFT3, unlike the prior art in which devices and TFTs connected thereto are arranged in a horizontal direction, the arrangement mode of the PIN device and the first TFT saves the occupied area of the substrate in the horizontal direction, is favorable for improving the pixel density of a product, and is favorable for the production of the product with high PPI.
Therefore, the first TFT in the array substrate is small in size, the structure between the first TFT and the PIN device is compact, the occupied area on the substrate parallel to the substrate is small, the pixel density of a product can be effectively improved, and the production of the product with high PPI is facilitated.
Specifically, the orthographic projection of the second electrode 33 on the substrate 1 protrudes from the first electrode 31 on both sides; as shown in fig. 7 and 9, the first contact region, the second contact region, the connection region, and the gate are all two, one gate 36 and the other gate 37; one gate 36 is electrically connected to the PIN device 2 and the other gate 37 is used to apply a fixed potential. The width of the first electrode 31 is greater than that of the second electrode 33, the second electrode 33 is above the first electrode 31, the orthographic projection of the second electrode 33 on the substrate 1 falls within the orthographic projection of the first electrode 31 on the substrate 1, namely, both sides of the first electrode 31 extend out of both sides of the second electrode 33, both sides of the first electrode 31 relative to both sides of the second electrode 33 respectively form a protruding part, the active layer 34 of the first TFT covers the second electrode 33 and contacts with the second electrode 33, the parts of the active layer 34 contacting with both side parts of the second electrode 33 and the second electrode 33 form a second contact region, the active layer can cross over the second electrode 33 and both ends respectively contact with the first electrode 31, namely, the active layer respectively forms two first contact regions with the first electrode 31, and the orthographic projections of the two first contact regions on the substrate 1 are respectively located on both sides of the orthographic projection of the second electrode 33 on the substrate 1, i.e., two first contact regions are respectively located at the protruding portions at two sides of the first electrode 31, two channel regions, i.e., a channel region 341 and a channel region 342, are formed in the active layer, wherein a gate electrode is respectively disposed at each of two sides corresponding to the first electrode 31 and the second electrode 33, the two gate electrodes are insulated from each other, each gate electrode corresponds to one channel region in the active layer 34 and covers the corresponding channel region in the vertical direction, of the two gate electrodes, the gate electrode 36 is connected to the PIN device 2, the PIN device 2 can be directly disposed on the gate electrode to be in contact with and electrically connected to the gate electrode, the gate electrode 37 is used for loading a fixed potential, the gate electrode 37 loaded with the fixed potential is configured by the structure of the first TFT3, i.e., a double-gate structure is disposed in the first TFT3, so that the gate electrode 37 loaded with the fixed potential is loaded with a certain voltage to control the output signal of the first TFT3 together with the voltage signal generated by, has the function of amplifying the photosensitive signal and leads the sensitivity of the photosensitive signal to be higher.
As shown in fig. 9, the photosensitive structure in the array substrate further includes: a signal line 4 electrically connected to the PIN device 2, where the signal line 4 is used for applying a fixed potential; the signal line 4 is arranged on the metal layer above the PIN device 2 and is not overlapped with the PIN device 2; the signal line 4 is conducted with the PIN device 2 through the transparent bridging line 5; the transparent bridging line 5 is arranged on the film layer above the metal layer on which the PIN device 2 and the signal line 4 are arranged.
Specifically, the array substrate further includes a plurality of sub-pixels arranged in an array on the substrate 1, each sub-pixel includes a light emitting device and a second TFT6, and the second TFT6 is a switch for controlling the optical device.
And with regard to the film arrangement in the second TFT6 structure, in particular, the gate 61 of the second TFT6 may be arranged in the same layer as the gate 36 and the gate 37 of the first TFT 3; the active layer 62 of the second TFT6 may be disposed in the same layer as the active layer 34 of the first TFT 3; the source-drain electrodes 63 of the second TFT6 are provided in the same layer as the signal line 4. The structure of the second TFT6 and the structure of the first TFT3 are prepared simultaneously, so that the process flow is simplified, and the cost is saved.
The anode 7 and the transparent bridging line 5 of the light-emitting device are arranged on the same layer, that is, the transparent bridging line 5 is one part of the anode 7 layer of the light-emitting device, and the transparent bridging line 5 and the anode 7 in the anode 7 layer are insulated from each other, so that the transparent bridging line 5 is formed on one part of the anode 7 layer, and the process flow is saved.
In the above array substrate, the orthographic projection of the signal line 4 on the substrate 1 may be provided on the peripheral side of the orthographic projection of the PIN device 2 on the substrate 1, that is, the signal line 4 is provided on the peripheral side of the PIN device 2 in the horizontal direction, and specifically, as shown in fig. 7, as one arrangement of the signal line 4, the signal line 4 may be provided on the side of the PIN device 2 facing away from the first TFT3 in the horizontal direction, that is, the orthographic projection of the signal line 4 on the substrate 1 is located on the side of the orthographic projection of the PIN device 2 on the substrate 1 facing away from the first TFT3 on the substrate 1; as another arrangement of the signal lines 4, as shown in fig. 8, the signal lines 4 may be disposed on a side of the PIN device 2 facing the first TFT3 in a horizontal direction and correspond to the first TFT3 in a vertical direction, that is, an orthogonal projection of the signal lines 4 on the substrate 1 may overlap an orthogonal projection of the first TFT3 on the substrate 1, so as to increase compactness of the photosensitive structure in the array substrate, and further reduce an occupied area of the photosensitive structure and improve pixel density.
Based on the same inventive concept, referring to fig. 1 to 7, the present invention further provides a method for manufacturing an array substrate, including: first, a first electrode 31, a first insulating layer 32, a second electrode 33, an active layer 34, a second insulating layer 35, and a gate electrode 36, which constitute the first TFT3, are formed in this order on a substrate 1; wherein the active layer 34 contacts the first electrode 31 through the first insulating layer 32, and the active layer 34 has a channel region 341 connected between the first electrode 31 and the second electrode 33, the channel region 341 including a first contact region contacting the first electrode 31, a second contact region contacting the second electrode 33, and a connection region between the first contact region and the second contact region; then, the PIN device 2 electrically connected to the gate is formed on the first TFT 3.
Specifically, in the above manufacturing method, a light emitting device and a second TFT for controlling the light emitting device are formed at the same time as the photosensitive structure is formed, wherein, specifically, a part of a film layer in the second TFT is formed in the same layer and material as a part of a film layer of a first TFT in the photosensitive structure, that is, the second TFT is also manufactured at the same time as the first TFT, and specifically, the manufacturing method may be as follows:
first, as shown in fig. 1, a first electrode 31, a first insulating layer 32, and a second electrode 33 are formed in this order on a substrate; then, as shown in fig. 2, the active layer 34 of the first TFT and the active layer 62 of the second TFT are formed on the first insulating layer 32 at the same time, that is, the active layer 34 of the first TFT and the active layer 62 of the second TFT can be simultaneously prepared in the same preparation process, and a portion of the active layer 62 of the second TFT corresponding to the source and drain electrodes is doped, so that a portion of the active layer 62 of the second TFT corresponding to the source and drain electrodes is made conductive, and the active layer 34 of the first TFT contacts the first electrode 31 through the first insulating layer 32, and the active layer 34 of the first TFT has a channel region connected between the first electrode 31 and the second electrode 33, the channel region includes a first contact region contacting the first electrode 31, a second contact region contacting the second electrode 33, and a connection region located between the first contact region and the second contact region; next, as shown in fig. 3, a second insulating layer 35 is formed on the first insulating layer 32 and the active layer 34 of the first TFT and the active layer 62 of the second TFT, and then the gate electrode of the first TFT and the gate electrode of the second TFT are simultaneously formed on the second insulating layer 35; next, as shown in fig. 4 and 5, forming a PIN device 2 on the gate of the first TFT, and then forming an interlayer dielectric layer on the same layer of the PIN device 2; then, as shown in fig. 6, a signal line 4 electrically connected to the PIN device and connected to a fixed potential is formed on the interlayer dielectric layer, the signal line 4 is not directly connected to the PIN device 2, and is insulated from the PIN device 2, and a source/drain electrode 63 of the second TFT is formed at the same time, and the source/drain electrode 62 penetrates through the interlayer dielectric layer and the second insulating layer 35 to be in contact with and electrically connected to a portion corresponding to the active layer 62 of the second TFT; next, as shown in fig. 7, a flat layer is formed on the interlayer dielectric layer, the PIN device 2, the signal line 4, and the source/drain electrode 63, and the transparent bridge line 5 and the anode 7 of the light emitting device are formed on the flat layer by using the same patterning process, in which the transparent bridge line 5 penetrates through the flat layer to be connected with the PIN device 2 and is connected with the signal line 4, the PIN device 2 is electrically connected with the signal line 4, and the anode 7 penetrates through the flat layer to be connected with the source/drain electrode of the second TFT. In the preparation method, the second TFT6 and the first TFT3 are prepared simultaneously, and partial film layers in the structures of the second TFT6 and the first TFT3 are prepared at the same layer and at the same time, so that the preparation method is beneficial to simplifying the preparation process and saving the preparation cost.
Based on the same inventive concept, an embodiment of the present invention further provides a display device, including any one of the array substrates provided in the above embodiments.
It will be apparent to those skilled in the art that various changes and modifications may be made in the embodiments of the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (11)
1. An array substrate, comprising: the photosensitive structure comprises a substrate and a plurality of photosensitive structures arranged on the substrate; each photosensitive structure comprises a PIN device and a first TFT; wherein the first TFT includes:
a first electrode provided on the substrate;
a first insulating layer provided over the first electrode;
the second electrode is arranged on the first insulating layer, and the orthographic projection of the first electrode on the substrate protrudes out of the second electrode on two sides;
an active layer disposed on the second electrode, the active layer contacting the first electrode through the first insulating layer, and the active layer having a channel region connected between the first electrode and the second electrode, the channel region including a first contact region contacting the first electrode, a second contact region contacting the second electrode, and a connection region between the first contact region and the second contact region;
a second insulating layer disposed on the active layer;
a gate electrode disposed on the second insulating layer, the gate electrode covering the channel region in a direction perpendicular to the substrate;
the PIN device is disposed on the first TFT and electrically connected to the gate.
2. The array substrate of claim 1, wherein there are two of the first contact region, the second contact region, the connection region and the gate; wherein one gate is electrically connected to the PIN device and the other gate is used to apply a fixed potential.
3. The array substrate of claim 1, wherein the photosensitive structure further comprises: a signal line electrically connected to the PIN device; the signal line is arranged on the metal layer above the PIN device and is not overlapped with the PIN device; the signal line is conducted with the PIN device through a transparent bridging line; the transparent bridging line is arranged on the PIN device and the film layer on the metal layer.
4. The array substrate of claim 3, further comprising a plurality of sub-pixels arranged in an array on the substrate, each of the sub-pixels comprising a light emitting device and a second TFT.
5. The array substrate of claim 4, wherein the gate of the second TFT is disposed on the same layer as the gate of the first TFT.
6. The array substrate of claim 4, wherein the active layer of the second TFT is disposed in the same layer as the active layer of the first TFT.
7. The array substrate of claim 4, wherein the source and drain electrodes of the second TFT are disposed on the same layer as the signal line.
8. The array substrate of claim 4, wherein the anode of the light emitting device is disposed on the same layer as the transparent bridge line.
9. A method for preparing an array substrate according to any one of claims 1 to 8, comprising:
sequentially forming a first electrode, a first insulating layer, a second electrode, an active layer, a second insulating layer and a gate electrode which form a first TFT on a substrate; wherein the active layer contacts the first electrode through the first insulating layer, and the active layer has a channel region connected between the first electrode and the second electrode, the channel region including a first contact region contacting the first electrode, a second contact region contacting the second electrode, and a connection region between the first contact region and the second contact region;
forming a PIN device electrically connected to the gate electrode on the first TFT.
10. The method of manufacturing according to claim 9, further comprising:
forming an active layer of a second TFT simultaneously with forming an active layer of the first TFT;
forming a gate electrode of the second TFT simultaneously with forming a gate electrode of the first TFT;
carrying out a doping process on the exposed part of the active layer of the second TFT by utilizing the grid shielding of the second TFT;
after the PIN device is formed, simultaneously forming a signal line and a source drain electrode of the second TFT;
and forming a transparent bridging line for conducting the PIN device and the signal line, and forming an anode of the light-emitting device.
11. A display device comprising the array substrate according to any one of claims 1 to 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910394109.0A CN110112160B (en) | 2019-05-13 | 2019-05-13 | Array substrate, preparation method thereof and display device |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910394109.0A CN110112160B (en) | 2019-05-13 | 2019-05-13 | Array substrate, preparation method thereof and display device |
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| CN110112160A CN110112160A (en) | 2019-08-09 |
| CN110112160B true CN110112160B (en) | 2021-03-23 |
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| US11735605B2 (en) * | 2019-11-12 | 2023-08-22 | Boe Technology Group Co., Ltd. | Display substrate and method for manufacturing the same, and display apparatus |
| CN112768477B (en) * | 2021-01-19 | 2023-08-01 | Tcl华星光电技术有限公司 | Array substrate, preparation method thereof and display panel |
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