CN110087392B

CN110087392B - Circuit board structure and manufacturing method thereof

Info

Publication number: CN110087392B
Application number: CN201810072395.4A
Authority: CN
Inventors: 谢育忠; 陈裕华; 简俊贤
Original assignee: Unimicron Technology Corp
Current assignee: Unimicron Technology Corp
Priority date: 2018-01-25
Filing date: 2018-01-25
Publication date: 2021-08-10
Anticipated expiration: 2038-01-25
Also published as: CN110087392A

Abstract

The invention provides a circuit board structure and a manufacturing method thereof, wherein the circuit board structure comprises an insulating layer, a first circuit layer and a second circuit layer which are arranged on two opposite sides of the insulating layer, a conductive through hole which penetrates through the insulating layer and is electrically connected with the first circuit layer and the second circuit layer, a capacitor dielectric layer, a dielectric layer and a rewiring circuit layer. The first circuit layer includes a first capacitor electrode. The capacitor dielectric layer is located on the first capacitor electrode. The dielectric layer covers the first circuit layer and the capacitor dielectric layer. The redistribution layer comprises a redistribution circuit on the dielectric layer, a first conductive blind via in the dielectric layer and connected with the first circuit layer, and a second capacitor electrode in the dielectric layer. The two ends of the second capacitor electrode are respectively contacted with the capacitor dielectric layer and the redistribution circuit. The second capacitor electrode, the capacitor dielectric layer and the first capacitor electrode form a capacitor.

Description

Circuit board structure and manufacturing method thereof

Technical Field

The present disclosure relates to circuit board structures, and particularly to a circuit board structure with a capacitor and a method for manufacturing the same.

Background

With the demand of electronic products toward higher functionality, higher signal transmission speed and higher circuit device density, the functions of the integrated circuit chip become stronger, and the number of passive devices associated with the chip increases dramatically for consumer electronic products. Moreover, when the electronic products are emphasized to be light, thin, small, and small, how to accommodate a large number of electronic components in a limited packaging space has become a technical bottleneck to be solved and overcome by electronic packaging manufacturers. In order to solve this problem, packaging technology gradually moves to a System integration stage of a single Package System (SIP), especially to the packaging of a Multi-Chip Module (MCM). Among them, embedded active device and passive device technology (embedded technology) becomes a key technology. By embedding the elements, the packaging volume can be greatly reduced, and more high-functionality elements can be put in, so that the layout area of the surface of the substrate is increased, and the aim of thinning the electronic product is fulfilled.

Common embedded passive capacitive elements are Metal-Insulator-Metal (MIM) capacitors and Metal-Oxide-Metal (MOM) capacitors, commonly referred to as sandwich capacitors. However, in the process of fabricating the embedded passive capacitor device, at least three masks with specific patterns are required to define the two metal electrodes forming the capacitor and the insulator/oxide located between the two metal electrodes. As such, it is more complicated and costly to manufacture, and may result in a reduction in yield (yield). Therefore, in the fabrication of a circuit board structure having an embedded passive device, it is an urgent need to simplify the fabrication process to improve the fabrication efficiency and yield, further reduce the volume of the circuit board structure, and reduce the fabrication cost.

Disclosure of Invention

The invention provides a circuit board structure and a manufacturing method thereof, which can reduce the whole thickness of a packaging structure, improve the manufacturing efficiency and yield and reduce the manufacturing cost.

The invention provides a circuit board structure, which comprises an insulating layer, a first circuit layer, a second circuit layer, a conductive through hole, a capacitance dielectric layer, a dielectric layer and a rewiring circuit layer. The insulating layer has a first surface and a second surface opposite to the first surface. The first circuit layer is located on the first surface of the insulating layer. The first circuit layer includes a first capacitor electrode. The second circuit layer is located on the second surface of the insulating layer. The conductive through hole penetrates through the insulating layer to be electrically connected with the first circuit layer and the second circuit layer. The capacitance dielectric layer is positioned on the first capacitance electrode of the first circuit layer. The dielectric layer at least covers part of the first circuit layer and part of the capacitor dielectric layer. The redistribution layer includes a redistribution layer, a first conductive via, and a second capacitor electrode. The redistribution layer is disposed on the dielectric layer. The first conductive blind via is located in the dielectric layer and connects the first circuit layer and the redistribution circuit. The second capacitance electrode is located in the dielectric layer. The second capacitor electrode has a first end and a second end opposite to each other, the first end is in contact with the capacitor dielectric layer, and the second end is in contact with the redistribution trace. The second capacitor electrode, the capacitor dielectric layer and part of the first circuit layer form a capacitor.

In an embodiment of the invention, an orthographic projection of the first end on the first surface is smaller than an orthographic projection of the second end on the first surface.

In an embodiment of the invention, a sum of the thickness of the second capacitor electrode and the thickness of the capacitor dielectric layer is approximately equal to the thickness of the first conductive via.

In an embodiment of the invention, the second capacitor electrode has a sidewall connected to the first end and the second end, and the sidewall is an inclined surface.

In an embodiment of the invention, the circuit board structure further includes a plurality of second conductive vias and a plurality of third conductive vias. The second conductive through holes and the third conductive through holes are positioned in the insulating layer, and part of the first circuit layer and part of the second circuit layer penetrate through the insulating layer in a spiral mode to form the three-dimensional inductor.

In an embodiment of the invention, the circuit board structure further includes a plurality of conductive terminals. The conductive terminals are disposed on the redistribution layer and electrically connected to the redistribution layer.

The manufacturing method of the circuit board structure comprises the following steps. An insulating layer is provided. The insulating layer has a first surface and a second surface opposite to the first surface. Forming a first circuit layer, a second circuit layer and at least one conductive via. The first circuit layer is located on the first surface of the insulating layer and includes a first capacitor electrode. The second circuit layer is located on the second surface of the insulating layer. The conductive through hole penetrates through the insulating layer to be electrically connected with the first circuit layer and the second circuit layer. A capacitor dielectric layer is formed on the first circuit layer to cover a portion of the first circuit layer. A dielectric layer is formed on the first circuit layer and the capacitor dielectric layer. The dielectric layer has a first opening and a second opening, wherein the first opening exposes a portion of the first circuit layer, and the second opening exposes a portion of the capacitor dielectric layer. A redistribution layer is formed on the first wiring layer. The redistribution layer includes a redistribution layer, a first conductive via, and a second capacitor electrode. The redistribution traces are on the dielectric surface of the dielectric layer. The first conductive blind via is located in the first opening and connects the first circuit layer and the redistribution circuit. The second capacitor electrode is located in the second opening and contacts with the capacitor dielectric layer. The second capacitor electrode, the capacitor dielectric layer and the first capacitor electrode form a capacitor.

In an embodiment of the invention, the first conductive via and the second capacitor electrode are formed simultaneously by the same process.

In an embodiment of the invention, forming the redistribution layer includes the following steps. A patterned photoresist layer is formed on the dielectric layer and the first circuit layer to expose the first opening and the second opening. A conductive material is formed on the dielectric layer and the first circuit layer. The conductive material is filled in the first opening, the second opening and the patterned photoresist layer, wherein the part of the conductive material filled in the first opening forms a first conductive blind hole, and the part of the conductive material filled in the second opening forms a second capacitor electrode. The patterned photoresist layer is removed to form the redistribution traces.

In an embodiment of the invention, forming the redistribution layer includes the following steps. A conductive material is formed on the dielectric layer and the first circuit layer. The conductive material covers the dielectric surface of the dielectric layer and fills the first opening and the second opening, wherein a portion of the conductive material filled into the first opening forms the first conductive blind via, and a portion of the conductive material filled into the second opening forms the second capacitor electrode. Removing part of the conductive material covering the dielectric surface of the dielectric layer to form a redistribution circuit.

In an embodiment of the invention, the method for manufacturing the circuit board structure further includes the following steps. A plurality of conductive terminals are disposed on the redistribution layer. The conductive terminals are electrically connected with the redistribution circuit layer.

Based on the above, the present invention forms two electrodes of the embedded capacitor by the second capacitor electrode on part of the first circuit layer and the redistribution circuit layer. Therefore, in the manufacturing process of the circuit board structure with the embedded capacitor, the manufacturing process can be simplified, the manufacturing efficiency and the yield can be improved, and the manufacturing cost of the circuit board structure can be reduced. In addition, the capacitance of the capacitor can be further adjusted by adjusting the overlapping area of the second capacitor electrode and the first circuit layer. Therefore, the process of manufacturing the capacitor has a larger process desire.

In order to make the aforementioned and other features and advantages of the invention more comprehensible, embodiments accompanied with figures are described in detail below.

Drawings

Fig. 1A to fig. 1G are schematic cross-sectional views illustrating a manufacturing process of a circuit board structure according to a first embodiment of the invention.

Fig. 1H is an enlarged view of the region R in fig. 1G.

Fig. 1I is a schematic top view of the region R in fig. 1G.

Fig. 2 is a schematic top view of a portion of a circuit board structure according to a second embodiment of the invention.

Fig. 3 is a schematic top view of a portion of a circuit board structure according to a third embodiment of the invention.

Fig. 4A is a schematic top view of a portion of a circuit board structure according to a fourth embodiment of the invention.

Fig. 4B is a schematic sectional view taken along a line a-a' in fig. 4A.

Fig. 4C is a partial perspective view of a circuit board structure according to a fourth embodiment of the invention.

Description of the reference numerals

100. 200, 300, 400: a circuit board structure;

10: a capacitor;

20: an inductance;

20 a: a magnetic flux shaft;

110: a circuit substrate;

111: an insulating layer;

111 a: a first surface;

111 b: a second surface;

111 c: through holes are formed;

112: a first circuit layer;

112 a: a first capacitance electrode;

113: a second circuit layer;

114: a conductive via;

116: a conductive via;

118: a conductive via;

120: a capacitor dielectric layer;

130: a dielectric layer;

130 a: a dielectric surface;

131: a first opening;

132: a second opening;

141: a first conductive layer;

142: a second conductive layer;

150: re-routing the circuit layer;

151. 251: re-routing the circuit;

251 a: an edge;

152: a first conductive blind hole;

153. 353, and 2: a second capacitance electrode;

155: a side wall;

153a, 353 a: a first end;

153b, 353 b: a second end;

154: a connecting pad;

160: a protective layer;

170: plating;

171: a conductive terminal;

t1, T2, T3: thickness;

r: and (4) a region.

Detailed Description

The foregoing and other technical and scientific aspects, features and utilities of the present invention will be apparent from the following detailed description of various embodiments, which is to be read in connection with the accompanying drawings. Directional terms as referred to in the following examples, for example: "upper", "lower", "front", "rear", "left", "right", etc., are simply directions with reference to the attached drawings. Accordingly, the directional terminology is used for purposes of illustration and is in no way limiting. Also, in the following embodiments, the same or similar elements will be given the same or similar reference numerals.

Fig. 1A to fig. 1G are schematic cross-sectional views illustrating a manufacturing process of a circuit board structure according to an embodiment of the invention. Fig. 1H is an enlarged view of the region R in fig. 1G. Fig. 1I is a schematic top view of the region R in fig. 1G. For clarity, in fig. 1I, portions of the mold layers or members are omitted from illustration.

The method for manufacturing the circuit board structure 100 of the present embodiment includes the following steps. First, referring to fig. 1A, an insulating layer 111 is provided, wherein the insulating layer 111 includes a through hole (via) 111c, a first surface 111A and a second surface 111b, the first surface 111A and the second surface 111b are opposite to each other, and the via 111c penetrates through the insulating layer 111 to communicate the first surface 111A and the second surface 111 b. In this embodiment, the through hole 111c penetrating through the insulating layer 111 may be formed by, for example, mechanical drilling or laser drilling, but the embodiment is merely illustrative, and the forming manner of the through hole 111c is not limited in the present invention.

In the present embodiment, the insulating layer 111 may include a core layer, and the core layer may include a polymer glass fiber composite substrate, a glass substrate, a ceramic substrate, or a Polyimide (PI) glass fiber composite substrate, but the present invention is not limited thereto. In other embodiments, the insulating layer 111 may be a dielectric layer with a single layer or multiple layers of dielectric materials, or may be a single layer or multiple layers of circuit boards with an outer layer of dielectric materials and an inner layer embedded with circuits.

Next, referring to fig. 1B, a first circuit layer 112 may be formed on the first surface 111a of the insulating layer 111, and a second circuit layer 113 may be formed on the second surface 111B of the insulating layer 111. Specifically, the method for manufacturing the first circuit layer 112 and the second circuit layer 113 may include the following steps, for example. The conductive substance may be formed on the first surface 111a and the second surface 111b of the insulating layer 111 through a deposition process and/or a plating process or other suitable processes. Furthermore, the conductive material may further fill the through hole 111c of the insulating layer 111 and cover the sidewall of the through hole 111c to form a conductive through hole (conductive through hole)114 with conductive property. Subsequently, the conductive material covering the first surface 111a and the second surface 111b of the insulating layer 111 may be patterned by, for example, photolithography and etching processes to form the first circuit layer 112 and the second circuit layer 113, respectively. In the embodiment, the conductive material only covers the sidewall of the through hole 111c to form the hollow conductive via 114, but the invention is not limited thereto. In other embodiments, the conductive material may be filled in the through hole 111c to form a solid conductive via 114.

In the embodiment shown in fig. 1B, the number of the conductive vias 114 is one, but the invention is not limited thereto.

Next, with reference to fig. 1B, after the first circuit layer 112 is formed, a capacitor dielectric layer 120 may be formed on the first circuit layer 112, and the capacitor dielectric layer 120 covers a portion of the first circuit layer 112. The material of the capacitor dielectric layer 120 may include aluminum oxide (Al)₂O₃) Aluminum nitride (aluminum nitride; AlN), Silicon oxide (Silicon oxide; SiO 2₂) Silicon nitride (Silicon nitride; si₃N₄) Hafnium oxide (Hafnium dioxide; HfO₂) Zirconium oxide (Zirconium dioxide; ZrO (ZrO)₂) Lanthanum oxide (Lanthanum oxide; la₂O₃) Other similar metal oxide materials, metal nitride materials, or other suitable high-K materials.

Next, referring to fig. 1C, after the capacitor dielectric layer 120 is formed, a dielectric layer 130 is formed. The material of the dielectric layer 130 may include an organic material, a photosensitive dielectric material, a resin sheet (preprg), an inorganic material (e.g., silicon oxide, silicon nitride, silicon oxynitride, other suitable materials, or a stacked layer of at least two of the above materials), or other suitable dielectric materials. Taking an organic dielectric material as an example, the organic dielectric material may be formed on the first surface 111a and the second surface 111b of the insulating layer 111 by a coating method, a bonding method, a Sol-Gel method (Sol-Gel method), a pressing method, or other suitable processes, and then, may be cured by a photo-polymerization (photopolymerization) or baking (baking) process according to the properties of the organic dielectric material to form the dielectric layer 130. Taking inorganic dielectric materials as an example, the inorganic dielectric materials may be formed on the first surface 111a and the second surface 111b of the insulating layer 111 by a deposition process or other suitable processes, and the formed dielectric layer 130 may cover the first circuit layer 112, the capacitor dielectric layer 120 and the second circuit layer 113.

In the present embodiment, the dielectric constant of the capacitor dielectric layer 120 may be greater than the dielectric constant of the dielectric layer 130, so that the capacitor 10 (shown in fig. 1G) formed by the capacitor dielectric layer 120 with the above-mentioned materials has a better capacitance (capacitance), but the invention is not limited thereto.

Next, referring to fig. 1D, a plurality of

openings

131 and 132 are formed on the dielectric surface 130a of the dielectric layer 130. For example, the dielectric layer 130 may be formed of an organic material, and the

openings

131 and 132 may be formed by photolithography, etching, drilling, or other suitable processes. In another embodiment, taking the dielectric layer 130 formed of photosensitive dielectric material as an example, the

openings

131 and 132 may be formed by a photolithography process of exposure and development. In another embodiment, for example, the dielectric layer 130 formed of an inorganic material, the opening may be formed by photolithography and etching processes. As such, the sidewalls of the

openings

131, 132 may be substantially free of uneven contours. As shown in fig. 1D, in the present embodiment, the sidewalls of the

openings

131 and 132 may be a slope in a cross section perpendicular to the first surface 111a, but the invention is not limited thereto.

In this embodiment, the openings may include a first opening 131 and a second opening 132. The first opening 131 extends from the dielectric surface 130a of the dielectric layer 130 to the first circuit layer 112 to expose a portion of the first circuit layer 112. The second opening 132 extends from the dielectric surface 130a of the dielectric layer 130 to the capacitor dielectric layer 120 to expose a portion of the capacitor dielectric layer 120. In the present embodiment, the first opening 131 and the second opening 132 may be formed through a similar process. Taking the first opening 131 and the second opening 132 formed by the etching process as an example, the first opening 131 uses the first circuit layer 112 as an etching stop layer (etching stop layer), and the second opening 132 uses the capacitor dielectric layer 120 as an etching stop layer. Therefore, the manufacturing process can be simplified, and the manufacturing efficiency and yield can be improved. In fig. 1D, the number of the first openings 131 and/or the second openings 132 is one, but the invention is not limited thereto.

Next, referring to fig. 1E, a first conductive layer 141 may be selectively formed on the dielectric surface 130a of the dielectric layer 130 and in the

openings

131 and 132. In other words, the first conductive layer 141 is conformal (conformal) with the dielectric layer 130. In the present embodiment, the first conductive layer 141 is, for example, a seed layer (seed layer) formed by sputtering, and the common seed layer has a titanium layer and/or a copper layer, or an electroless copper layer formed by electroless plating. However, the actual material of the seed layer depends on the conductive material that will be subsequently filled into the first opening 131 and the second opening 132.

Next, referring to fig. 1F, a redistribution layer 150 is formed on the first circuit layer 112, and the redistribution layer 150 may include a redistribution trace 151, a first conductive blind via hole 152(conductive blind via hole), and a second capacitor electrode 153. Specifically, the redistribution layer 150 may be formed, for example, by a semi-additive method including the following steps. First, a patterned photoresist layer (not shown) may be formed on the first conductive layer 141 by a photolithography process, wherein the patterned photoresist layer exposes a portion of the first conductive layer 141, does not overlap the first opening 131 and the second opening 132, and exposes the first opening 131 and the second opening 132. Next, a patterned second conductive layer 142 made of a conductive material may be formed on the first conductive layer 141 exposed by the patterned photoresist layer by, for example, electroplating. The second conductive layer 142 covers at least a portion of the first conductive layer 141 exposed by the patterned photoresist layer, and the second conductive layer 142 further fills the first opening 131 (shown in fig. 1E) and the second opening 132 (shown in fig. 1E) to cover the first conductive layer 141 in the first opening 131 and the second opening 132, thereby forming a first conductive blind via 152 and a second capacitor electrode 153, respectively. Then, the photoresist layer may be removed by plasma ashing or etching, and the second conductive layer 142 is used as a mask to remove a portion of the first conductive layer 141 not covered by the second conductive layer 142, so as to form the redistribution traces 151 on the second trace layer 113.

In other embodiments, a redistribution layer may be formed on the second circuit layer 113 in a manner similar to that described above (e.g., deposition, photolithography, and etching processes using subtractive methods).

Specifically, the method for manufacturing the redistribution layer 150 may include the following steps. First, a second conductive layer 142 made of a conductive material is entirely formed on the first conductive layer 141 by, for example, electroplating. The second conductive layer 142 at least covers the first conductive layer 141, and the second conductive layer 142 further fills the first opening 131 (shown in fig. 1E) and the second opening 132 (shown in fig. 1E) to cover the first conductive layer 141 in the first opening 131 and the second opening 132, so as to form a first conductive via 152 and a second capacitive electrode 153, respectively. Then, a patterned photoresist layer (not shown) may be formed on the second conductive layer 142, and the exposed conductive material may be removed by an etching process or the like, that is, a portion of the second conductive layer 142 may be removed to form the redistribution trace 151. Finally, the patterned photoresist layer is removed by plasma ashing or etching. And, the second conductive layer 142 is used as a mask to remove a part of the first conductive layer 141 not covered by the second conductive layer 142.

In terms of structure, the first conductive layer 141 and the second conductive layer 142 filled in the first opening 131 (shown in fig. 1D) may form a first conductive via hole 152, the first conductive layer 141 and the second conductive layer 142 filled in the second opening 132 (shown in fig. 1D) may form a second capacitor electrode 153, and the first conductive via hole 152 and the second capacitor electrode 153 are electrically separated from each other. The remaining portions of the first conductive layer 141 and the second conductive layer 142 on the dielectric surface 130a of the dielectric layer 130 may form a redistribution trace 151, and the first conductive via 152 and the second capacitor electrode 153 may be electrically connected to other mold layers or members through the corresponding redistribution trace 151. In the present embodiment, the first conductive via hole 152 and the second capacitor electrode 153 can be formed by the same process. Therefore, the manufacturing process can be simplified to improve the manufacturing efficiency and yield, two patterning photomask processes are not needed, and the manufacturing cost can be reduced.

In addition, the first conductive via hole 152/the second capacitor electrode 153 are formed by filling conductive materials (e.g., the first conductive layer 141 and the second conductive layer 142) into the first opening 131/the second opening 132. Therefore, the shapes of the first conductive blind via 152/the second capacitive electrode 153 substantially conform to the shapes of the corresponding first opening 131/the second opening 132. For example, the sidewall 155 of the first conductive via 152/the second capacitive electrode 153 may be a substantially non-concave surface. In the present embodiment, the sidewall 155 of the first conductive via 152/the second capacitor electrode 153 may be an inclined surface on a cross section perpendicular to the first surface 111a, but the invention is not limited thereto.

In addition, in the process of forming the second capacitor electrode 153, the capacitor dielectric layer 120 is used as an etching stop layer, and the second capacitor electrode 153 is formed by filling conductive materials (e.g., the first conductive layer 141 and the second conductive layer 142) into the second opening 132. Therefore, as shown in FIG. 1I, on the first surface 111a (e.g., the paper surface of FIG. 1I), the projected area of the second capacitor electrode 153 on the first surface 111a is smaller than the projected area of the capacitor dielectric layer 120 on the first surface 111a, and the projected area of the capacitor dielectric layer 120 on the first surface 111a is smaller than the projected area of the first circuit layer 112 on the first surface 111 a. Also, the first end 153a of the second capacitor electrode 153 in contact with the capacitor dielectric layer 120 has a smaller orthographic projection on the first surface 111a than the second end 153b of the second capacitor electrode 153 in contact with the redistribution trace 151.

For circuit, the second capacitor electrode 153, the capacitor dielectric layer 120 and the portion of the first circuit layer 112 overlapped with the second capacitor electrode 153/the capacitor dielectric layer 120 may form a capacitor 10. Generally, the capacitance of the capacitor 10 is related to the overlapping area of two capacitor electrodes (e.g., the second capacitor electrode 153 and the first capacitor electrode 112a) constituting the capacitor 10. As shown in FIG. 1I, in the present embodiment, a projected area of the second capacitor electrode 153 on the first surface 111a (e.g., the paper surface of FIG. 1I) is smaller than a projected area of the first circuit layer 112 on the first surface 111 a. Therefore, the capacitance of the capacitor 10 can be further adjusted by adjusting the opening area of the second opening 132 (shown in fig. 1D) to adjust the overlapping area of the second capacitor electrode 153 and the first circuit layer 112. Thus, the process window has a larger process window in the manufacturing process of the capacitor 10 with a specific capacitance.

Next, referring to fig. 1G, after forming the redistribution layer 150, a protection layer 160 may be formed on the first surface 111a and/or the second surface 111b, and the protection layer 160 may expose a portion of the redistribution layer 151 to define a connection pad 154. The passivation layer 160 may be a solder mask (solder mask) or a dry film (dry film), but the present invention is not limited thereto. The connecting pads 154 may have conductive terminals 171 thereon, so that the redistribution layer 150 is electrically connected to other layers or components through the corresponding conductive terminals 171. In addition, in some embodiments, the bonding pads 154 may further have a plating layer 170 plated with a metal layer or an alloy layer of nickel, palladium, gold, etc. to improve the bonding force between the bonding pads 154 and other films or components.

The fabrication of the semiconductor package structure of the present embodiment can be substantially completed through the above processes. Referring to fig. 1G and fig. 1H, structurally, the circuit board structure 100 of the present embodiment includes a circuit substrate 110, a capacitor dielectric layer 120, a dielectric layer 130, and a redistribution layer 150. The circuit substrate 110 includes an insulating layer 111, a first circuit layer 112, a second circuit layer 113, and at least one conductive via 114. The insulating layer 111 has a first surface 111a and a second surface 111b opposite to the first surface 111 a. The first circuit layer 112 is located on the first surface 111a of the insulating layer 111. The second wiring layer 113 is located on the second surface 111b of the insulating layer 111. The conductive via 114 penetrates the insulating layer 111 to electrically connect the first circuit layer 112 and the second circuit layer 113. The capacitor dielectric layer 120 is disposed on the first circuit layer 112 of the circuit substrate 110. The dielectric layer 130 covers a portion of the first circuit layer 112 and a portion of the capacitor dielectric layer 120. The redistribution layer 150 includes a redistribution trace 151, a first conductive via 152, and a second capacitor electrode 153. The redistribution traces 151 are located on the dielectric layer 130. The first conductive via 152 is embedded in the dielectric layer 130 and connected to the first circuit layer 112. The second capacitor electrode 153 is embedded in the dielectric layer 130, wherein the second capacitor electrode 153 has a first end 153a and a second end 153b opposite to each other, the first end 153a is in contact with the capacitor dielectric layer 120, and the second end 153b is in contact with the redistribution trace 151. The second capacitor electrode 153, the capacitor dielectric layer 120 and a portion of the first circuit layer 112 form a capacitor 10.

Since one of the electrodes forming the capacitor 10 may be a part of the first circuit layer 112, and the second capacitor electrode 153 forming the other electrode of the capacitor 10 may be formed in the same manner and/or in the same step as the other via holes (e.g., the first conductive via hole 152) on the redistribution circuit layer 150. Therefore, it is technically possible to form the two electrodes constituting the capacitor 10 together in the step of forming other mold layers/members (e.g., forming the first wiring layer 112 or other blind holes on the redistribution wiring layer 150). Thus, the manufacturing process can be simplified to improve the manufacturing efficiency and yield, and the manufacturing cost of the circuit board structure 100 can be reduced.

In the present embodiment, the first conductive via hole 152 and the second capacitor electrode 153 are formed in the same manner, and the capacitance of the capacitor 10 can be adjusted by adjusting the size of the second capacitor electrode 153. Therefore, the manufacturing process can be simplified, and the manufacturing efficiency and yield can be improved. In addition, by the above formation, the sum of the thickness T1 of the second capacitor electrode 153 and the thickness T2 of the capacitor dielectric layer 120 can be approximately equal to the thickness T3 of the first conductive via 152.

In the present embodiment, the insulating layer 111 may be a core layer, and the material of the core layer may be different from the material of the capacitor dielectric layer 120 and/or the dielectric layer 130. The material of the core layer may include polymer glass fiber composite, glass substrate, ceramic substrate, Polyimide (PI) glass fiber composite substrate, or other similar hard dielectric materials. Stated differently, the circuit board structure 100 of the present embodiment may be a core (core) circuit board structure having a core layer, but the invention is not limited thereto. In other embodiments, the material of the insulating layer 111 is the same as or similar to the material of the dielectric layer 130, i.e., the insulating layer 111 may be a common dielectric layer, and thus the circuit board structure 100 may be a coreless (core) circuit board structure, for example, by forming the above-mentioned capacitor 10 and/or other stacked layers on two opposite surfaces of the carrier, and then removing the carrier to form two independent coreless circuit board structures 100.

Fig. 2 is a schematic top view of a portion of a circuit board structure according to a second embodiment of the invention. Specifically, fig. 2 may be a schematic top view of a region R similar to that in fig. 1G. The circuit board structure 200 of the present embodiment is similar to the circuit board structure 100 of the previous embodiment, and the main differences between the circuit board structure 200 and the circuit board structure 100 are as follows: the projected shape of the edge 251a of the redistribution trace 251 on the second capacitive electrode 153 on the first surface 111a (e.g., the paper surface of fig. 2) may have a similar and corresponding projected shape of the first end 153a and/or the second end 153 b.

Fig. 3 is a schematic top view of a portion of a circuit board structure according to a third embodiment of the invention. Specifically, fig. 3 may be a schematic top view of a region R similar to that in fig. 1G. The circuit board structure 300 of the present embodiment is similar to the circuit board structure 100 of the previous embodiment, and the main differences between the circuit board structure 300 and the circuit board structure 100 are: on the first surface 111a (e.g., the paper surface of fig. 3), the projected shape of the first end 353a and/or the second end 353b of the second capacitive electrode 353 may have a shape similar to the projected shape of the capacitive dielectric layer 120, and the projected areas of the first end 353a and the second end 353b are smaller than the projected area of the capacitive dielectric layer 120.

In the present embodiment, the projection shape of the first end 353a, the projection shape of the second end 353b, and the projection shape of the capacitive dielectric layer 120 on the first surface 111a (e.g., the paper surface of fig. 3) may be similar to a quadrilateral, but the present invention is not limited thereto.

Fig. 4A is a schematic top view of a portion of a circuit board structure according to a fourth embodiment of the invention. Fig. 4B is a schematic sectional view taken along a line a-a' in fig. 4A. Fig. 4C is a partial perspective view of a circuit board structure according to a fourth embodiment of the invention. Specifically, fig. 4C is a partial perspective view of one of the solid inductors in a circuit board structure according to a fourth embodiment of the present invention. In addition, in fig. 4A, a part of the mold layer or member is omitted for clarity.

The circuit board structure 400 of the present embodiment is similar to the circuit board structure 100 of the previous embodiment, and the main differences between the circuit board structure 400 and the circuit board structure 100 are: the circuit board structure 400 may further have a three-dimensional inductor 20.

Please refer to fig. 4A to fig. 4C. In detail, in the present embodiment, a plurality of conductive vias 116 and a plurality of conductive vias 118 are further included, and as shown in fig. 4A and/or fig. 4C, the first circuit layer 112, the conductive vias 116, the conductive vias 118, and the second circuit layer 113 may form the three-dimensional inductor 20 with a conductive coil. Stated differently, the conductive coil of the three-dimensional inductor 20 is in the form of a spiral that extends through the insulating layer 111. In this way, the direction of the magnetic flux axis 20a of the inductor 20 can be parallel to the first surface 111a (i.e., the paper surface in fig. 4A).

Therefore, passive components with different properties (such as the capacitor 10 and the inductor 20) can be embedded and integrated in the circuit board structure 400, and the volume of the circuit board structure 400 can be reduced.

In summary, the second capacitor electrode on part of the first circuit layer and the redistribution circuit layer form two electrodes of the embedded capacitor. Therefore, in the manufacturing process of the circuit board structure with the embedded capacitor, the manufacturing process can be simplified, the manufacturing efficiency and the yield can be improved, and the manufacturing cost of the circuit board structure can be reduced. In addition, the capacitance of the capacitor can be further adjusted by adjusting the overlapping area of the second capacitor electrode and the first circuit layer. Therefore, the manufacturing process of the capacitor has larger process tolerance.

Although the present invention has been described with reference to the above embodiments, it should be understood that the invention is not limited to the embodiments, and various changes and modifications can be made by those skilled in the art without departing from the spirit and scope of the invention.

Claims

1. A manufacturing method of a circuit board structure is characterized by comprising the following steps:

providing an insulating layer having a first surface and a second surface opposite to the first surface;

forming a first circuit layer on the first surface of the insulating layer, the first circuit layer including a first capacitor electrode, a second circuit layer on the second surface of the insulating layer, and at least one conductive via penetrating the insulating layer to electrically connect the first circuit layer and the second circuit layer;

forming a capacitance dielectric layer on the first circuit layer to cover a part of the first capacitance electrode;

forming a dielectric layer on the first circuit layer and the capacitor dielectric layer, the dielectric layer having a first opening and a second opening, wherein the first opening exposes a portion of the first circuit layer and the second opening exposes a portion of the capacitor dielectric layer; and

form the rewired circuit layer on the first circuit layer, the rewired circuit layer includes rewired circuit, first electrically conductive blind hole and second capacitance electrode, the rewired circuit is located on the dielectric surface of dielectric layer, first electrically conductive blind hole is located in first opening and connect first circuit layer with the rewired circuit, second capacitance electrode is located in the second opening and with the capacitance dielectric layer contacts, just second capacitance electrode the capacitance dielectric layer and first capacitance electrode constitutes electric capacity.

2. The method of claim 1, wherein the first conductive via and the second capacitive electrode are formed simultaneously by a same process.

3. The method of fabricating a circuit board structure according to claim 1, wherein the step of forming said redistribution circuit layer comprises:

forming a patterned photoresist layer on the dielectric layer and the first circuit layer to expose the first opening and the second opening;

forming a conductive material on the dielectric layer and the first circuit layer, wherein the conductive material fills the first opening, the second opening and the patterned photoresist layer, wherein a portion of the conductive material filling the first opening forms the first conductive blind via, and a portion of the conductive material filling the second opening forms the second capacitor electrode; and

and removing the patterned photoresist layer to form the redistribution circuit.

4. The method of fabricating a circuit board structure according to claim 1, wherein the step of forming said redistribution circuit layer comprises:

forming a conductive material on the dielectric layer and the first circuit layer, wherein the conductive material covers the dielectric surface of the dielectric layer and fills the first opening and the second opening, wherein the conductive material filled into the first opening forms the first conductive blind via, and the conductive material filled into the second opening forms the second capacitor electrode; and

removing a portion of the conductive material overlying the dielectric surface of the dielectric layer to form the redistribution trace.

5. The method of making a circuit board structure of claim 1, further comprising:

and arranging a plurality of conductive terminals on the rewiring circuit layer, wherein the conductive terminals are electrically connected with the rewiring circuit layer.

6. A circuit board structure, comprising:

the insulating layer is provided with a first surface and a second surface opposite to the first surface;

a first circuit layer on the first surface of the insulating layer, the first circuit layer including a first capacitor electrode;

a second circuit layer on the second surface of the insulating layer;

a first conductive via penetrating the insulating layer to electrically connect the first circuit layer and the second circuit layer;

a capacitor dielectric layer on the first capacitor electrode of the first circuit layer;

a dielectric layer at least covering a portion of the first circuit layer and at least covering a portion of the capacitor dielectric layer; and

the rewiring circuit layer comprises a rewiring circuit, a first conductive blind hole and a second capacitor electrode, wherein the rewiring circuit is located on the dielectric layer, the first conductive blind hole is located in the dielectric layer and connected with the first circuit layer and the rewiring circuit, the second capacitor electrode is located in the dielectric layer, the second capacitor electrode is provided with a first end and a second end which are opposite to each other, the first end is in contact with the capacitor dielectric layer, the second end is in contact with the rewiring circuit, the second capacitor electrode, the capacitor dielectric layer and the first capacitor electrode form a capacitor, and the first conductive blind hole and the second capacitor electrode are the same film layer formed by the same process at the same time.

7. The circuit board structure of claim 6, wherein an orthographic projection of the first end on the first surface is smaller than an orthographic projection of the second end on the first surface.

8. The circuit board structure of claim 6, wherein the sum of the thickness of said second capacitive electrode and the thickness of said capacitive dielectric layer is equal to the thickness of said first conductive blind via.

9. The circuit board structure of claim 6, wherein said second capacitor electrode has a sidewall connected to said first end and said second end, and said sidewall is a bevel.

10. The circuit board structure of claim 6, further comprising a plurality of second conductive vias and a plurality of third conductive vias in the insulating layer, wherein a portion of the first circuit layer, a portion of the second circuit layer, the plurality of second conductive vias and the plurality of third conductive vias penetrate the insulating layer in a spiral manner to form a three-dimensional inductor.

11. The wiring board structure of claim 6, further comprising:

and the conductive terminals are configured on the redistribution circuit layer and are electrically connected with the redistribution circuit layer.