CN110060961B - 一种晶圆封装器件 - Google Patents
一种晶圆封装器件 Download PDFInfo
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- CN110060961B CN110060961B CN201810055269.8A CN201810055269A CN110060961B CN 110060961 B CN110060961 B CN 110060961B CN 201810055269 A CN201810055269 A CN 201810055269A CN 110060961 B CN110060961 B CN 110060961B
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Abstract
一种晶圆封装器件,所述晶圆封装器件包括晶圆,以及相对设置的第一基板和第二基板,其中所述晶圆设置于所述第一基板朝向所述第二基板的表面;所述晶圆和所述第一基板通过第一导电部件形成电气连接;所述第一基板和所述第二基板通过第二导电部件形成电气连接;所述晶圆和所述第二基板通过导热层形成散热通路。所述晶圆封装器件还包括塑封件,用于包裹所述晶圆。设置于晶圆和第二基板之间的导热层能够将晶圆产生的大量热量快速散出至第二基板,使晶圆维持正常温度。
Description
技术领域
本发明涉及电子及通信技术领域,尤其涉及一种晶圆封装器件。
背景技术
如图1所示,一种现有的晶圆封装器件100包括相对设置的上层基板101和下层基板102,以及设置在上层基板101朝向所述下层基板102的表面的晶圆103,所述上层基板101和所述下层基板102之间填充有塑封材料104,以增加整个封装结构的支撑强度。所述上层基板101和下层基板102之间通过内嵌式球栅阵列105形成电气连接。随着晶圆103的功率的增加,晶圆103在运行过程中产生的热量也越来越多。当晶圆103产生的热量累积而不能快速散出,其内部的温度会过高,影响晶圆103的工作性能和使用寿命。
发明内容
本发明的目的在于提供一种具有较高散热效率的晶圆封装器件,以实现将晶圆产生的热量通过导热层以较高效率散出。
第一方面,本发明的实施例提供一种晶圆封装器件。所述晶圆封装器件包括:
晶圆,塑封件,导热层,以及相对设置的第一基板和第二基板,其中所述晶圆设置于所述第一基板朝向所述第二基板的表面;所述晶圆与所述第一基板之间通过第一导电部件电气连接,所述第二基板与所述第一基板之间通过第二导电部件电气连接;
所述导热层设置于所述晶圆和所述第二基板之间,所述导热层用于形成所述晶圆和所述第二基板之间的散热通路;
所述塑封件,用于包裹所述晶圆。
在一个可能的设计中,所述导热层为导热胶。
在一个可能的设计中,所述导热层包括:第一导热层和第二导热层,其中,所述第一导热层设置于所述晶圆朝向所述第二基板的表面,所述第二导热层设置于所述第一导热层朝向所述第二基板的表面。
在一个可能的设计中,所述第一导热层为金属层,所述第二导热层为导热胶。
在一个可能的设计中,所述第一导热层为金属层,所述第二导热层为锡膏。
在一个可能的设计中,所述第一导热层为导热胶,所述第二导热层为多个金属柱,其中所述多个金属柱呈离散的阵列分布。
在一个可能的设计中,所述晶圆产生的热量较多的区域对应的所述金属柱的密度大于所述晶圆产生的热量较少的区域对应的所述金属柱的密度。
在一个可能的设计中,所述塑封件还用于包裹所述第一导热层以及所述第二导热层的靠近所述第一导热层的部分。
在一个可能的设计中,所述导热层包括多个金属柱,其中所述多个金属柱呈离散的阵列分布。
在一个可能的设计中,所述晶圆产生的热量较多的区域对应的所述金属柱的密度大于所述晶圆产生的热量的较少的区域对应的所述金属柱的密度。
在一个可能的设计中,所述第一导电部件包括多个金属球。
在一个可能的设计中,所述塑封件还用于包裹所述多个金属球。
在一个可能的设计中,所述第一导电部件包括:多个金属球和多个金属柱,其中所述金属柱设置于所述晶圆朝向第一基板的表面,所述金属球设置于所述金属柱靠近所述第一基板的一端,用于电气连接所述金属柱和所述第一基板。
在一个可能的设计中,所述塑封件还用于包裹所述第一导电部件的所述多个金属柱。
在一个可能的设计中,所述第二导电部件为多个金属球。
在一个可能的设计中,所述第二导电部件为多个金属柱。
在一个可能的设计中,所述塑封件还用于包裹所述第二导电部件靠近第一基板的部分。
在一个可能的设计中,所述第二导电部件包括:
多个第一金属球、多个金属柱和多个第二金属球,其中所述第一金属球设置于所述第一基板朝向所述第二基板的表面,所述第二金属球设置于所述第二基板的朝向所述第一基板的表面,所述金属柱设置于所述第一金属球和第二金属球之间,用于电气连接第一所述第一金属球和第二金属球。
在一个可能的设计中,所述塑封件还用于包裹所述第二导电部件的所述多个金属柱的靠近所述第一基板的部分。
本发明提供的一种晶圆封装器件,通过设置于晶圆和第二基板之间的导热层,形成晶圆和第二基板之间的散热通路,使晶圆在正常工作时产生的大量热量能够通过导热层散出至第二基板,维持晶圆正常的工作温度,提高晶圆的使用寿命。
附图说明
下面将参照所示附图对本发明实施例进行更详细的描述:
图1为现有技术中的一种晶圆封装器件;
图2为本发明实施例提供的一种晶圆封装器件;
图3为本发明实施例提供的另一种晶圆封装器件;
图4为本发明实施例提供的又一种晶圆封装器件;
图5为本发明实施例提供的一种晶圆的热量分布图;
图6为本发明实施例提供的再一种晶圆封装器件;
图7为本发明实施例提供的再一种晶圆封装器件;
图8为本发明实施例提供的再一种晶圆封装器件;
图9为本发明实施例提供的再一种晶圆封装器件;
附图标记说明:21-晶圆,22-第一基板,23-第二基板,24-第一导电部件,25-第二导电部件,26-导热层。
具体实施方式
如图2所示,本发明的实施例提供一种晶圆封装器件200,其中晶圆封装器件200包括:晶圆21,导热层26,塑封件以及相对设置的第一基板22和第二基板23。晶圆21设置在第一基板22的朝向第二基板23的表面,晶圆21与第一基板22之间通过第一导电部件24电气连接。第二基板23与第一基板22之间通过第二导电部件25电气连接。晶圆21与第二基板23之间设置所述导热层26,导热层26用于将晶圆21产生的热量通过第二基板23散出。所述塑封件用于包裹所述晶圆21。
在本发明的上述实施例中,通过在晶圆21与第二基板23之间设置导热层26,从而在晶圆21与第二基板23之间提供了一条散热通道,降低晶圆21在正常工作时的温度,有利于延长晶圆21的使用寿命,保持晶圆21的工作性能。
此外,第二基板23内部设置有多个垂直方向的金属导热线231和多个水平方向的金属导热线232。金属导热线231和金属导热线232可以相互交叉,以形成多条散热通路。晶圆21产生的热量通过导热层26传输至第二基板23时,通过多个金属导热线231和多个金属导热线232形成的多个互通的散热通道传输至外部环境,避免第二基板23内部的温度过高,影响热量散出。
具体来讲,导热层26可以为导热胶,导热胶一般具有较高的热导率。晶圆21产生的热量通过导热胶传输至第二基板23。
如图3所示的一种晶圆封装器件200,在导热层26的另一种实现方式中,导热层26可以包括第一导热层261,以及覆盖于第一导热层261的一侧表面的第二导热层262。第一导热层261可以为金属层,材质为具有较好导热性能的金、银或其他金属,金属层能够将晶圆21产生的热量以较高的效率导出。第二导热层262可以为导热胶,或界面热阻更低的锡膏,以起到更好的散热作用,并形成第一导热层261和第二基板23之间的物理连接。
如图4所示的一种晶圆封装器件400,在第一导热层261和第二导热层262的另一种实现方式中,第一导热层261可以为导热胶,第二导热层262可以包括多个金属柱,其中金属柱的材质可以为铜,或其他导热性能较好的金属,如金或银。金属柱与第二基板23之间可以通过焊接的方式实现物理连接,并建立导热路径。
第二导热层262中的多个金属柱可以呈离散的阵列分布,例如呈矩形的阵列分布。第二导热层262中的多个金属柱将第一导热层261散出的热量传输至第二基板23。将第二导热层262设置成离散的阵列分布可以提高第二导热层262中的多个金属柱与第二基板23的焊接良率,使第二导热层262的厚度更加均匀,区域焊接更加良好,从而使区域热量能更快速地散出。
晶圆21在正常工作时,不同区域产生的热量并非均匀分布。如图5所示的是晶圆21在正常工作时产生的热量分布图,在长度相等的时间段内,边缘区域510产生较少的热量,而中心区域520则产生较多的热量。因此,第二导热层262中的多个金属柱的分布情况可以按照芯片产生的热量的分布来设置。例如:在芯片产生热量较多的区域(例如:中心区域520),对应的第二导热层262中的多个金属柱的分布密度较大,在芯片产生热量较少的区域(例如:边缘区域510),对应的第二导热层262中的多个金属柱的分布密度较小,从而,更有利于提高晶圆21的热量散出的效率。
如图6所示的一种晶圆封装器件200,在第二导热层262的另外一种实现方式中,第二导热层262中的多个金属柱可以呈图形化分布,将第一导热层261散出的热量传输至第二基板23,其中晶圆产生的热量较多的区域对应的所述金属柱的密度大于所述晶圆产生的热量的较少的区域对应的所述金属柱的密度。具体来说,第二导热层262中的多个金属柱可以按照如图5所示的晶圆21的热量分布图来设置多个金属柱所在的位置,其中,靠近晶圆21中心区域的金属柱分布密度较大,远离晶圆21中心区域的金属柱分布密度较小。分布密度较大的金属柱可以将晶圆21产生的热量以更高的效率传递至第二基板23,使晶圆21在发热集中区域的热量能够更好散出。
如图7所示的一种晶圆封装器件200,在导热层26的另外一种实现方式中,导热层26还可以包括多个金属柱,将晶圆21散出的热量传输至第二基板23。其中,导热层26中的多个金属柱可以呈离散的阵列分布,例如呈矩形的阵列分布,以提高导热层26的焊接良率,避免了连续导热层产生的厚度不均匀、部分区域焊接不良的问题,使区域热量能够快速地散出。导热层26的多个金属柱与第二基板23接触的一端通过焊锡与第二基板23连接,以提供更好的焊接强度。导热层26中的多个金属柱还可以呈图形化分布,将导热层26散出的热量传输至第二基板23,其中晶圆产生的热量较多的区域对应的所述金属柱的密度大于所述晶圆产生的热量的较少的区域对应的所述金属柱的密度。具体来说,导热层26中的多个金属柱可以按照如图5所示的晶圆21的热量分布图来设置多个金属柱所在的位置,其中,靠近晶圆21中心区域的金属柱分布密度较大,远离晶圆21中心区域的金属柱分布密度较小。分布密度较大的金属柱可以将晶圆21产生的热量以更高的效率传递至第二基板23,使晶圆21在发热集中区域的热量能够更好散出。在晶圆封装器件200的实施例中,第一基板22与晶圆21可以通过连接在晶圆21与第一基板22之间的多个第一导电部件24实现电气连接。如图8所示的一种晶圆封装器件200,在第一导电部件24的一种实现方式中,第一导电部件24可以为多个金属球。金属球可以设置于第一基板22表面,具体设置的方式可以为:多个金属球可以呈离散的阵列分布,例如呈矩形的阵列分布,以使得晶圆21和第一基板22之间的电信号能够更好地导通。金属球可以为锡球。
如图8所示的一种晶圆封装器件200,在第一导电部件的另外一种实现方式中,多个第一导电部件24包括多个金属球241和多个金属柱242。其中,金属柱242的一端与晶圆21连接,另一端与金属球241连接;金属球241连接在第一基板22与金属柱242之间。金属球241与金属柱242均设置于第一基板22表面,具体设置的方式可以为:多个金属球241和多个金属柱242可以呈离散的阵列分布,例如呈矩形的阵列分布,以使得晶圆21和第一基板22之间的电信号能够更好地导通。金属球241可以为锡球。
在晶圆封装器件200的实施例中,具体来讲,第一基板22与第二基板23通过第二导电部件24实现电气连接。在第二导电部件的一种实现方式中,第二导电部件25可以为金属球,例如锡球,或其他具有高电导率的金属焊球,以将第一基板22中的电信号通过第二导电部件25传递至第二基板23。在第二导电部件25的另外一种实现方式中,第二导电部件25可以为金属柱,例如铜柱,或其他具有高电导率的金属柱。
如图8所示的一种晶圆封装器件200,在第二导电部件25的另外一种实现方式中,第二导电部件25可以为第一金属球251、多个金属柱252和多个第二金属球253。其中,第一金属球251设置于第一基板22朝向第二基板23的表面,第二金属球253设置于第二基板23朝向第一基板22的表面,金属柱252的一端与第一金属球251连接,另一端与第二金属球253连接。第一金属球251、金属柱252和第二金属球253形成第一基板22和第二基板23之间的电气连接通路。第一金属球251和第二金属球253可以为锡球。金属柱252的材质可以为铜,或者其他导电性能较好的金属。
在本发明的上述实施例中,具体来讲,晶圆封装器件200还可以包括塑封件28,塑封件28设置于第一基板22和第二基板23之间。
具体来讲,如图3所示的一种晶圆封装器件300,其中塑封件28可以用于包裹晶圆21、第一导电部件24、以及第二导电部件25的靠近第一基板22的部分。其中,晶圆21朝向第二基板23的表面裸露于塑封件28之外,用于和导热层26连接以将晶圆21的热量散出;第二导电部件25的靠近第二基板的部分裸露于塑封件28之外。
如图9所示的一种晶圆封装器件200,在塑封件28的另外一种实现方式中,塑封件28还可以用于包裹晶圆21、第一导电部件24、第二导电部件25的靠近第一基板22的部分、第一导热层261、以及第二导热层262的靠近晶圆21的部分。其中,第二导电部件25的靠近第二基板23的部分裸露于塑封件28之外;第二导热层262的靠近第二基板23的部分裸露于塑封件28之外。
如图8所示的一种晶圆封装器件200,在塑封件28的另外一种实现方式中,塑封件28还可以用于包裹晶圆21、第一导电部件24的金属柱242、以及第二导电部件25的金属柱252。
以上的具体实施例,对本发明的目的、技术方案和有益效果进行了进一步的详细说明。此外,以上仅为本发明的具体实施例而已,并不用于限制本发明,凡在本发明的精神和原则之内,所做的任何修改、等同替换、改进等,均应包含在本发明的保护范围之内。
Claims (1)
1.一种芯片封装器件,其特征在于,包括:
芯片,导热层,第一导电部件,第二导电部件,塑封件,以及相对设置的第一基板和第二基板;其中,
所述芯片设置于所述第一基板朝向所述第二基板的表面;所述芯片与所述第一基板之间通过所述第一导电部件电气连接,所述第二基板与所述第一基板之间通过所述第二导电部件电气连接,所述导热层设置于所述芯片和所述第二基板之间;
所述第一导电部件包括:多个第一金属球和多个第一金属柱,其中所述多个第一金属柱分别设置于所述芯片和所述多个第一金属球之间;
所述第二导电部件包括:多个第二金属球、多个第二金属柱和多个第三金属球,其中所述多个第二金属球设置于所述第一基板朝向所述第二基板的表面,所述多个第三金属球设置于所述第二基板的朝向所述第一基板的表面,所述多个第二金属柱分别设置于所述多个第二金属球和所述多个第三金属球之间;
所述塑封件包裹所述芯片、所述第二导电部件中的所述多个第二金属柱,以及所述第一导电部件中的多个第一金属柱;
所述导热层包括多个第三金属柱,其中所述多个第三金属柱呈离散的阵列分布。
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US7049695B1 (en) * | 2005-01-14 | 2006-05-23 | International Business Machines Corporation | Method and device for heat dissipation in semiconductor modules |
CN100539126C (zh) * | 2007-05-18 | 2009-09-09 | 日月光半导体制造股份有限公司 | 芯片堆叠结构以及可制成芯片堆叠结构的晶片结构 |
US7675465B2 (en) * | 2007-05-22 | 2010-03-09 | Sibeam, Inc. | Surface mountable integrated circuit packaging scheme |
US20120126396A1 (en) * | 2010-11-19 | 2012-05-24 | Broadcom Corporation | Die down device with thermal connector |
US20140151880A1 (en) * | 2011-08-19 | 2014-06-05 | Marvell World Trade Ltd. | Package-on-package structures |
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US9418971B2 (en) * | 2012-11-08 | 2016-08-16 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package-on-package structure including a thermal isolation material and method of forming the same |
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