CN110047804B - Array substrate, manufacturing method, display panel and spliced screen - Google Patents
Array substrate, manufacturing method, display panel and spliced screen Download PDFInfo
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- CN110047804B CN110047804B CN201910362292.6A CN201910362292A CN110047804B CN 110047804 B CN110047804 B CN 110047804B CN 201910362292 A CN201910362292 A CN 201910362292A CN 110047804 B CN110047804 B CN 110047804B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
- H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
Abstract
The invention relates to the technical field of display, and provides an array substrate, a manufacturing method, a display panel and a spliced screen, wherein the manufacturing method of the array substrate comprises the following steps: forming a substrate, wherein the substrate comprises a substrate main body, a first binding terminal group positioned on the front surface of the substrate main body and a second binding terminal group positioned on the back surface of the substrate main body; forming a photoresist layer on the front surface, the back surface and the side surface between the front surface and the back surface of the substrate main body; exposing the photoresist layer to light so that the photoresist layer forms a lead pattern that can not be dissolved by a developing solution; forming a first conductive layer on the photoresist layer, and developing the photoresist layer to form a first lead group with the same lead pattern as the lead pattern; and forming a second lead group to connect the first lead group with the first binding terminal group and the second binding terminal group. The array substrate manufacturing method can reduce the reject ratio of the first lead group and can reduce the lead line width and the distance between adjacent leads.
Description
Technical Field
The invention relates to the technical field of display, in particular to an array substrate, a manufacturing method of the array substrate, a display panel and a spliced screen.
Background
The display panel generally includes a display area and a bezel area surrounding the display area. The display panel with the narrow frame can bring a good visual effect to a user, and especially in the application of the spliced screen, the display panel with the narrow frame can reduce gaps between the spliced screens. In the prior art, a bonding region for bonding a driver chip in an array substrate is disposed on a back surface (a surface opposite to a display side) of the array substrate to reduce a frame size of a display panel.
In the related art, the binding terminal group of the array substrate is generally located on the front side (display side) of the array substrate, and therefore, a new binding terminal group needs to be disposed on the back side of the array substrate, and the binding terminal group located on the front side of the array substrate and the binding terminal group located on the back side of the array substrate are connected through the lead group. In the related art, the lead connecting the two binding terminal groups is formed at the edge of the array substrate by methods such as ink-jet printing and screen printing.
However, the edge of the array substrate is close to a right angle and has sharp burrs, which easily causes wire breakage, and further, due to the limitation of the accuracy of inkjet printing and screen printing, the pitch and the line width of the wires are large, which limits the resolution of the screen.
It is to be noted that the information invented in the above background section is only for enhancing the understanding of the background of the present invention, and therefore, may include information that does not constitute prior art known to those of ordinary skill in the art.
Disclosure of Invention
The invention aims to provide an array substrate, a manufacturing method of the array substrate, a display panel and a spliced screen.
Additional features and advantages of the invention will be set forth in the detailed description which follows, or may be learned by practice of the invention.
According to an aspect of the present disclosure, there is provided a method for fabricating an array substrate, the method including:
forming a substrate, wherein the substrate comprises a substrate main body, a first binding terminal group positioned on the front surface of the substrate main body and a second binding terminal group positioned on the back surface of the substrate main body;
forming photoresist layers on the front surface and the back surface of the substrate main body and on the side surface between the front surface and the back surface so as to connect the first binding terminal group and the second binding terminal group;
exposing a preset position of the photoresist layer to enable the photoresist layer to form a lead pattern which can not be dissolved by a developing solution;
forming a first conductive layer on the photoresist layer, and developing the photoresist layer to form the first conductive layer into a first lead group having the same pattern as the lead pattern;
and forming a second lead group to connect the first lead group with the first binding terminal group and the second binding terminal group.
In an exemplary embodiment of the present disclosure, the substrate main body includes a base substrate, and before forming a photoresist layer on a front surface, a back surface, and a side surface between the front surface and the back surface of the substrate main body, the method further includes:
and passivating the edges and corners of the side surfaces of the substrate base plate.
In an exemplary embodiment of the present disclosure, before forming a photoresist layer on the front surface, the back surface, and the side surface between the front surface and the back surface of the substrate main body, the method further includes:
and carrying out burr passivation treatment on the side surface of the substrate base plate.
In an exemplary embodiment of the present disclosure, forming a photoresist layer on a front surface, a back surface, and a side surface between the front surface and the back surface of the substrate main body includes:
a photoresist layer is formed on the front surface, the back surface, and a side surface between the front surface and the back surface of the substrate main body through a coating process.
In one exemplary embodiment of the present disclosure, forming the second lead group includes:
the second lead group is formed by an inkjet printing technique.
In an exemplary embodiment of the present disclosure, the photoresist layer is a positive photoresist or a negative photoresist.
According to an aspect of the present disclosure, there is provided an array substrate including: the device comprises a substrate, a photoresist layer, a first lead group and a second lead group. The substrate comprises a substrate main body, a first binding terminal group positioned on the front surface of the substrate main body and a second binding terminal group positioned on the back surface of the substrate main body; the photoresist layer is formed on the front surface, the back surface and the side surface between the front surface and the back surface of the substrate main body and is used for connecting the first binding terminal group and the second binding terminal group; the first lead group is arranged on the photoresist layer; the second lead group is connected between the first lead group and the first binding terminal group and between the first lead group and the second binding terminal group.
In an exemplary embodiment of the present disclosure, the base plate body further includes a base plate, and corners of the side surfaces of the base plate are rounded.
In an exemplary embodiment of the present disclosure, the photoresist layer is a positive photoresist or a negative photoresist.
According to an aspect of the present disclosure, a display panel is provided, which includes the array substrate.
According to an aspect of the present disclosure, a tiled screen is provided, which includes the above-mentioned display panel.
The disclosure provides an array substrate, a manufacturing method, a display panel and a spliced screen, wherein the method comprises the following steps: forming a substrate, wherein the substrate comprises a substrate main body, a first binding terminal group positioned on the front surface of the substrate main body and a second binding terminal group positioned on the back surface of the substrate main body; forming photoresist layers on the front surface and the back surface of the substrate main body and on the side surface between the front surface and the back surface so as to connect the first binding terminal group and the second binding terminal group; exposing a preset position of the photoresist layer to enable the photoresist layer to form a lead pattern which can not be dissolved by a developing solution; forming a first conductive layer on the photoresist layer, and developing the photoresist layer to form the first conductive layer into a first lead group having the same pattern as the lead pattern; and forming a second lead group to connect the first lead group with the first binding terminal group and the second binding terminal group. On one hand, according to the array substrate manufacturing method provided by the disclosure, the first lead is arranged on the photoresist layer, and the photoresist layer has planarization and passivation effects on the front surface, the back surface and the side surfaces of the array substrate, so that the fracture risk of the first lead group caused by edge corners and burrs of the array substrate is reduced; on the other hand, the first leads are formed by the photoetching technology of the photoresist layer, the width of the first leads and the distance between the adjacent first leads can be reduced, and therefore the limitation of the first lead group on the resolution of the array substrate is reduced.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention. It is obvious that the drawings in the following description are only some embodiments of the invention, and that for a person skilled in the art, other drawings can be derived from them without inventive effort.
Fig. 1 is a flowchart of an exemplary embodiment of a method for manufacturing an array substrate according to the present disclosure;
fig. 2 to 16 are schematic structural diagrams of a manufacturing process in an exemplary embodiment of a manufacturing method of an array substrate according to the present disclosure.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted.
Although relative terms, such as "upper" and "lower," may be used in this specification to describe one element of an icon relative to another, these terms are used in this specification for convenience only, e.g., in accordance with the orientation of the examples described in the figures. It will be appreciated that if the device of the icon were turned upside down, the element described as "upper" would become the element "lower". Other relative terms, such as "high," "low," "top," "bottom," "left," "right," and the like are also intended to have similar meanings. When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via another structure.
The terms "a," "an," "the," and "the" are used to indicate the presence of one or more elements/components/parts/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc.
The present exemplary embodiment provides a method for manufacturing an array substrate, as shown in fig. 1, which is a flowchart of an exemplary embodiment of a method for manufacturing an array substrate according to the present disclosure, the method including:
step S1: forming a substrate, wherein the substrate comprises a substrate main body, a first binding terminal group positioned on the front surface of the substrate main body and a second binding terminal group positioned on the back surface of the substrate main body;
step S2: forming photoresist layers on the front surface and the back surface of the substrate main body and on the side surface between the front surface and the back surface so as to connect the first binding terminal group and the second binding terminal group;
step S3: exposing a preset position of the photoresist layer to enable the photoresist layer to form a lead pattern which can not be dissolved by a developing solution;
step S4: forming a first conductive layer on the photoresist layer, and developing the photoresist layer to form the first conductive layer into a first lead group having the same pattern as the lead pattern;
step S5: and forming a second lead group to connect the first lead group with the first binding terminal group and the second binding terminal group.
The front surface of the substrate main body can be one surface of the display side of the array substrate, and the back surface of the substrate main body can be one surface of the array substrate opposite to the display side.
The present disclosure provides an array substrate and a manufacturing method thereof, the method includes: forming a substrate, wherein the substrate comprises a substrate main body, a first binding terminal group positioned on the front surface of the substrate main body and a second binding terminal group positioned on the back surface of the substrate main body; forming photoresist layers on the front surface and the back surface of the substrate main body and on the side surface between the front surface and the back surface so as to connect the first binding terminal group and the second binding terminal group; exposing a preset position of the photoresist layer to enable the photoresist layer to form a lead pattern which can not be dissolved by a developing solution; forming a first conductive layer on the photoresist layer, and developing the photoresist layer to form the first conductive layer into a first lead group having the same pattern as the lead pattern; and forming a second lead group to connect the first lead group with the first binding terminal group and the second binding terminal group. On one hand, according to the array substrate manufacturing method provided by the disclosure, the first lead is arranged on the photoresist layer, and the photoresist layer has planarization and passivation effects on the front surface, the back surface and the side surfaces of the array substrate, so that the fracture risk of the first lead group caused by edge corners and burrs of the array substrate is reduced; on the other hand, the first leads are formed by the photoetching technology of the photoresist layer, the width of the first leads and the distance between the adjacent first leads can be reduced, and therefore the limitation of the first lead group on the resolution of the array substrate is reduced.
The above steps are explained in detail below:
fig. 2 to 16 are schematic structural diagrams illustrating a manufacturing process in an exemplary embodiment of a method for manufacturing an array substrate according to the present disclosure. Fig. 2, 4, 5, 10 and 15 are side views of an array substrate in an exemplary embodiment of a method for manufacturing an array substrate according to the present disclosure, and fig. 3, 6, 8, 11 and 13 are front views of an array substrate in an exemplary embodiment of a method for manufacturing an array substrate according to the present disclosure; FIG. 7 is a cross-sectional view taken along line A-A of FIG. 6; FIG. 9 is a cross-sectional view taken along line A-A of FIG. 8; FIG. 12 is a sectional view taken along the line A-A in FIG. 11; fig. 14 is a sectional view taken along the line a-a in fig. 13.
Step S1: forming a substrate, wherein the substrate comprises a substrate main body, a first binding terminal group positioned on the front surface of the substrate main body and a second binding terminal group positioned on the back surface of the substrate main body. As shown in fig. 2 and 3, the array substrate may include: the circuit board comprises a substrate body 1, a first binding terminal group positioned on the front surface of the substrate body and a second binding terminal group positioned on the back surface of the substrate body. Wherein the first binding terminal group may include a plurality of first binding terminals 2, and the second binding terminal group may include a plurality of second binding terminals 3; the substrate main body 1 may include a base substrate 12 and a functional layer 11, and the functional layer 11 may be any one of pixel driving circuit layers; the first binding terminal 2 may be located at one side of the functional layer 11 for connecting with a signal terminal in the pixel driving circuit layer; the second binding terminal 3 may be located at one side of the substrate base plate 12 for connection with a driving chip, which may be a source driving chip, a gate driving chip, or the like. It should be understood that the base plate body may have other structures, for example, the base plate body may only include a substrate base plate, and the first binding terminal group and the second binding terminal group are respectively disposed on two sides of the substrate base plate.
As shown in fig. 4, in the present exemplary embodiment, before forming the photoresist layer on the front surface, the back surface, and the side surface between the front surface and the back surface of the substrate main body, the method may further include: and passivating the edge and corner of the side surface of the substrate base plate to form a fillet, so that the risk of breaking the first lead group is further reduced. In this exemplary embodiment, before forming the photoresist layer on the front surface, the back surface, and the side surface between the front surface and the back surface of the substrate main body, the method may further include: the side face of the substrate base plate is subjected to burr passivation treatment, and the arrangement can also reduce the risk of breakage of the first lead group.
Step S2: and forming photoresist layers on the front surface and the back surface of the substrate main body and the side surface between the front surface and the back surface so as to connect the first binding terminal group and the second binding terminal group. As shown in fig. 5, 6, and 7, a photoresist layer 4 may be formed on the front surface, the rear surface, and the side surface between the front surface and the rear surface of the substrate main body. Wherein, forming the photoresist layer may include: the photoresist layer 4 is formed by a coating process. The photoresist layer 4 may be formed, for example, by immersing the substrate main body in a photoresist solution, and the photoresist layer may be formed, for example, by spraying.
Step S3: and exposing the preset position of the photoresist layer to form a lead pattern which can not be dissolved by a developing solution on the photoresist layer. As shown in fig. 8 and 9, the photoresist layer 4 may be exposed to light to form a lead pattern 41 that is insoluble to a developing solution. The photoresist layer may be either a positive photoresist layer or a negative photoresist layer. When the photoresist is a positive photoresist, the lead pattern 41 is an unexposed portion, and when the photoresist is a negative photoresist, the lead pattern 41 is an exposed portion.
Step S4: and forming a first conductive layer on the photoresist layer, and developing the photoresist layer to form the first conductive layer into a first lead group having the same pattern as the lead pattern. As shown in fig. 10, 11 and 12, the step S4 may include forming the first conductive layer 5 on the photoresist layer 4, as shown in fig. 13 and 14, and the step S4 may further include developing the photoresist layer 4, wherein the photoresist layer 4 is dissolved by the developing solution, and the portions of the photoresist layer 4 other than the lead patterns 41 are dissolved, and the first conductive layer 5 other than the lead patterns 41 is also dissolved, as shown in fig. 14, so that the first conductive layer 5 may be formed into a first lead group having the same pattern as the lead patterns 41, and the first lead group includes a plurality of first leads 51.
Step S5: and forming a second lead group to connect the first lead group with the first binding terminal group and the second binding terminal group. As shown in fig. 15 and 16, step S5 may include forming a second lead group to connect the first lead group with the first and second binding terminal groups. The second lead group includes a plurality of second leads 6. Wherein forming the second lead group may include: the second lead group is formed by an inkjet printing technique. In other exemplary embodiments, forming the second lead group may further include: the second lead group is formed by evaporation, ink jet printing and other technologies.
In addition, the manufacturing method of the array substrate can further comprise the step of packaging the first lead group and the second lead group so as to avoid oxidation of the first lead group and the second lead group. Another function is to prevent the exposed leads from shorting to other metals.
The present exemplary embodiment also provides an array substrate, including: the device comprises a substrate, a photoresist layer, a first lead group and a second lead group. The substrate comprises a substrate main body, a first binding terminal group positioned on the front surface of the substrate main body and a second binding terminal group positioned on the back surface of the substrate main body; the photoresist layer is formed on the front surface, the back surface and the side surface between the front surface and the back surface of the substrate main body and is used for connecting the first binding terminal group and the second binding terminal group; the first lead group is arranged on the photoresist layer; the second lead group is connected between the first lead group and the first binding terminal group and between the first lead group and the second binding terminal group.
In this exemplary embodiment, the base plate main body further includes a base plate, and corners of the side surfaces of the base plate are rounded.
In the present exemplary embodiment, the photoresist layer is a positive photoresist or a negative photoresist.
The array substrate provided by the present exemplary embodiment has the same technical features and working principles as the above-mentioned array substrate manufacturing method, and the above-mentioned contents have been described in detail and are not described again here.
The present exemplary embodiment also provides a display panel including the array substrate described above. The display panel can be different types of display panels such as OLED, LCD, LED, etc.
The display panel provided by the present exemplary embodiment has the same technical features and working principles as the array substrate, and the above contents have been described in detail and are not repeated herein.
The exemplary embodiment also provides a tiled screen including the display panel described above.
The mosaic screen provided by the present exemplary embodiment has the same technical features and working principles as those of the display panel, and the details of the above description are already given, and are not repeated herein.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
It will be understood that the present disclosure is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is to be limited only by the terms of the appended claims.
Claims (10)
1. An array substrate manufacturing method, the method comprising:
forming a substrate, wherein the substrate comprises a substrate main body, a first binding terminal group positioned on the front surface of the substrate main body and a second binding terminal group positioned on the back surface of the substrate main body;
forming photoresist layers on the front surface and the back surface of the substrate main body and on the side surface between the front surface and the back surface so as to connect the first binding terminal group and the second binding terminal group;
exposing a preset position of the photoresist layer to enable the photoresist layer to form a lead pattern which can not be dissolved by a developing solution, wherein the lead pattern is connected between the first binding terminal group and the second binding terminal group;
forming a first conductive layer on the photoresist layer, and developing the photoresist layer to form the first conductive layer into a first lead group having the same pattern as the lead pattern;
and forming a second lead group on the lead pattern to connect the first lead group with the first binding terminal group and the second binding terminal group.
2. The method for manufacturing the array substrate according to claim 1, wherein the substrate main body comprises a substrate base, and before forming the photoresist layer on the front surface, the back surface, and the side surface between the front surface and the back surface of the substrate main body, the method further comprises:
and passivating the edges and corners of the side surfaces of the substrate base plate.
3. The method for manufacturing an array substrate according to claim 2, further comprising, before forming a photoresist layer on the front surface, the back surface, and the side surface between the front surface and the back surface of the substrate main body:
and carrying out burr passivation treatment on the side surface of the substrate base plate.
4. The method for manufacturing an array substrate according to claim 1, wherein forming a photoresist layer on the front surface, the back surface, and the side surface between the front surface and the back surface of the substrate main body comprises:
a photoresist layer is formed on the front surface, the back surface, and a side surface between the front surface and the back surface of the substrate main body through a coating process.
5. The method of claim 1, wherein forming a second lead group comprises:
the second lead group is formed by an inkjet printing technique.
6. The method for manufacturing the array substrate according to claim 1, wherein the photoresist layer is a positive photoresist or a negative photoresist.
7. An array substrate, comprising:
the substrate comprises a substrate main body, a first binding terminal group positioned on the front surface of the substrate main body and a second binding terminal group positioned on the back surface of the substrate main body;
the photoresist layer is formed on the front surface, the back surface and the side surface between the front surface and the back surface of the substrate main body, a lead pattern which can not be dissolved by a developing solution is formed on the photoresist layer, and the lead pattern is connected between the first binding terminal group and the second binding terminal group;
a first lead group disposed on the lead pattern;
and the second lead group is arranged on the lead pattern and is connected among the first lead group, the first binding terminal group and the second binding terminal group.
8. The array substrate of claim 7, wherein the substrate body further comprises a substrate base, and wherein corners of the sides of the substrate base are rounded.
9. A display panel comprising the array substrate according to any one of claims 1 to 8.
10. A tiled screen comprising the display panel of claim 9.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910362292.6A CN110047804B (en) | 2019-04-30 | 2019-04-30 | Array substrate, manufacturing method, display panel and spliced screen |
| PCT/CN2020/076364 WO2020220805A1 (en) | 2019-04-30 | 2020-02-24 | Array substrate and fabrication method, display panel and splicing screen |
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| CN201910362292.6A CN110047804B (en) | 2019-04-30 | 2019-04-30 | Array substrate, manufacturing method, display panel and spliced screen |
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| CN110047804B true CN110047804B (en) | 2021-08-03 |
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| CN110047804B (en) * | 2019-04-30 | 2021-08-03 | 京东方科技集团股份有限公司 | Array substrate, manufacturing method, display panel and spliced screen |
| CN110931513A (en) * | 2019-11-27 | 2020-03-27 | 深圳市华星光电半导体显示技术有限公司 | Display panel and display device |
| CN113644085B (en) | 2020-08-14 | 2023-06-02 | 友达光电股份有限公司 | Electronic device and method for manufacturing electronic device |
| CN114822248A (en) * | 2022-04-06 | 2022-07-29 | Tcl华星光电技术有限公司 | Display panel and manufacturing method thereof |
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