WO2020220805A1 - Array substrate and fabrication method, display panel and splicing screen - Google Patents

Array substrate and fabrication method, display panel and splicing screen Download PDF

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Publication number
WO2020220805A1
WO2020220805A1 PCT/CN2020/076364 CN2020076364W WO2020220805A1 WO 2020220805 A1 WO2020220805 A1 WO 2020220805A1 CN 2020076364 W CN2020076364 W CN 2020076364W WO 2020220805 A1 WO2020220805 A1 WO 2020220805A1
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Prior art keywords
lead
group
orthographic projection
substrate
binding terminal
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PCT/CN2020/076364
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French (fr)
Chinese (zh)
Inventor
史鲁斌
孙双
周婷婷
牛菁
王锦谦
张方振
陈小海
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京东方科技集团股份有限公司
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Publication of WO2020220805A1 publication Critical patent/WO2020220805A1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods
    • H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Definitions

  • the present invention relates to the field of display technology, in particular to an array substrate and a manufacturing method, a display panel, and a splicing screen.
  • the display panel generally includes a display area and a border area surrounding the display area.
  • a display panel with a narrow frame can bring better visual effects to users, especially in splicing screen applications, a narrow frame display panel can reduce the gap between splicing screens.
  • the bonding area for bonding the driving chip in the array substrate is arranged on the back of the array substrate (the side opposite to the display side) to reduce the frame size of the display panel.
  • the bonding terminal group of the array substrate is generally located on the front side (display side) of the array substrate, so it is necessary to set a new bonding terminal group on the back of the array substrate, and connect the bonding located on the front side of the array substrate through the lead group.
  • the terminal group and the binding terminal group on the back of the array substrate are mainly used to form leads connecting the two bound terminal groups on the edge of the array substrate.
  • the edge of the array substrate is close to a right angle and there are sharp burrs, which easily lead to wire breakage.
  • the lead spacing and line width are large, which limits the resolution of the screen. rate.
  • the purpose of the present invention is to provide an array substrate and a manufacturing method, a display panel, and a splicing screen.
  • the manufacturing method of the array substrate can solve the problem that the lead is easily broken and the lead spacing and line width are large in the related technology, which limits the screen resolution. technical problem.
  • a manufacturing method of an array substrate including:
  • a substrate includes a substrate body, the substrate body includes a first surface, a second surface, and side surfaces adjacent to the first surface and the second surface, and the first surface of the substrate body includes The first binding terminal group, the second surface of the substrate body includes a second binding terminal group corresponding to the first binding terminal group, and the orthographic projection of the first binding terminal group on the first surface and The orthographic projections of the second binding terminal group on the first surface coincide;
  • a first conductive layer is formed on the photoresist layer, and the photoresist layer is developed to form a first lead group.
  • the orthographic projection of the first lead group on the first surface is located at the The lead pattern is in the orthographic projection on the first surface, and the orthographic projection of the first lead group on the second surface is in the orthographic projection of the lead pattern on the second surface;
  • a second lead group is formed for connecting the first lead group and the first binding terminal group and connecting the first lead group and the second binding terminal group.
  • the orthographic projection of the lead pattern on the plane where the side surface is located is within the orthographic projection of the first lead group on the plane where the side surface is located.
  • the substrate body includes a base substrate, a photoresist layer is formed on the first surface, the second surface, and the side surface of the substrate body, and Methods also include:
  • the method before forming a photoresist layer on the first surface, the second surface, and the side surface of the substrate body, the method further includes:
  • Burr passivation is performed on the side surface of the base substrate.
  • forming a photoresist layer on the first surface, the second surface, and the side surface of the substrate body includes:
  • a photoresist layer is formed on the first surface, the second surface and the side surface of the substrate body through a coating process.
  • forming the second lead group includes:
  • the second lead group is formed by inkjet printing technology.
  • the photoresist layer is a positive photoresist or a negative photoresist.
  • an array substrate including: a substrate including a substrate main body, the substrate main body including a first surface, a second surface, and the first surface and the second surface Adjacent side surfaces, the first surface of the substrate main body includes a first binding terminal group, the second surface of the substrate main body includes a second binding terminal group, and the first binding terminal group is in the first The orthographic projection of a surface coincides with the orthographic projection of the second binding terminal group on the first surface;
  • a first lead group, the orthographic projection of the first lead group on the first surface is within the orthographic projection of the lead pattern on the first surface, and the first lead group is on the second surface
  • the orthographic projection on the second surface is within the orthographic projection of the lead pattern on the second surface
  • the second lead group is used for connecting the first lead group and the first binding terminal group and connecting the first lead group and the second binding terminal group.
  • the orthographic projection of the lead pattern on the plane where the side surface is located is within the orthographic projection of the first lead group on the plane where the side surface is located.
  • the orthographic projection of the second lead group on the first surface and the orthographic projection of the first binding terminal group on the first surface and the The orthographic projection of the first lead group on the first surface at least partially overlaps, and the orthographic projection of the second lead group on the second surface and the second binding terminal group on the second surface The orthographic projection of and the orthographic projection of the first lead group on the second surface at least partially overlap.
  • the substrate body further includes a base substrate, and the corners of the side surface of the base substrate are rounded corners.
  • the first bonding terminal group is connected to a signal terminal in the pixel driving circuit layer, and the second bonding terminal group is connected to a driving chip.
  • the first lead is arranged on the photoresist layer, and the photoresist layer has a flattening and passivation effect on the front, back and side surfaces of the array substrate, thereby reducing the first lead.
  • the lead set is at risk of breaking due to the edges and burrs of the array substrate.
  • the first lead is formed by photolithography on the photoresist layer, which can reduce the width of the first lead and the distance between adjacent first leads. The distance, thereby reducing the limitation on the resolution of the array substrate by the first lead group.
  • FIG. 1 is a flowchart of an exemplary embodiment of a manufacturing method of an array substrate of the present disclosure
  • FIG. 2 is a schematic diagram of a partial structure of an array substrate in an exemplary embodiment of the present disclosure
  • FIG. 3 is a side view of an array substrate in an exemplary embodiment of the present disclosure
  • FIG. 4 is a schematic diagram of a partial structure of an array substrate in an exemplary embodiment of the present disclosure
  • FIG. 5 is a schematic diagram of a partial structure of an array substrate in an exemplary embodiment of the present disclosure
  • Fig. 6 is a side view of an array substrate in an exemplary embodiment of the present disclosure.
  • Figure 7 is a cross-sectional view in the direction of A-A in Figure 6;
  • FIG. 8 is a side view of an array substrate in an exemplary embodiment of the present disclosure.
  • Figure 9 is a cross-sectional view in the direction of A-A in Figure 8.
  • FIG. 10 is a schematic diagram of a partial structure of an array substrate in an exemplary embodiment of the present disclosure.
  • FIG. 11 is a side view of an array substrate in an exemplary embodiment of the present disclosure.
  • Figure 12 is a cross-sectional view in the direction of A-A in Figure 11;
  • FIG. 13 is a side view of an array substrate in an exemplary embodiment of the present disclosure.
  • Figure 14 is a cross-sectional view in the direction of A-A in Figure 13;
  • 15 is a schematic diagram of a partial structure of an array substrate in an exemplary embodiment of the present disclosure.
  • FIG. 16 is a side view of an array substrate in an exemplary embodiment of the present disclosure.
  • FIG. 17 is a top view of an array substrate in an exemplary embodiment of the present disclosure.
  • This exemplary embodiment provides a method for manufacturing an array substrate. As shown in FIG. 1, it is a flowchart of an exemplary embodiment of the method for manufacturing an array substrate of the present disclosure. The method includes:
  • Step S1 Provide a substrate, the substrate includes a substrate main body, the substrate main body includes a first surface, a second surface, and side surfaces adjacent to the first surface and the second surface, and the first surface of the substrate main body
  • One surface includes a first binding terminal group
  • the second surface of the substrate body includes a second binding terminal group corresponding to the first binding terminal group
  • the first binding terminal group is located on the first surface
  • the orthographic projection coincides with the orthographic projection of the second binding terminal group on the first surface;
  • Step S2 forming a photoresist layer on the first surface, the second surface and the side surface of the substrate body;
  • Step S3 Expose the photoresist layer to form a lead pattern that can not be dissolved by the developer
  • Step S4 forming a first conductive layer on the photoresist layer, and developing the photoresist layer to form a first lead group, the first lead group being located on the first surface
  • the projection is located in the orthographic projection of the lead pattern on the first surface
  • the orthographic projection of the first lead group on the second surface is located in the orthographic projection of the lead pattern on the second surface ;
  • Step S5 forming a second lead group for connecting the first lead group and the first binding terminal group and connecting the first lead group and the second binding terminal group.
  • the first surface of the substrate body may be, for example, the front surface of the substrate body, that is, the display side of the array substrate
  • the second surface of the substrate body may be, for example, the back surface of the substrate body, that is, the array The side of the substrate opposite to the display side.
  • the side surface of the substrate body may be the side surface adjacent to the front surface and the back surface.
  • the first lead is disposed on the photoresist layer, and the photoresist layer has a flattening and passivation effect on the front, back and sides of the array substrate, thereby reducing
  • the first lead group is at risk of breaking due to the edges and burrs of the array substrate;
  • the first lead is formed by photolithography on the photoresist layer, which can reduce the width of the first lead and the distance between adjacent first leads. Therefore, the limitation of the first lead group on the resolution of the array substrate is reduced.
  • FIGS. 2 to 16 they are schematic structural diagrams of the manufacturing process in an exemplary embodiment of the manufacturing method of the array substrate of the present disclosure.
  • Figures 2, 4, 5, 10, 15 are partial structural diagrams of the array substrate in an exemplary embodiment of the disclosed array substrate manufacturing method
  • Figures 3, 6, 8, 11, 13 are the disclosed array substrate manufacturing method
  • a side view of the array substrate in an exemplary embodiment FIG. 7 is a cross-sectional view in the AA direction in FIG. 6
  • FIG. 9 is a cross-sectional view in the AA direction in FIG. 8
  • FIG. 12 is a cross-sectional view in the AA direction in FIG. 11; Section 13 in the direction of AA.
  • Step S1 forming a substrate, the substrate includes a substrate main body, the substrate main body includes a first surface (for example, the front U1 of the substrate main body), a second surface (for example, the back B1 of the substrate main body) and the first surface and the The side surface adjacent to the second surface (for example, the side surface L1 connecting the front surface U1 and the back surface B1).
  • the array substrate may include a substrate body 1, a first surface U1 of the substrate body includes a first binding terminal group, and a second surface B1 of the substrate body includes a first binding terminal group corresponding to the first binding terminal group.
  • the first binding terminal group may include a plurality of first binding terminals 2, and the second binding terminal group may include a plurality of second binding terminals 3.
  • the plurality of first binding terminals 2 may be arranged in parallel with each other at intervals, and the plurality of second binding terminals 3 may be arranged in parallel with each other at intervals.
  • the orthographic projection of the first binding terminal group on the first surface U1 coincides with the orthographic projection of the second binding terminal group on the first surface U1.
  • the substrate body 1 may include a base substrate 12 and a functional layer 11.
  • the functional layer 11 may be any layer of the pixel driving circuit layer; the plurality of first binding terminals 2 may be located on the functional layer One side of 11 is used to connect to the signal terminal in the pixel driving circuit layer; the plurality of second binding terminals 3 may be located on one side of the base substrate 12 and used to connect to the driving chip.
  • the driving chip may be a source driving chip, a gate driving chip, and so on.
  • the material of the base substrate 12 may be any of glass, quartz, silicon, plastic, polyimide, polymethyl methacrylate, etc., and the thickness of the base substrate 12 may be about 0.5 mm.
  • the substrate main body may also have other structures.
  • the substrate main body may only include a base substrate, and the first binding terminal group and the second binding terminal group are respectively disposed on both sides of the base substrate.
  • the method may further include: The edges and corners of the side surface of the substrate are passivated to round the edges and corners of the side surface of the base substrate, thereby further reducing the risk of the first lead group breaking.
  • the method may further include: burring the side surface of the base substrate ⁇ . This can also reduce the risk of breakage of the first lead group.
  • Step S2 forming a photoresist layer on the first surface, the second surface and the side surface of the substrate body.
  • a photoresist layer 4 may be formed on the first surface U1, the second surface B1, and the side surface L1 of the substrate body.
  • forming the photoresist layer may include: forming the photoresist layer 4 through a coating process.
  • the main body of the substrate can be immersed in a photoresist solution to form the photoresist layer 4, and for another example, the photoresist layer can be formed by spraying.
  • Step S3 Expose the photoresist layer to form a lead pattern that can not be dissolved by the developer.
  • the photoresist layer 4 may be exposed to light so that the photoresist layer can form a lead pattern 41 that can not be dissolved by the developer.
  • the photoresist layer can be a positive photoresist layer or a negative photoresist layer.
  • the lead pattern 41 is an unexposed part
  • the photoresist is a negative photoresist
  • Step S4 forming a first conductive layer on the photoresist layer, and developing the photoresist layer to form a first lead group, the first lead group being located on the first surface
  • the projection is located in the orthographic projection of the lead pattern on the first surface
  • the orthographic projection of the first lead group on the second surface is located in the orthographic projection of the lead pattern on the second surface .
  • step S4 may include forming a first conductive layer 5 on the photoresist layer 4.
  • step S4 may also include a step on the photoresist layer 4.
  • the part of the photoresist layer 4 outside the lead pattern 41 is dissolved by the developer, and the first conductive layer 5 outside the lead pattern 41 is also dissolved, as shown in FIG. 14, so that the first The conductive layer 5 forms a first lead group with the same pattern as the lead pattern 41, and the first lead group includes a plurality of first leads 51.
  • the first lead group is formed.
  • the orthographic projection of the conductive layer 5 on the first surface U1 is located within the orthographic projection of the photoresist layer 4 on the first surface U1; the orthographic projection of the first conductive layer 5 on the second surface B1 is located on the photoresist layer 4 In the orthographic projection on the second surface B1.
  • the width of the first conductive layer 5 in the direction along the first surface U1 pointing to the second surface B1 on the plane of the side surface L1 must be greater than that of the photoresist layer 4 on the plane of the side surface L1 pointing to the second surface along the first surface U1
  • the width in the direction of B1; the width of the first conductive layer 5 on the plane of the side L1 along the direction perpendicular to the first surface U1 to the second surface B1 is less than or equal to the width of the photoresist layer 4 on the plane of the side L1
  • the width along the direction perpendicular to the first surface U1 to the second surface B1 is as shown in FIG. 11.
  • the embodiments of the present disclosure are not limited to this, and the size of the first conductive layer 5 in the direction perpendicular to the first surface U1 to the second surface B1 on the plane where the side surface L1 is located may also be equal to the size of the photoresist layer 4 in this direction. size of.
  • the orthographic projection of the first lead group on the first surface U1 is within the orthographic projection of the lead pattern 41 on the first surface U1, and the orthographic projection of the first lead group on the second surface B1 The projection is located within the orthographic projection of the lead pattern 41 on the second surface B1.
  • the orthographic projection of the lead pattern 41 on the plane where the side face L1 is located is within the orthographic projection of the first lead group on the plane where the side face L1 is located. It can be understood that the width of the first lead group in the direction along the first surface U1 pointing to the second surface B1 on the plane where the side surface L1 is located must be greater than that of the lead pattern 41 on the plane where the side surface L1 is directed to the second surface along the first surface U1.
  • the width in the direction of the two surfaces B1; the width of the first lead group on the plane where the side surface L1 is located in the direction perpendicular to the first surface U1 to the second surface B1 is less than or equal to the edge of the lead pattern 41 on the plane where the side surface L1 is located
  • Step S5 forming a second lead group for connecting the first lead group and the first binding terminal group and connecting the first lead group and the second binding terminal group.
  • step S5 may include forming a second lead group to connect the first lead group and the first binding terminal group and to connect the first lead group and the second binding terminal group.
  • the second lead group includes a plurality of second leads 6, which may be arranged in parallel with each other at intervals.
  • FIG. 17 is a top view of the formed array substrate.
  • the orthographic projection of the second lead group on the first surface U1 and the orthographic projection of the first binding terminal group on the first surface U1 and the first lead group on the first surface U1 The orthographic projection of at least partially overlaps, the orthographic projection of the second lead group on the second surface B1 and the orthographic projection of the second binding terminal group on the second surface of B1 and the orthographic projection of the first lead group on the second surface B1 At least partially overlap.
  • the connection between the first lead group and the first binding terminal group can be realized by the multiple second leads 6 in the second lead group, and the first lead group can be realized by the multiple cases 6 of the second lead group. Connection with the second binding terminal group.
  • forming the second lead group may include: forming the second lead group by inkjet printing technology.
  • forming the second lead group may further include: forming the second lead group by techniques such as evaporation and inkjet printing.
  • the manufacturing method of the array substrate may further include packaging the first lead group and the second lead group to avoid oxidation of the first lead group and the second lead group. Another function is to avoid short circuits between exposed leads and other metals.
  • the exemplary embodiment also provides an array substrate, the array substrate includes: a substrate, including a substrate main body, the substrate main body includes a first surface, a second surface and the first surface and the second surface. Adjacent to the side surface, the first surface of the substrate body includes a first binding terminal group, and the second surface of the substrate body includes a second binding terminal group, and the first binding terminal group is in the first The orthographic projection of the surface coincides with the orthographic projection of the second binding terminal group on the first surface; the lead pattern covers part of the surface of the first binding terminal group and part of the second binding terminal group Surface and part of the surface of the side surface; a first lead group, the orthographic projection of the first lead group on the first surface is located within the orthographic projection of the lead pattern on the first surface, the first The orthographic projection of a lead group on the second surface is located within the orthographic projection of the lead pattern on the second surface; a second lead group is used to connect the first lead group and the first binding The terminal group is fixed and the first lead group and the second binding terminal
  • the substrate body further includes a base substrate, and the corners of the side surface of the base substrate are rounded corners.
  • the photoresist layer is a positive photoresist or a negative photoresist.
  • the orthographic projection of the lead pattern on the plane where the side surface is located is within the orthographic projection of the first lead group on the plane where the side surface is located. It can be understood that the width of the first lead group on the plane of the side surface along the first surface pointing to the second surface must be larger than the width of the lead pattern on the plane of the side surface along the first surface pointing to the second surface. Width; the width of the first lead group on the plane of the side surface along the direction perpendicular to the first surface to the second surface is less than or equal to the width of the lead pattern on the plane of the side surface along the direction perpendicular to the first surface to the second surface Width,
  • the orthographic projection of the second lead group on the first surface and the orthographic projection of the first binding terminal group on the first surface and the first lead group on the The orthographic projection on the first surface at least partially overlaps, the orthographic projection of the second lead group on the second surface and the orthographic projection of the second binding terminal group on the second surface and the The orthographic projections of the first lead group on the second surface at least partially overlap.
  • the array substrate provided by this exemplary embodiment has the same technical features and working principles as the above-mentioned manufacturing method of the array substrate. The above content has been described in detail and will not be repeated here.
  • the exemplary embodiment also provides a display panel including the above-mentioned array substrate.
  • the display panel can be different types of display panels such as OLED, LCD, and LED.
  • the display panel provided by this exemplary embodiment has the same technical features and working principles as the above-mentioned array substrate, and the above-mentioned content has been described in detail, and will not be repeated here.
  • This exemplary embodiment also provides a splicing screen, which includes the above-mentioned display panel.
  • the splicing screen provided by this exemplary embodiment has the same technical features and working principles as the foregoing display panel.
  • the foregoing content has been described in detail and will not be repeated here.

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Abstract

Provided are an array substrate and a fabrication method, a display panel and a splicing screen. The fabrication method for the array substrate comprises: providing a substrate, the substrate comprising a substrate main body (1), the substrate main body comprising a first surface (U1), a second surface (B1), and a side surface (L1) adjacent to the first surface and the second surface, the first surface of the substrate main body comprising a first binding terminal group (2), and the second surface of the substrate main body comprising a second binding terminal group (3) corresponding to the first binding terminal group; exposing a photoresist layer (4) so as to form a lead pattern (41) that may not be dissolved by a developer; forming a first conductive layer (5) on the photoresist layer, and developing the photoresist layer so as to form a first lead group (51); and forming a second lead group (6) used for connecting the first lead group and the first binding terminal group and connecting the first lead group and the second binding terminal group.

Description

阵列基板及制作方法、显示面板、拼接屏Array substrate and manufacturing method, display panel and splicing screen
本申请要求于2019年4月30日提交的中国专利申请201910362292.6的优先权，其内容通过引用的方式全文并入于此。This application claims the priority of Chinese patent application 201910362292.6 filed on April 30, 2019, the content of which is incorporated herein by reference in its entirety.
技术领域Technical field
本发明涉及显示技术领域，尤其涉及一种阵列基板及制作方法、显示面板、拼接屏。The present invention relates to the field of display technology, in particular to an array substrate and a manufacturing method, a display panel, and a splicing screen.
背景技术Background technique
显示面板一般包括显示区和围绕显示区的边框区。窄边框的显示面板可以给用户带来较好的视觉效果，尤其在拼接屏应用中，窄边框显示面板可以减小拼接屏之间的缝隙。现有技术通过将阵列基板中，用于绑定驱动芯片的绑定区设置于阵列基板的背面(显示侧的相对一面)以减小显示面板的边框尺寸。The display panel generally includes a display area and a border area surrounding the display area. A display panel with a narrow frame can bring better visual effects to users, especially in splicing screen applications, a narrow frame display panel can reduce the gap between splicing screens. In the prior art, the bonding area for bonding the driving chip in the array substrate is arranged on the back of the array substrate (the side opposite to the display side) to reduce the frame size of the display panel.
相关技术中，阵列基板的绑定端子组一般位于阵列基板的正面(显示侧)，因此需要在阵列基板的背面设置新的绑定端子组，以及通过引线组连接位于阵列基板的正面的绑定端子组和位于阵列基板背面的绑定端子组。相关技术中，主要采用喷墨打印、丝网印刷等方法在阵列基板的边沿形成连接上述两绑定端子组的引线。In the related art, the bonding terminal group of the array substrate is generally located on the front side (display side) of the array substrate, so it is necessary to set a new bonding terminal group on the back of the array substrate, and connect the bonding located on the front side of the array substrate through the lead group. The terminal group and the binding terminal group on the back of the array substrate. In the related art, methods such as inkjet printing, screen printing, etc. are mainly used to form leads connecting the two bound terminal groups on the edge of the array substrate.
然而，阵列基板的边缘接近直角且存在锋利的毛刺，从而易导致引线断线，另外由于喷墨打印、丝网印刷精度的限制，使得引线的间距和线宽较大，从而限制了屏幕的分辨率。However, the edge of the array substrate is close to a right angle and there are sharp burrs, which easily lead to wire breakage. In addition, due to the limitations of inkjet printing and screen printing accuracy, the lead spacing and line width are large, which limits the resolution of the screen. rate.
需要说明的是，在上述背景技术部分发明的信息仅用于加强对本发明的背景的理解，因此可以包括不构成对本领域普通技术人员已知的现有技术的信息。It should be noted that the information of the invention in the background art section above is only used to enhance the understanding of the background of the invention, and therefore may include information that does not constitute the prior art known to those of ordinary skill in the art.
发明内容Summary of the invention
本发明的目的在于提供一种阵列基板及制作方法、显示面板、拼接屏，该阵列基板制作方法能够解决相关技术中，引线容易断线以及引线的间距和线宽较大，限制屏幕分辨率的技术问题。The purpose of the present invention is to provide an array substrate and a manufacturing method, a display panel, and a splicing screen. The manufacturing method of the array substrate can solve the problem that the lead is easily broken and the lead spacing and line width are large in the related technology, which limits the screen resolution. technical problem.
本发明的其他特性和优点将通过下面的详细描述变得显然，或部分地通过本发明的实践而习得。Other characteristics and advantages of the present invention will become apparent through the following detailed description, or partly learned through the practice of the present invention.
根据本公开的一方面，提供一种阵列基板制作方法，所述方法包括：According to an aspect of the present disclosure, there is provided a manufacturing method of an array substrate, the method including:
提供基板，所述基板包括基板主体，所述基板主体包括第一表面、第二表面和与所述第一表面和所述第二表面相邻接的侧面，所述基板主体的第一表面包括第一绑定端子组，所述基板主体的第二表面包括与第一绑定端子组对应的第二绑定端子组，所述第一绑定端子组在所述第一表面的正投影与所述第二绑定端子组在所述第一表面的正投影重合；A substrate is provided, the substrate includes a substrate body, the substrate body includes a first surface, a second surface, and side surfaces adjacent to the first surface and the second surface, and the first surface of the substrate body includes The first binding terminal group, the second surface of the substrate body includes a second binding terminal group corresponding to the first binding terminal group, and the orthographic projection of the first binding terminal group on the first surface and The orthographic projections of the second binding terminal group on the first surface coincide;
在所述基板主体的所述第一表面、所述第二表面以及所述侧面形成光刻胶层；Forming a photoresist layer on the first surface, the second surface, and the side surface of the substrate body;
对所述光刻胶层进行曝光，以形成能够不被显影液溶解的引线图案；Exposing the photoresist layer to form a lead pattern that can not be dissolved by the developer;
在所述光刻胶层上形成第一导电层，并对所述光刻胶层进行显影，以形成第一引线组，所述第一引线组在所述第一表面上的正投影位于所述引线图案在所述第一表面上的正投影内，所述第一引线组在所述第二表面上的正投影位于所述引线图案在所述第二表面上的正投影内；A first conductive layer is formed on the photoresist layer, and the photoresist layer is developed to form a first lead group. The orthographic projection of the first lead group on the first surface is located at the The lead pattern is in the orthographic projection on the first surface, and the orthographic projection of the first lead group on the second surface is in the orthographic projection of the lead pattern on the second surface;
形成第二引线组，用于连接所述第一引线组与所述第一绑定端子组和连接所述第一引线组与所述第二绑定端子组。A second lead group is formed for connecting the first lead group and the first binding terminal group and connecting the first lead group and the second binding terminal group.
在本公开的一种示例性实施例中，所述引线图案在所述侧面所在平面上的正投影位于所述第一引线组在所述侧面所在平面上的正投影内。In an exemplary embodiment of the present disclosure, the orthographic projection of the lead pattern on the plane where the side surface is located is within the orthographic projection of the first lead group on the plane where the side surface is located.
在本公开的一种示例性实施例中，所述基板主体包括衬底基板，在所述基板主体的所述第一表面、所述第二表面以及所述侧面形成光刻胶层，所述方法还包括：In an exemplary embodiment of the present disclosure, the substrate body includes a base substrate, a photoresist layer is formed on the first surface, the second surface, and the side surface of the substrate body, and Methods also include:
对所述衬底基板的侧面的棱角进行钝化处理。Passivating the edges and corners of the side surface of the base substrate.
在本公开的一种示例性实施例中，在所述基板主体的所述第一表面、所述第二表面以及所述侧面形成光刻胶层之前，所述方法还包括：In an exemplary embodiment of the present disclosure, before forming a photoresist layer on the first surface, the second surface, and the side surface of the substrate body, the method further includes:
对所述衬底基板的侧面进行毛刺钝化处理。Burr passivation is performed on the side surface of the base substrate.
在本公开的一种示例性实施例中，在所述基板主体的所述第一表面、所述第二表面以及所述侧面形成光刻胶层，包括：In an exemplary embodiment of the present disclosure, forming a photoresist layer on the first surface, the second surface, and the side surface of the substrate body includes:
通过涂覆工艺在所述基板主体的所述第一表面、所述第二表面以及所述侧面形成光刻胶层。A photoresist layer is formed on the first surface, the second surface and the side surface of the substrate body through a coating process.
在本公开的一种示例性实施例中，形成第二引线组，包括：In an exemplary embodiment of the present disclosure, forming the second lead group includes:
通过喷墨打印技术形成所述第二引线组。The second lead group is formed by inkjet printing technology.
在本公开的一种示例性实施例中，所述光刻胶层为正性光刻胶或负性光刻胶。In an exemplary embodiment of the present disclosure, the photoresist layer is a positive photoresist or a negative photoresist.
根据本公开的一方面，提供一种阵列基板，所述阵列基板包括：基板，包括基板主体，所述基板主体包括第一表面、第二表面和与所述第一表面和所述第二表面相邻接的侧面，所述基板主体的第一表面包括第一绑定端子组、所述基板主体的第二表面包括第二绑定端子组，所述第一绑定端子组在所述第一表面的正投影与所述第二绑定端子组在所述第一表面的正投影重合；According to an aspect of the present disclosure, there is provided an array substrate including: a substrate including a substrate main body, the substrate main body including a first surface, a second surface, and the first surface and the second surface Adjacent side surfaces, the first surface of the substrate main body includes a first binding terminal group, the second surface of the substrate main body includes a second binding terminal group, and the first binding terminal group is in the first The orthographic projection of a surface coincides with the orthographic projection of the second binding terminal group on the first surface;
引线图案，覆盖所述第一绑定端子组的部分表面、所述第二绑定端子组的部分表面以及所述侧面的部分表面；A lead pattern covering part of the surface of the first binding terminal group, part of the surface of the second binding terminal group, and part of the surface of the side surface;
第一引线组，所述第一引线组在所述第一表面上的正投影位于所述引线图案在所述第一表面上的正投影内，所述第一引线组在所述第二表面上的正投影位于所述引线图案在所述第二表面上的正投影内；A first lead group, the orthographic projection of the first lead group on the first surface is within the orthographic projection of the lead pattern on the first surface, and the first lead group is on the second surface The orthographic projection on the second surface is within the orthographic projection of the lead pattern on the second surface;
第二引线组，用于连接所述第一引线组与所述第一绑定端子组和连接所述第一引线组与所述第二绑定端子组。The second lead group is used for connecting the first lead group and the first binding terminal group and connecting the first lead group and the second binding terminal group.
在本公开的一种示例性实施例中，所述引线图案在所述侧面所在平面上的正投影位于所述第一引线组在所述侧面所在平面上的正投影内。In an exemplary embodiment of the present disclosure, the orthographic projection of the lead pattern on the plane where the side surface is located is within the orthographic projection of the first lead group on the plane where the side surface is located.
在本公开的一种示例性实施例中，所述第二引线组在所述第一表面上的正投影与所述第一绑定端子组在所述第一表面上的正投影以及所述第一引线组在所述第一表面上的正投影至少部分重合，所述第二引线组在所述第二表面上的正投影与所述第二绑定端子组在所述第二表面上的正投影以及所述第一引线组在所述第二表面上的正投影至少部分重合。In an exemplary embodiment of the present disclosure, the orthographic projection of the second lead group on the first surface and the orthographic projection of the first binding terminal group on the first surface and the The orthographic projection of the first lead group on the first surface at least partially overlaps, and the orthographic projection of the second lead group on the second surface and the second binding terminal group on the second surface The orthographic projection of and the orthographic projection of the first lead group on the second surface at least partially overlap.
在本公开的一种示例性实施例中，所述基板主体还包括衬底基板，所述衬底基板的所述侧面的棱角为圆角。In an exemplary embodiment of the present disclosure, the substrate body further includes a base substrate, and the corners of the side surface of the base substrate are rounded corners.
在本公开的一种示例性实施例中，所述第一绑定端子组与像素驱动电路层中的信号端连接，所述第二绑定端子组与驱动芯片连接。In an exemplary embodiment of the present disclosure, the first bonding terminal group is connected to a signal terminal in the pixel driving circuit layer, and the second bonding terminal group is connected to a driving chip.
在本公开提供的技术方案中，一方面，将第一引线设置在光刻胶层上，光刻胶层对阵列基板的正面、背面以及侧面具有平坦化和钝化效果，从而降低了第一引线组由于阵列基板边沿棱角和毛刺造成的断裂风险；另一方面，通过对光刻胶层的光刻技术形成第一引线，可以减小第一引线的宽度以及相邻第一引线之间的距离，从而降低了第一引线组对阵列基板分辨率的限制。In the technical solution provided by the present disclosure, on the one hand, the first lead is arranged on the photoresist layer, and the photoresist layer has a flattening and passivation effect on the front, back and side surfaces of the array substrate, thereby reducing the first lead. The lead set is at risk of breaking due to the edges and burrs of the array substrate. On the other hand, the first lead is formed by photolithography on the photoresist layer, which can reduce the width of the first lead and the distance between adjacent first leads. The distance, thereby reducing the limitation on the resolution of the array substrate by the first lead group.
应当理解的是，以上的一般描述和后文的细节描述仅是示例性和解释性的，并不能限制本发明。It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present invention.
附图说明Description of the drawings
此处的附图被并入说明书中并构成本说明书的一部分，示出了符合本发明的实施例，并与说明书一起用于解释本发明的原理。显而易见地，下面描述中的附图仅仅是本发明的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。The drawings herein are incorporated into the specification and constitute a part of the specification, show embodiments in accordance with the present invention, and together with the specification are used to explain the principle of the present invention. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative work.
图1为本公开阵列基板制作方法一种示例性实施例的流程图；FIG. 1 is a flowchart of an exemplary embodiment of a manufacturing method of an array substrate of the present disclosure;
图2为本公开一种示例性实施例中阵列基板的局部结构示意图；2 is a schematic diagram of a partial structure of an array substrate in an exemplary embodiment of the present disclosure;
图3为本公开一种示例性实施例中阵列基板的侧视图；FIG. 3 is a side view of an array substrate in an exemplary embodiment of the present disclosure;
图4为本公开一种示例性实施例中阵列基板的局部结构示意图；4 is a schematic diagram of a partial structure of an array substrate in an exemplary embodiment of the present disclosure;
图5为本公开一种示例性实施例中阵列基板的局部结构示意图；FIG. 5 is a schematic diagram of a partial structure of an array substrate in an exemplary embodiment of the present disclosure;
图6为本公开一种示例性实施例中阵列基板的侧视图；Fig. 6 is a side view of an array substrate in an exemplary embodiment of the present disclosure;
图7为图6中A-A方向的剖视图；Figure 7 is a cross-sectional view in the direction of A-A in Figure 6;
图8为本公开一种示例性实施例中阵列基板的侧视图；FIG. 8 is a side view of an array substrate in an exemplary embodiment of the present disclosure;
图9为图8中A-A方向的剖视图；Figure 9 is a cross-sectional view in the direction of A-A in Figure 8;
图10为本公开一种示例性实施例中阵列基板的局部结构示意图；FIG. 10 is a schematic diagram of a partial structure of an array substrate in an exemplary embodiment of the present disclosure;
图11为本公开一种示例性实施例中阵列基板的侧视图；FIG. 11 is a side view of an array substrate in an exemplary embodiment of the present disclosure;
图12为图11中A-A方向的剖视图；Figure 12 is a cross-sectional view in the direction of A-A in Figure 11;
图13为本公开一种示例性实施例中阵列基板的侧视图；FIG. 13 is a side view of an array substrate in an exemplary embodiment of the present disclosure;
图14为图13中A-A方向的剖视图；Figure 14 is a cross-sectional view in the direction of A-A in Figure 13;
图15为本公开一种示例性实施例中阵列基板的局部结构示意图；15 is a schematic diagram of a partial structure of an array substrate in an exemplary embodiment of the present disclosure;
图16为本公开一种示例性实施例中阵列基板的侧视图；FIG. 16 is a side view of an array substrate in an exemplary embodiment of the present disclosure;
图17为本公开一种示例性实施例中阵列基板的俯视图。FIG. 17 is a top view of an array substrate in an exemplary embodiment of the present disclosure.
具体实施方式Detailed ways
现在将参考附图更全面地描述示例实施例。然而，示例实施例能够以多种形式实施，且不应被理解为限于在此阐述的范例；相反，提供这些实施例使得本发明将更加全面和完整，并将示例实施例的构思全面地传达给本领域的技术人员。图中相同的附图标记表示相同或类似的结构，因而将省略它们的详细描述。Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms, and should not be construed as being limited to the examples set forth herein; on the contrary, the provision of these embodiments makes the present invention more comprehensive and complete, and fully conveys the concept of the example embodiments To those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed descriptions will be omitted.
虽然本说明书中使用相对性的用语，例如“上”“下”来描述图标的一个组件对于另一组件的相对关系，但是这些术语用于本说明书中仅出于方便，例如根据附图中所述的示例的方向。能理解的是，如果将图标的装置翻转使其上下颠倒，则所叙述在“上”的组件将会成为在“下”的组件。其他相对性的用语，例如“高”“低”“顶”“底”“左”“右”等也作具有类似含义。当某结构在其它结构“上”时，有可能是指某结构一体形成于其它结构上，或指某结构“直接”设置在其它结构上，或指某结构通过另一结构“间接”设置在其它结构上。Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used in this specification only for convenience, for example, according to the drawings. The direction of the example described. It can be understood that if the device of the icon is turned over and turned upside down, the component described as "upper" will become the "lower" component. Other relative terms, such as "high", "low", "top", "bottom", "left" and "right" have similar meanings. When a structure is “on” another structure, it may mean that a certain structure is integrally formed on another structure, or that a certain structure is “directly” arranged on another structure, or that a certain structure is “indirectly” arranged on another structure through another structure. On other structures.
用语“一个”、“一”、“用以表示存在一个或多个要素/组成部分/等；用语“包括”和“具有”用以表示开放式的包括在内的意思并且是指除了列出的要素/组成部分/等之外还可存在另外的要素/组成部分/等。The terms "a", "a", and "are used to indicate the presence of one or more elements/components/etc.; the terms "include" and "have" are used to mean open-ended inclusion and refer to the In addition to the elements/components/etc., there may be other elements/components/etc.
本示例性实施例提供一种阵列基板制作方法，如图1所示，为本公开阵列基板制作方法一种示例性实施例的流程图，所述方法包括：This exemplary embodiment provides a method for manufacturing an array substrate. As shown in FIG. 1, it is a flowchart of an exemplary embodiment of the method for manufacturing an array substrate of the present disclosure. The method includes:
步骤S1：提供基板，所述基板包括基板主体，所述基板主体包括第一表面、第二表面和与所述第一表面和所述第二表面相邻接的侧面，所述基板主体的第一表面包括第一绑定端子组，所述基板主体的第二表面包括与第一绑定端子组对应的第二绑定端子组，所述第一绑定端子组在所述第一表面的正投影与所述第二绑定端子组在所述第一表面的正投影重合；Step S1: Provide a substrate, the substrate includes a substrate main body, the substrate main body includes a first surface, a second surface, and side surfaces adjacent to the first surface and the second surface, and the first surface of the substrate main body One surface includes a first binding terminal group, the second surface of the substrate body includes a second binding terminal group corresponding to the first binding terminal group, and the first binding terminal group is located on the first surface The orthographic projection coincides with the orthographic projection of the second binding terminal group on the first surface;
步骤S2：在所述基板主体的所述第一表面、所述第二表面以及所述侧面形成光刻胶层；Step S2: forming a photoresist layer on the first surface, the second surface and the side surface of the substrate body;
步骤S3：对所述光刻胶层进行曝光，以形成能够不被显影液溶解的引线图案；Step S3: Expose the photoresist layer to form a lead pattern that can not be dissolved by the developer;
步骤S4：在所述光刻胶层上形成第一导电层，并对所述光刻胶层进行显影，以形成第一引线组，所述第一引线组在所述第一表面上的正投影位于所述引线图案在所述第一表面上的正投影内，所述第一引线组在所述第二表面上的正投影位于所述引线图案在所述第二表面上的正投影内；Step S4: forming a first conductive layer on the photoresist layer, and developing the photoresist layer to form a first lead group, the first lead group being located on the first surface The projection is located in the orthographic projection of the lead pattern on the first surface, and the orthographic projection of the first lead group on the second surface is located in the orthographic projection of the lead pattern on the second surface ；
步骤S5：形成第二引线组，用于连接所述第一引线组与所述第一绑定端子组和连接 所述第一引线组与所述第二绑定端子组。Step S5: forming a second lead group for connecting the first lead group and the first binding terminal group and connecting the first lead group and the second binding terminal group.
在本公开的实施例中，基板主体的第一表面例如可以是基板主体的正面，即可以为阵列基板显示侧的一面，基板主体的第二表面例如可以是基板主体的背面，即可以为阵列基板相对显示侧的一面。基板主体的侧面可以是与正面和背面相邻接的侧面。In the embodiment of the present disclosure, the first surface of the substrate body may be, for example, the front surface of the substrate body, that is, the display side of the array substrate, and the second surface of the substrate body may be, for example, the back surface of the substrate body, that is, the array The side of the substrate opposite to the display side. The side surface of the substrate body may be the side surface adjacent to the front surface and the back surface.
在本公开实施例提供的技术方案中，一方面，将第一引线设置在光刻胶层上，光刻胶层对阵列基板的正面、背面以及侧面具有平坦化和钝化效果，从而降低了第一引线组由于阵列基板边沿棱角和毛刺造成的断裂风险；另一方面，通过对光刻胶层的光刻技术形成第一引线，可以减小第一引线的宽度以及相邻第一引线之间的距离，从而降低了第一引线组对阵列基板分辨率的限制。In the technical solution provided by the embodiments of the present disclosure, on the one hand, the first lead is disposed on the photoresist layer, and the photoresist layer has a flattening and passivation effect on the front, back and sides of the array substrate, thereby reducing The first lead group is at risk of breaking due to the edges and burrs of the array substrate; on the other hand, the first lead is formed by photolithography on the photoresist layer, which can reduce the width of the first lead and the distance between adjacent first leads. Therefore, the limitation of the first lead group on the resolution of the array substrate is reduced.
以下对上述步骤进行详细说明：The above steps are described in detail below:
如图2-图16所示，为本公开阵列基板制作方法一种示例性实施例中制作过程的结构示意图。其中，图2、4、5、10、15为本公开阵列基板制作方法一种示例性实施例中阵列基板的局部结构示意图，图3、6、8、11、13为本公开阵列基板制作方法一种示例性实施例中阵列基板的侧视图；图7为图6中A-A方向的剖视图；图9为图8中A-A方向的剖视图；图12为图11中A-A方向的剖视图；图14为图13中A-A方向的剖视图。As shown in FIGS. 2 to 16, they are schematic structural diagrams of the manufacturing process in an exemplary embodiment of the manufacturing method of the array substrate of the present disclosure. Among them, Figures 2, 4, 5, 10, 15 are partial structural diagrams of the array substrate in an exemplary embodiment of the disclosed array substrate manufacturing method, and Figures 3, 6, 8, 11, 13 are the disclosed array substrate manufacturing method A side view of the array substrate in an exemplary embodiment; FIG. 7 is a cross-sectional view in the AA direction in FIG. 6; FIG. 9 is a cross-sectional view in the AA direction in FIG. 8; FIG. 12 is a cross-sectional view in the AA direction in FIG. 11; Section 13 in the direction of AA.
步骤S1：形成一基板，所述基板包括基板主体，基板主体包括第一表面(例如基板主体的正面U1)、第二表面(例如基板主体的背面B1)和与所述第一表面和所述第二表面相邻接的侧面(例如连接正面U1和背面B1的侧面L1)。Step S1: forming a substrate, the substrate includes a substrate main body, the substrate main body includes a first surface (for example, the front U1 of the substrate main body), a second surface (for example, the back B1 of the substrate main body) and the first surface and the The side surface adjacent to the second surface (for example, the side surface L1 connecting the front surface U1 and the back surface B1).
如图2、3所示，该阵列基板可以包括基板主体1，基板主体的第一表面U1包括第一绑定端子组，基板主体的第二表面B1包括与第一绑定端子组对应的第二绑定端子组。其中，第一绑定端子组可以包括多个第一绑定端子2，第二绑定端子组可以包括多个第二绑定端子3。该多个第一绑定端子2可以相互间隔彼此平行地设置，该多个第二绑定端子3页可以相互间隔彼此平行地设置。第一绑定端子组在第一表面U1的正投影与第二绑定端子组在第一表面U1的正投影重合。As shown in FIGS. 2 and 3, the array substrate may include a substrate body 1, a first surface U1 of the substrate body includes a first binding terminal group, and a second surface B1 of the substrate body includes a first binding terminal group corresponding to the first binding terminal group. Two binding terminal group. The first binding terminal group may include a plurality of first binding terminals 2, and the second binding terminal group may include a plurality of second binding terminals 3. The plurality of first binding terminals 2 may be arranged in parallel with each other at intervals, and the plurality of second binding terminals 3 may be arranged in parallel with each other at intervals. The orthographic projection of the first binding terminal group on the first surface U1 coincides with the orthographic projection of the second binding terminal group on the first surface U1.
根据本公开的一实施例，基板主体1可以包括衬底基板12和功能层11，功能层11可以为像素驱动电路层中的任意一层；该多个第一绑定端子2可以位于功能层11的一侧，用于与像素驱动电路层中的信号端连接；该多个第二绑定端子3可以位于衬底基板12的一侧，用于与驱动芯片连接。该驱动芯片可以为源极驱动芯片、栅极驱动芯片等。衬底基板12的材质可以为玻璃、石英、硅、塑料、聚酰亚胺，聚甲基丙烯酸甲酯等中的任意一种，衬底基板12的厚度可以为0.5mm左右。According to an embodiment of the present disclosure, the substrate body 1 may include a base substrate 12 and a functional layer 11. The functional layer 11 may be any layer of the pixel driving circuit layer; the plurality of first binding terminals 2 may be located on the functional layer One side of 11 is used to connect to the signal terminal in the pixel driving circuit layer; the plurality of second binding terminals 3 may be located on one side of the base substrate 12 and used to connect to the driving chip. The driving chip may be a source driving chip, a gate driving chip, and so on. The material of the base substrate 12 may be any of glass, quartz, silicon, plastic, polyimide, polymethyl methacrylate, etc., and the thickness of the base substrate 12 may be about 0.5 mm.
应该理解的是，基板主体还可以有其他的结构，例如，基板主体可以仅仅包括一衬底基板，第一绑定端子组和第二绑定端子组分别设置于衬底基板的两侧。It should be understood that the substrate main body may also have other structures. For example, the substrate main body may only include a base substrate, and the first binding terminal group and the second binding terminal group are respectively disposed on both sides of the base substrate.
如图4所示，本示例性实施例中，在所述基板主体的所述第一表面、所述第二表面以及所述侧面形成光刻胶层之前，该方法还可以包括：对衬底基板的侧面的棱角进行钝化处 理，以将衬底基板的所述侧面的棱角形成圆角，从而进一步降低第一引线组断裂的风险。As shown in FIG. 4, in this exemplary embodiment, before the photoresist layer is formed on the first surface, the second surface, and the side surface of the substrate body, the method may further include: The edges and corners of the side surface of the substrate are passivated to round the edges and corners of the side surface of the base substrate, thereby further reducing the risk of the first lead group breaking.
根据一实施例，在所述基板主体的所述第一表面、所述第二表面以及所述侧面形成光刻胶层之前，还可以包括：对所述衬底基板的所述侧面进行毛刺钝化处理。这同样可以降低第一引线组断裂的风险。According to an embodiment, before forming the photoresist layer on the first surface, the second surface, and the side surface of the substrate body, the method may further include: burring the side surface of the base substrate化处理. This can also reduce the risk of breakage of the first lead group.
步骤S2：在所述基板主体的所述第一表面、所述第二表面以及所述侧面形成光刻胶层。Step S2: forming a photoresist layer on the first surface, the second surface and the side surface of the substrate body.
如图5、6、7所示，可以在所述基板主体的第一表面U1、第二表面B1以及侧面L1形成光刻胶层4。其中，形成光刻胶层，可以包括：通过涂覆工艺形成光刻胶层4。例如，可以将基板主体浸入入光刻胶溶液内从而形成光刻胶层4，再例如，可以通过喷涂形成光刻胶层。As shown in FIGS. 5, 6, and 7, a photoresist layer 4 may be formed on the first surface U1, the second surface B1, and the side surface L1 of the substrate body. Wherein, forming the photoresist layer may include: forming the photoresist layer 4 through a coating process. For example, the main body of the substrate can be immersed in a photoresist solution to form the photoresist layer 4, and for another example, the photoresist layer can be formed by spraying.
步骤S3：对所述光刻胶层进行曝光，以形成能够不被显影液溶解的引线图案。Step S3: Expose the photoresist layer to form a lead pattern that can not be dissolved by the developer.
如图8、9所示，可以对所述光刻胶层4进行曝光，以使所述光刻胶层形成能够不被显影液溶解的引线图案41。该光刻胶层可以为正性光刻胶层也可以为负性光刻胶层。当光刻胶为正性光刻胶时，引线图案41为未被曝光部分，当光刻胶为负性光刻胶时，引线图案41为被曝光部分。As shown in FIGS. 8 and 9, the photoresist layer 4 may be exposed to light so that the photoresist layer can form a lead pattern 41 that can not be dissolved by the developer. The photoresist layer can be a positive photoresist layer or a negative photoresist layer. When the photoresist is a positive photoresist, the lead pattern 41 is an unexposed part, and when the photoresist is a negative photoresist, the lead pattern 41 is an exposed part.
步骤S4：在所述光刻胶层上形成第一导电层，并对所述光刻胶层进行显影，以形成第一引线组，所述第一引线组在所述第一表面上的正投影位于所述引线图案在所述第一表面上的正投影内，所述第一引线组在所述第二表面上的正投影位于所述引线图案在所述第二表面上的正投影内。Step S4: forming a first conductive layer on the photoresist layer, and developing the photoresist layer to form a first lead group, the first lead group being located on the first surface The projection is located in the orthographic projection of the lead pattern on the first surface, and the orthographic projection of the first lead group on the second surface is located in the orthographic projection of the lead pattern on the second surface .
如图10、11、12所示，步骤S4可以包括在所述光刻胶层4上形成第一导电层5，如图13、14所示，步骤S4还包括对所述光刻胶层4进行显影，光刻胶层4位于引线图案41以外的部分被显影液溶解，同时位于引线图案41以外部分的第一导电层5也被溶解，如图14所示，从而可以将所述第一导电层5形成与所述引线图案41图案相同的第一引线组，第一引线组包括多条第一引线51。可以理解的是，为了保证在对光刻胶层4进行显影工艺的同时，能够对第一导电层5图案化以形成与引线图案41图案大致相同的第一引线组，故所形成的第一导电层5在第一表面U1上的正投影位于光刻胶层4在第一表面U1上的正投影内；第一导电层5在第二表面B1上的正投影位于光刻胶层4在第二表面B1上的正投影内。第一导电层5在侧面L1所在平面上的沿第一表面U1指向第二表面B1的方向上的宽度必然大于光刻胶层4在侧面L1所在平面上的沿第一表面U1指向第二表面B1的方向上的宽度；第一导电层5在侧面L1所在平面上的沿垂直于第一表面U1指向第二表面B1的方向上的宽度小于等于光刻胶层4在侧面L1所在平面上的沿垂直于第一表面U1指向第二表面B1的方向上的宽度，如图11所示。As shown in FIGS. 10, 11, and 12, step S4 may include forming a first conductive layer 5 on the photoresist layer 4. As shown in FIGS. 13 and 14, step S4 may also include a step on the photoresist layer 4. During development, the part of the photoresist layer 4 outside the lead pattern 41 is dissolved by the developer, and the first conductive layer 5 outside the lead pattern 41 is also dissolved, as shown in FIG. 14, so that the first The conductive layer 5 forms a first lead group with the same pattern as the lead pattern 41, and the first lead group includes a plurality of first leads 51. It can be understood that, in order to ensure that the first conductive layer 5 can be patterned to form a first lead group having approximately the same pattern as the lead pattern 41 while the photoresist layer 4 is undergoing the development process, the first lead group is formed. The orthographic projection of the conductive layer 5 on the first surface U1 is located within the orthographic projection of the photoresist layer 4 on the first surface U1; the orthographic projection of the first conductive layer 5 on the second surface B1 is located on the photoresist layer 4 In the orthographic projection on the second surface B1. The width of the first conductive layer 5 in the direction along the first surface U1 pointing to the second surface B1 on the plane of the side surface L1 must be greater than that of the photoresist layer 4 on the plane of the side surface L1 pointing to the second surface along the first surface U1 The width in the direction of B1; the width of the first conductive layer 5 on the plane of the side L1 along the direction perpendicular to the first surface U1 to the second surface B1 is less than or equal to the width of the photoresist layer 4 on the plane of the side L1 The width along the direction perpendicular to the first surface U1 to the second surface B1 is as shown in FIG. 11.
然而本公开实施例不限于此，第一导电层5在在侧面L1所在平面上的沿垂直于第一表面U1指向第二表面B1的方向上的尺寸也可以等于光刻胶层4在该方向的尺寸。However, the embodiments of the present disclosure are not limited to this, and the size of the first conductive layer 5 in the direction perpendicular to the first surface U1 to the second surface B1 on the plane where the side surface L1 is located may also be equal to the size of the photoresist layer 4 in this direction. size of.
根据本公开的一示例性实施例，第一引线组在第一表面U1上的正投影位于引线图案41在第一表面U1上的正投影内，第一引线组在第二表面B1上的正投影位于引线图案41在第二表面B1上的正投影内。According to an exemplary embodiment of the present disclosure, the orthographic projection of the first lead group on the first surface U1 is within the orthographic projection of the lead pattern 41 on the first surface U1, and the orthographic projection of the first lead group on the second surface B1 The projection is located within the orthographic projection of the lead pattern 41 on the second surface B1.
根据本公开的一示例性实施例，引线图案41在侧面L1所在平面上的正投影位于第一引线组在侧面L1所在平面上的正投影内。可以理解的是，第一引线组在侧面L1所在平面上的沿第一表面U1指向第二表面B1的方向上的宽度必然大于引线图案41在侧面L1所在平面上的沿第一表面U1指向第二表面B1的方向上的宽度；第一引线组在侧面L1所在平面上的沿垂直于第一表面U1指向第二表面B1的方向上的宽度小于等于引线图案41在侧面L1所在平面上的沿垂直于第一表面U1指向第二表面B1的方向上的宽度，According to an exemplary embodiment of the present disclosure, the orthographic projection of the lead pattern 41 on the plane where the side face L1 is located is within the orthographic projection of the first lead group on the plane where the side face L1 is located. It can be understood that the width of the first lead group in the direction along the first surface U1 pointing to the second surface B1 on the plane where the side surface L1 is located must be greater than that of the lead pattern 41 on the plane where the side surface L1 is directed to the second surface along the first surface U1. The width in the direction of the two surfaces B1; the width of the first lead group on the plane where the side surface L1 is located in the direction perpendicular to the first surface U1 to the second surface B1 is less than or equal to the edge of the lead pattern 41 on the plane where the side surface L1 is located The width in the direction perpendicular to the first surface U1 pointing to the second surface B1,
步骤S5：形成第二引线组，用于连接所述第一引线组与所述第一绑定端子组和连接所述第一引线组与所述第二绑定端子组。Step S5: forming a second lead group for connecting the first lead group and the first binding terminal group and connecting the first lead group and the second binding terminal group.
如图15、16所示，步骤S5可以包括形成第二引线组，以连接所述第一引线组与所述第一绑定端子组并连接第一引线组与第二绑定端子组。第二引线组包括多条第二引线6，该多条第二引线可以彼此间隔相互并行地设置。图17为所形成的阵列基板的俯视图。As shown in FIGS. 15 and 16, step S5 may include forming a second lead group to connect the first lead group and the first binding terminal group and to connect the first lead group and the second binding terminal group. The second lead group includes a plurality of second leads 6, which may be arranged in parallel with each other at intervals. FIG. 17 is a top view of the formed array substrate.
根据本公开的一示例性实施例，第二引线组在第一表面U1上的正投影与第一绑定端子组在第一表面U1上的正投影以及第一引线组在第一表面U1上的正投影至少部分重合，第二引线组在第二表面B1上的正投影与第二绑定端子组在B1第二表面上的正投影以及第一引线组在第二表面B1上的正投影至少部分重合。以此方式，可以通过第二引线组中的多个第二引线6实现第一引线组与第一绑定端子组的连接，并且通过第二引线组的多个多案子6实现第一引线组与第二绑定端子组的连接。According to an exemplary embodiment of the present disclosure, the orthographic projection of the second lead group on the first surface U1 and the orthographic projection of the first binding terminal group on the first surface U1 and the first lead group on the first surface U1 The orthographic projection of at least partially overlaps, the orthographic projection of the second lead group on the second surface B1 and the orthographic projection of the second binding terminal group on the second surface of B1 and the orthographic projection of the first lead group on the second surface B1 At least partially overlap. In this way, the connection between the first lead group and the first binding terminal group can be realized by the multiple second leads 6 in the second lead group, and the first lead group can be realized by the multiple cases 6 of the second lead group. Connection with the second binding terminal group.
根据一示例性实施例，在形成第二引线组可以包括：通过喷墨打印技术形成所述第二引线组。According to an exemplary embodiment, forming the second lead group may include: forming the second lead group by inkjet printing technology.
在其他示例性实施例中，形成第二引线组还可以包括：通过蒸镀、喷墨打印等技术形成所述第二引线组。In other exemplary embodiments, forming the second lead group may further include: forming the second lead group by techniques such as evaporation and inkjet printing.
此外，该阵列基板制作方法还可以包括对上述的第一引线组和第二引线组进行封装，以避免第一引线组和第二引线组氧化。另外一个作用是避免露在外面的引线与其他金属短路。In addition, the manufacturing method of the array substrate may further include packaging the first lead group and the second lead group to avoid oxidation of the first lead group and the second lead group. Another function is to avoid short circuits between exposed leads and other metals.
本示例性实施例还提供一种阵列基板，所述阵列基板包括：基板，包括基板主体，所述基板主体包括第一表面、第二表面和与所述第一表面和所述第二表面相邻接的侧面，所述基板主体的第一表面包括第一绑定端子组、所述基板主体的第二表面包括第二绑定端子组，所述第一绑定端子组在所述第一表面的正投影与所述第二绑定端子组在所述第一表面的正投影重合；引线图案，覆盖所述第一绑定端子组的部分表面、所述第二绑定端子组的部分表面以及所述侧面的部分表面；第一引线组，所述第一引线组在所述第一表面上的正投影位于所述引线图案在所述第一表面上的正投影内，所 述第一引线组在所述第二表面上的正投影位于所述引线图案在所述第二表面上的正投影内；第二引线组，用于连接所述第一引线组与所述第一绑定端子组和连接所述第一引线组与所述第二绑定端子组。The exemplary embodiment also provides an array substrate, the array substrate includes: a substrate, including a substrate main body, the substrate main body includes a first surface, a second surface and the first surface and the second surface. Adjacent to the side surface, the first surface of the substrate body includes a first binding terminal group, and the second surface of the substrate body includes a second binding terminal group, and the first binding terminal group is in the first The orthographic projection of the surface coincides with the orthographic projection of the second binding terminal group on the first surface; the lead pattern covers part of the surface of the first binding terminal group and part of the second binding terminal group Surface and part of the surface of the side surface; a first lead group, the orthographic projection of the first lead group on the first surface is located within the orthographic projection of the lead pattern on the first surface, the first The orthographic projection of a lead group on the second surface is located within the orthographic projection of the lead pattern on the second surface; a second lead group is used to connect the first lead group and the first binding The terminal group is fixed and the first lead group and the second binding terminal group are connected.
根据一示例性实施例中，所述基板主体还包括衬底基板，所述衬底基板的所述侧面的棱角为圆角。According to an exemplary embodiment, the substrate body further includes a base substrate, and the corners of the side surface of the base substrate are rounded corners.
根据一示例性实施例中，所述光刻胶层为正性光刻胶或负性光刻胶。According to an exemplary embodiment, the photoresist layer is a positive photoresist or a negative photoresist.
根据一示例性实施例，所述引线图案在所述侧面所在平面上的正投影位于所述第一引线组在所述侧面所在平面上的正投影内。可以理解的是，第一引线组在侧面所在平面上的沿第一表面指向第二表面的方向上的宽度必然大于引线图案在侧面所在平面上的沿第一表面指向第二表面的方向上的宽度；第一引线组在侧面所在平面上的沿垂直于第一表面指向第二表面的方向上的宽度小于等于引线图案在侧面所在平面上的沿垂直于第一表面指向第二表面的方向上的宽度，According to an exemplary embodiment, the orthographic projection of the lead pattern on the plane where the side surface is located is within the orthographic projection of the first lead group on the plane where the side surface is located. It can be understood that the width of the first lead group on the plane of the side surface along the first surface pointing to the second surface must be larger than the width of the lead pattern on the plane of the side surface along the first surface pointing to the second surface. Width; the width of the first lead group on the plane of the side surface along the direction perpendicular to the first surface to the second surface is less than or equal to the width of the lead pattern on the plane of the side surface along the direction perpendicular to the first surface to the second surface Width,
根据一示例性实施例，所述第二引线组在所述第一表面上的正投影与所述第一绑定端子组在所述第一表面上的正投影以及所述第一引线组在所述第一表面上的正投影至少部分重合，所述第二引线组在所述第二表面上的正投影与所述第二绑定端子组在所述第二表面上的正投影以及所述第一引线组在所述第二表面上的正投影至少部分重合。According to an exemplary embodiment, the orthographic projection of the second lead group on the first surface and the orthographic projection of the first binding terminal group on the first surface and the first lead group on the The orthographic projection on the first surface at least partially overlaps, the orthographic projection of the second lead group on the second surface and the orthographic projection of the second binding terminal group on the second surface and the The orthographic projections of the first lead group on the second surface at least partially overlap.
本示例性实施例提供的阵列基板与上述阵列基板制作方法具有相同的技术特征和工作原理，上述内容已经做出详细说明，此处不再赘述。The array substrate provided by this exemplary embodiment has the same technical features and working principles as the above-mentioned manufacturing method of the array substrate. The above content has been described in detail and will not be repeated here.
本示例性实施例还提供一种显示面板，该显示面板包括上述的阵列基板。其中，该显示面板可以为OLED、LCD、LED等不同类型的显示面板。The exemplary embodiment also provides a display panel including the above-mentioned array substrate. Among them, the display panel can be different types of display panels such as OLED, LCD, and LED.
本示例性实施例提供的显示面板与上述阵列基板具有相同的技术特征和工作原理，上述内容已经做出详细说明，此处不再赘述。The display panel provided by this exemplary embodiment has the same technical features and working principles as the above-mentioned array substrate, and the above-mentioned content has been described in detail, and will not be repeated here.
本示例性实施例还提供一种拼接屏，该拼接屏包括上述的显示面板。This exemplary embodiment also provides a splicing screen, which includes the above-mentioned display panel.
本示例性实施例提供的拼接屏与上述显示面板具有相同的技术特征和工作原理，上述内容已经做出详细说明，此处不再赘述。The splicing screen provided by this exemplary embodiment has the same technical features and working principles as the foregoing display panel. The foregoing content has been described in detail and will not be repeated here.
本领域技术人员在考虑说明书及实践这里公开的发明后，将容易想到本公开的其他实施例。本申请旨在涵盖本公开的任何变型、用途或者适应性变化，这些变型、用途或者适应性变化遵循本公开的一般性原理并包括本公开未公开的本技术领域中的公知常识或惯用技术手段。说明书和实施例仅被视为示例性的，本公开的真正范围和精神由权利要求指出。Those skilled in the art will easily think of other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptive changes of the present disclosure, which follow the general principles of the present disclosure and include common knowledge or conventional technical means in the technical field not disclosed in the present disclosure . The description and embodiments are only regarded as exemplary, and the true scope and spirit of the present disclosure are pointed out by the claims.
应当理解的是，本公开并不局限于上面已经描述并在附图中示出的精确结构，并且可以在不脱离其范围进行各种修改和改变。本公开的范围仅由所附的权利要求来限。It should be understood that the present disclosure is not limited to the precise structure that has been described above and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present disclosure is only limited by the appended claims.

Claims (14)

  1. 一种阵列基板制作方法，所述方法包括：A manufacturing method of an array substrate, the method comprising:
    提供基板，所述基板包括基板主体，所述基板主体包括第一表面、第二表面和与所述第一表面和所述第二表面相邻接的侧面，所述基板主体的第一表面包括第一绑定端子组，所述基板主体的第二表面包括与第一绑定端子组对应的第二绑定端子组，所述第一绑定端子组在所述第一表面的正投影与所述第二绑定端子组在所述第一表面的正投影重合；A substrate is provided, the substrate includes a substrate body, the substrate body includes a first surface, a second surface, and side surfaces adjacent to the first surface and the second surface, and the first surface of the substrate body includes The first binding terminal group, the second surface of the substrate body includes a second binding terminal group corresponding to the first binding terminal group, and the orthographic projection of the first binding terminal group on the first surface and The orthographic projections of the second binding terminal group on the first surface coincide;
    在所述基板主体的所述第一表面、所述第二表面以及所述侧面形成光刻胶层；Forming a photoresist layer on the first surface, the second surface, and the side surface of the substrate body;
    对所述光刻胶层进行曝光，以形成能够不被显影液溶解的引线图案；Exposing the photoresist layer to form a lead pattern that can not be dissolved by the developer;
    在所述光刻胶层上形成第一导电层，并对所述光刻胶层进行显影，以形成第一引线组，所述第一引线组在所述第一表面上的正投影位于所述引线图案在所述第一表面上的正投影内，所述第一引线组在所述第二表面上的正投影位于所述引线图案在所述第二表面上的正投影内；A first conductive layer is formed on the photoresist layer, and the photoresist layer is developed to form a first lead group. The orthographic projection of the first lead group on the first surface is located at the The lead pattern is in the orthographic projection on the first surface, and the orthographic projection of the first lead group on the second surface is in the orthographic projection of the lead pattern on the second surface;
    形成第二引线组，用于连接所述第一引线组与所述第一绑定端子组和连接所述第一引线组与所述第二绑定端子组。A second lead group is formed for connecting the first lead group and the first binding terminal group and connecting the first lead group and the second binding terminal group.
  2. 根据权利要求1所述的阵列基板制作方法，其特征在于，所述引线图案在所述侧面所在平面上的正投影位于所述第一引线组在所述侧面所在平面上的正投影内。The method for manufacturing an array substrate according to claim 1, wherein the orthographic projection of the lead pattern on the plane where the side surface is located is within the orthographic projection of the first lead group on the plane where the side surface is located.
  3. 根据权利要求1所述的阵列基板制作方法，其特征在于，所述基板主体包括衬底基板，在所述基板主体的所述第一表面、所述第二表面以及所述侧面形成光刻胶层之前，所述方法还包括：The method of manufacturing an array substrate according to claim 1, wherein the substrate body comprises a base substrate, and a photoresist is formed on the first surface, the second surface, and the side surface of the substrate body Before layering, the method further includes:
    对所述衬底基板的侧面的棱角进行钝化处理。Passivating the edges and corners of the side surface of the base substrate.
  4. 根据权利要求3所述的阵列基板制作方法，其特征在于，在所述基板主体的所述第一表面、所述第二表面以及所述侧面形成光刻胶层之前，所述方法还包括：4. The manufacturing method of the array substrate according to claim 3, wherein before forming a photoresist layer on the first surface, the second surface, and the side surface of the substrate body, the method further comprises:
    对所述衬底基板的侧面进行毛刺钝化处理。Burr passivation is performed on the side surface of the base substrate.
  5. 根据权利要求1所述的阵列基板制作方法，其特征在于，在所述基板主体的所述第一表面、所述第二表面以及所述侧面形成光刻胶层，包括：The method of manufacturing an array substrate according to claim 1, wherein forming a photoresist layer on the first surface, the second surface, and the side surface of the substrate body comprises:
    通过涂覆工艺在所述基板主体的所述第一表面、所述第二表面以及所述侧面形成光刻胶层。A photoresist layer is formed on the first surface, the second surface and the side surface of the substrate body through a coating process.
  6. 根据权利要求1所述的阵列基板制作方法，其特征在于，形成第二引线组，包括：The manufacturing method of the array substrate according to claim 1, wherein forming the second lead group comprises:
    通过喷墨打印技术形成所述第二引线组。The second lead group is formed by inkjet printing technology.
  7. 根据权利要求1至6中任一项所述的阵列基板制作方法，其特征在于，所述光刻胶层为正性光刻胶或负性光刻胶。The method for manufacturing an array substrate according to any one of claims 1 to 6, wherein the photoresist layer is a positive photoresist or a negative photoresist.
  8. 一种阵列基板，所述阵列基板包括：An array substrate, the array substrate comprising:
    基板，包括基板主体，所述基板主体包括第一表面、第二表面和与所述第一表面和所述第二表面相邻接的侧面，所述基板主体的第一表面包括第一绑定端子组、所述基板主体的第二表面包括第二绑定端子组，所述第一绑定端子组在所述第一表面的正投影与所述第二绑定端子组在所述第一表面的正投影重合；The substrate includes a substrate main body, the substrate main body includes a first surface, a second surface, and side surfaces adjacent to the first surface and the second surface, and the first surface of the substrate main body includes a first binding The terminal set and the second surface of the substrate main body include a second binding terminal set, and the orthographic projection of the first binding terminal set on the first surface and the second binding terminal set are in the first The orthographic projection of the surface coincides;
    引线图案，覆盖所述第一绑定端子组的部分表面、所述第二绑定端子组的部分表面以及所述侧面的部分表面；A lead pattern covering part of the surface of the first binding terminal group, part of the surface of the second binding terminal group, and part of the surface of the side surface;
    第一引线组，所述第一引线组在所述第一表面上的正投影位于所述引线图案在所述第一表面上的正投影内，所述第一引线组在所述第二表面上的正投影位于所述引线图案在所述第二表面上的正投影内；A first lead group, the orthographic projection of the first lead group on the first surface is within the orthographic projection of the lead pattern on the first surface, and the first lead group is on the second surface The orthographic projection on the second surface is within the orthographic projection of the lead pattern on the second surface;
    第二引线组，用于连接所述第一引线组与所述第一绑定端子组和连接所述第一引线组与所述第二绑定端子组。The second lead group is used for connecting the first lead group and the first binding terminal group and connecting the first lead group and the second binding terminal group.
  9. 根据权利要求8所述的阵列基板，其特征在于，所述引线图案在所述侧面所在平面上的正投影位于所述第一引线组在所述侧面所在平面上的正投影内。8. The array substrate according to claim 8, wherein the orthographic projection of the lead pattern on the plane where the side surface is located is within the orthographic projection of the first lead group on the plane where the side surface is located.
  10. 根据权利要求8所述的阵列基板，其特征在于，所述第二引线组在所述第一表面上的正投影与所述第一绑定端子组在所述第一表面上的正投影以及所述第一引线组在所述第一表面上的正投影至少部分重合，所述第二引线组在所述第二表面上的正投影与所述第二绑定端子组在所述第二表面上的正投影以及所述第一引线组在所述第二表面上的正投影至少部分重合。8. The array substrate according to claim 8, wherein the orthographic projection of the second lead group on the first surface and the orthographic projection of the first binding terminal group on the first surface and The orthographic projection of the first lead group on the first surface at least partially overlaps, the orthographic projection of the second lead group on the second surface and the second binding terminal group on the second The orthographic projection on the surface and the orthographic projection of the first lead group on the second surface at least partially overlap.
  11. 根据权利要求8所述的阵列基板，其特征在于，所述基板主体还包括衬底基板，所述衬底基板的所述侧面的棱角为圆角。8. The array substrate according to claim 8, wherein the main body of the substrate further comprises a base substrate, and the corners of the side surface of the base substrate are rounded.
  12. 根据权利要求8至10中任一项所述的阵列基板，其特征在于，所述第一绑定端子组与像素驱动电路层中的信号端连接，所述第二绑定端子组与驱动芯片连接。The array substrate according to any one of claims 8 to 10, wherein the first binding terminal group is connected to a signal terminal in the pixel driving circuit layer, and the second binding terminal group is connected to a driving chip connection.
  13. 一种显示面板，其特征在于，包括权利要求8-12任一项所述的阵列基板。A display panel, characterized by comprising the array substrate according to any one of claims 8-12.
  14. 一种拼接屏，其特征在于，至少包括两个权利要求13所述的显示面板。A splicing screen, characterized in that it comprises at least two display panels as claimed in claim 13.
PCT/CN2020/076364 2019-04-30 2020-02-24 Array substrate and fabrication method, display panel and splicing screen WO2020220805A1 (en)

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