CN110034026A - 封装件结构和方法 - Google Patents
封装件结构和方法 Download PDFInfo
- Publication number
- CN110034026A CN110034026A CN201811396075.0A CN201811396075A CN110034026A CN 110034026 A CN110034026 A CN 110034026A CN 201811396075 A CN201811396075 A CN 201811396075A CN 110034026 A CN110034026 A CN 110034026A
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- Prior art keywords
- layer
- via hole
- substrate
- conductive bump
- dielectric layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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Classifications
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- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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Abstract
在实施例中,一种器件包括:衬底,具有第一侧和与第一侧相对的第二侧;互连结构,与衬底的第一侧相邻;以及集成电路器件,附接到互连结构;导通孔,从衬底的第一侧延伸到衬底的第二侧,导通孔电连接到集成电路器件;凸块下金属(UBM),与衬底的第二侧相邻并且接触导通孔;导电凸块,位于凸块下金属上,导电凸块和凸块下金属是连续的导电材料,导电凸块与导通孔横向偏移;以及底部填充物,围绕凸块下金属和导电凸块。本发明的实施例还涉及封装件结构和方法。
Description
技术领域
本发明的实施例涉及封装件结构和方法。
背景技术
自从集成电路(IC)的发展以来,由于各种电子元件(即,晶体管、二极管、电阻器、电容器等)的集成密度的不断提高,半导体工业经历了持续的快速增长。在大多数情况下,集成密度的这些改进来自最小部件尺寸的反复减小,这允许将更多组件集成到给定区域中。
这些集成改进本质上基本上是二维的(2D),因为集成组件占据的区域基本上在半导体晶圆的表面上。集成电路的密度增加和相应的面积减小通常超过将集成电路芯片直接接合到衬底上的能力。已经使用中介层将球接触区域从芯片的球接触区域重新分布到中介层的更大区域。此外,中介层允许包括多个芯片的三维(3D)封装。还开发了其他封装件以结合3D方面。
发明内容
本发明的实施例提供了一种形成器件封装件的方法,包括:将集成电路器件附接到中介层的第一侧,所述中介层包括电连接到所述集成电路器件的导通孔;在所述中介层的第二侧上方沉积介电层;图案化所述介电层以暴露所述导通孔;在所述介电层上方形成第一掩模层,所述第一掩模层在所述导通孔上方具有第一图案;在所述第一掩模层的所述第一图案中镀凸块下金属(UBM);在所述凸块下金属和所述第一掩模层上形成第二掩模层,所述第二掩模层具有暴露所述凸块下金属的部分的第二图案;在所述第二掩模层的所述第二图案中镀导电凸块,所述导电凸块与所述导通孔横向偏移;以及去除所述第一掩模层和所述第二掩模层。
本发明的另一实施例提供了一种形成器件封装件的方法,包括:在中介层上形成介电层,所述中介层包括导通孔;在所述介电层中图案化开口;在所述开口中并且沿着所述介电层沉积晶种层;在所述晶种层上镀第一导电材料以形成沿着所述介电层并且穿过开口延伸的凸块下金属(UBM),利用所述晶种层镀所述第一导电材料;在所述第一导电材料上镀第二导电材料,以形成与所述导通孔横向偏移的导电凸块,利用所述晶种层镀所述第二导电材料。
本发明的又一实施例提供了一种半导体器件,包括:衬底,具有第一侧和与所述第一侧相对的第二侧;互连结构,与所述衬底的第一侧相邻;以及集成电路器件,附接到所述互连结构;导通孔,从所述衬底的第一侧延伸到所述衬底的第二侧,所述导通孔电连接到所述集成电路器件;凸块下金属(UBM),与所述衬底的第二侧相邻并且接触所述导通孔;导电凸块,位于所述凸块下金属上,所述导电凸块和所述凸块下金属是连续的导电材料,所述导电凸块与所述导通孔横向偏移;以及底部填充物,围绕所述凸块下金属和所述导电凸块。
附图说明
当结合附图进行阅读时,从以下详细描述可最佳理解本发明的各个方面。应该指出,根据工业中的标准实践,各个部件未按比例绘制。实际上,为了清楚的讨论,各个部件的尺寸可以任意地增大或减小。
图1是根据一些实施例的集成电路器件的截面图。
图2是根据一些实施例的晶圆的截面图。
图3至图18是根据一些实施例的在形成器件封装件的工艺期间的中间步骤的各种视图。
具体实施方式
以下公开内容提供了许多用于实现所提供主题的不同特征的不同实施例或实例。下面描述了组件和布置的具体实例以简化本发明。当然,这些仅仅是实例,而不旨在限制本发明。例如,以下描述中,在第二部件上方或者上形成第一部件可以包括第一部件和第二部件直接接触形成的实施例,并且也可以包括在第一部件和第二部件之间可以形成额外的部件,从而使得第一部件和第二部件可以不直接接触的实施例。此外,本发明可在各个实施例中重复参考标号和/或字符。该重复是为了简单和清楚的目的,并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
而且,为便于描述,在此可以使用诸如“在…之下”、“在…下方”、“下部”、“在…之上”、“上部”等空间相对术语,以描述如图所示的一个元件或部件与另一个(或另一些)原件或部件的关系。除了图中所示的方位外,空间相对术语旨在包括器件在使用或操作中的不同方位。装置可以以其它方式定向(旋转90度或在其它方位上),而本文使用的空间相对描述符可以同样地作出相应的解释。
根据一些实施例,形成凸块下金属(UBM)以使随后形成的导电连接件与中介层的导通孔横向偏移。还可以在UBM和中介层的主衬底之间形成缓冲层。因此可以减少在热测试期间由导电连接件施加在中介层上的力。此外,根据一些实施例,用于形成UBM的工艺可以使用单个灰化工艺,从而降低制造成本。
图1是根据一些实施例的集成电路器件50的截面图。集成电路器件50可以是逻辑管芯(例如,中央处理单元(CPU)、图形处理单元(GPU)、片上***(SoC)、微控制器等)、存储器管芯(例如,动态随机存取存储器(DRAM)管芯、静态随机存取存储器(SRAM)管芯等)、电源管理管芯(例如,电源管理集成电路(PMIC)管芯)、射频(RF)管芯、传感器管芯、微电子机械***(MEMS)管芯、信号处理管芯(例如,数字信号处理(DSP)管芯)、前端管芯(例如,模拟前端(AFE)管芯)等或它们的组合。集成电路器件50可以形成在晶圆中,该晶圆可以包括在后续步骤中被分割以形成多个集成电路器件50的不同器件区域。集成电路器件50包括衬底52和互连结构54。
衬底52可以包括体半导体衬底、绝缘体上半导体(SOI)衬底、多层半导体衬底等。衬底52的半导体材料可以是硅;锗;化合物半导体,包括硅锗、碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟;合金半导体,包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP;或它们的组合。也可以使用其他衬底,诸如多层或梯度衬底。衬底52可以是掺杂的或未掺杂的。诸如晶体管、电容器、电阻器、二极管等的器件可以形成在衬底52的有源表面(例如,面向上的表面)中和/或上。
在衬底52的有源表面上形成具有一个或多个介电层和相应的金属化图案的互连结构54。介电层可以是金属间化介电(IMD)层。IMD层可以通过本领域已知的任何合适的方法(诸如旋涂、化学气相沉积(CVD)、等离子体增强CVD(PECVD)、高密度等离子体化学气相沉积(HDP-CVD)等)由例如低K介电材料形成,诸如未掺杂的硅酸盐玻璃(USG)、磷硅酸盐玻璃(PSG)、硼磷硅酸盐玻璃(BPSG)、氟硅酸盐玻璃(FSG)、SiOxCy、旋涂玻璃、旋涂聚合物、硅碳材料、它们的化合物、它们的复合物、它们的组合等。介电层中的金属化图案可以在器件之间路由电信号,诸如通过使用通孔和/或迹线,并且还可以包含各种电子器件,诸如电容器、电阻器、电感器等。可以互连各种器件和金属化图案以执行一个或多个功能。这些功能可以包括存储器结构、处理结构、传感器、放大器、功率分配、输入/输出电路等。另外,诸如导电柱或接触焊盘的管芯连接件形成在互连结构54中和/或上,以提供至电路和器件的外部电连接。本领域普通技术人员将理解,提供上述实施例是为了说明的目的。可以根据给定的应用适当地使用其他电路。
虽然示出具有单个衬底52,但是应当理解,集成电路器件50可以包括多个衬底52。例如,集成电路器件50可以是堆叠器件,诸如混合存储器数据集(HMC)模块、高带宽存储器(HBM)模块等。在这样的实施例中,集成电路器件50包括通过通孔互连的多个衬底52。
图2是根据一些实施例的晶圆70的截面图。晶圆70包括多个器件区域100A和100B,其中将附接集成电路器件50以形成多个器件。形成在晶圆70中的器件可以是中介层、集成电路管芯等。晶圆70包括衬底72、导通孔74和互连结构76。
衬底72可以是体半导体衬底、SOI衬底、多层半导体衬底等。衬底72的半导体材料可以是硅;锗;化合物半导体,包括硅锗、碳化硅、砷化镓、磷化镓、磷化铟、砷化铟和/或锑化铟;合金半导体,包括SiGe、GaAsP、AlInAs、AlGaAs、GaInAs、GaInP和/或GaInAsP;或它们的组合。也可以使用其他衬底,例如多层或梯度衬底。衬底72可以是掺杂的或未掺杂的。在晶圆70中形成中介层的实施例中,衬底72中通常不包括有源器件,但是中介层可以包括在衬底72的前表面(例如,面向上的表面)中和/或上形成的无源器件。在集成电路管芯形成在晶圆70中的实施例中,诸如晶体管、电容器、电阻器、二极管等的器件可以形成在衬底72的前表面中和/或上。
导通孔74形成为从衬底72的前表面延伸到衬底72中。当衬底72是硅衬底时,导通孔74有时也被称为衬底通孔或硅通孔(TSV)。可以通过例如蚀刻、研磨、激光技术、它们的组合等在衬底72中形成凹槽来形成导通孔74。可以在凹槽中形成薄介电材料,例如通过使用氧化技术。薄阻挡层可以共形地沉积在衬底72的前侧上和开口中,例如通过CVD、原子层沉积(ALD)、物理气相沉积(PVD)、热氧化、它们的组合等。阻挡层可以由氮化物或氮氧化物形成,例如氮化钛、氮氧化钛、氮化钽、氮氧化钽、氮化钨、它们的组合等。可以在薄阻挡层上方和开口中沉积导电材料。导电材料可以通过电化学镀工艺、CVD、ALD、PVD、它们的组合等形成。导电材料的实例是铜、钨、铝、银、金、它们的组合等。通过例如化学机械抛光(CMP)从衬底72的前侧去除多余的导电材料和阻挡层。因此,导通孔74可以包括导电材料以及位于导电材料和衬底72之间的薄阻挡层。
互连结构76形成在衬底72的前表面上方,并且用于将集成电路器件(如果有的话)和/或导通孔74电连接在一起和/或电连接到外部器件。互连结构76可以包括一个或多个介电层和位于介电层中的相应的金属化图案。金属化图案可以包括通孔和/或迹线,以将任何器件和/或导通孔74互连在一起和/或与外部器件互连。介电层可以由氧化硅、氮化硅、碳化硅、氮氧化硅、低K介电材料形成,诸如PSG、BPSG、FSG、SiOxCy、旋涂玻璃、旋涂聚合物、硅碳材料、它们的化合物、它们的复合物、它们的组合等。可以通过本领域已知的任何合适的方法沉积介电层,诸如旋涂、CVD、PECVD、HDP-CVD等。可以在介电层中形成金属化图案,例如,通过使用光刻技术在介电层上沉积和图案化光刻胶材料,以暴露将成为金属化图案的介电层的部分。诸如各向异性干蚀刻工艺的蚀刻工艺可用于在介电层中产生对应于介电层的暴露部分的凹槽和/或开口。凹槽和/或开口可以衬有扩散阻挡层并且填充有导电材料。扩散阻挡层可以由通过ALD等沉积的一层或多层TaN、Ta、TiN、Ti、CoW等形成,并且导电材料可以由铜、铝、钨、银形成、它们的组合等形成并且可以通过CVD、PVD等沉积。可以去除介电层上的任何过量的扩散阻挡层和/或导电材料,例如通过使用CMP。
图3至图18是根据一些实施例的在形成器件封装件200的工艺期间的中间步骤的各种视图。图3至18是截面图。在图3至16中,通过将各种集成电路器件50接合到晶圆70的前侧来形成半导体器件100。在一个实施例中,半导体器件100是晶圆上芯片(CoW)封装件,但是应当理解,实施例可以应用于其他三维集成电路(3DIC)封装件。图17示出了所得到的半导体器件100。在图18中,通过将半导体器件100安装到衬底上而形成器件封装件200。在一个实施例中,器件封装件200是衬底上芯片上芯片(CoWoS)封装件,但是应当理解,实施例可以应用于其他3DIC封装件。
在图3中,多个集成电路器件50附接到互连结构76。集成电路器件50位于器件区域100A和100B中,其将在后续步骤中被分割以形成半导体器件100。集成电路器件50包括具有不同功能的多个器件50A和50B。器件50A和50B可以各自具有单个功能(例如,逻辑器件、存储器管芯等),或者可以具有多个功能(例如,SoC)。在一个实施例中,器件50A是诸如CPU的逻辑器件,而器件50B是诸如HBM模块的存储器器件。可以使用例如拾取和放置工具将集成电路器件50附接到互连结构76。
在所示的实施例中,集成电路器件50通过包括导电凸块102和104以及导电连接件106的连接而附接到互连结构76。导电凸块102和104由诸如铜、铝、金、镍、钯等、或它们的组合的导电材料形成,并且可以通过溅射、印刷、电镀、化学镀、CVD等形成。导电凸块102和104可以是无焊料的并且具有基本垂直的侧壁,并且可以称为凸块。导电凸块102电连接和物理连接到互连结构54,并且导电凸块104电连接和物理连接到互连结构76。导电连接件106接合导电凸块102和104。导电连接件106可以由诸如焊料的导电材料形成,并且可以通过诸如蒸发、电镀、印刷、焊料转移、球放置等的方法首先在导电凸块102或104上形成焊料层来形成。一旦形成焊料层,就可以实施回流工艺以将导电连接件106成形为期望的凸块形状。
在其他实施例中,集成电路器件50通过面对面接合附接到互连结构76。例如,可以使用混合接合、熔融接合、直接接合、电介质接合、金属接合等在不使用焊料的情况下附接互连结构54和76。此外,可以使用混合接合技术,例如,一些集成电路器件50可以通过导电连接件106接合到互连结构76,并且其他集成电路器件50可以通过面对面接合而接合到互连结构76。
在图4中,将底部填充材料108分配到集成电路器件50和互连结构76之间的间隙中。底部填充材料108围绕导电凸块102和104以及导电连接件106,并且可以沿着集成电路器件50的侧壁向上延伸。底部填充材料108可以是任何可接受的材料,例如聚合物、环氧树脂、模塑底部填充物等。底部填充材料108可以在集成电路器件50附接到互连结构76之后通过毛细管流动工艺形成,或者可以在附接集成电路器件50之前通过合适的沉积方法形成。
在图5中,在各种组件上形成密封剂110。密封剂110可以是模塑料、环氧树脂等,并且可以通过压缩模塑、传递模塑等施加。密封剂110可以形成在互连结构76上方,使得集成电路器件50和底部填充材料108被掩埋或覆盖。然后使密封剂110固化。在一些实施例中,减薄密封剂110,使得密封剂110和集成电路器件50的顶面齐平。
在图6中,翻转中间结构以准备处理衬底72的背侧。中间结构可以放置在载体衬底112或其他合适的支撑结构上以用于后续处理。例如,载体衬底112可以附接到密封剂110。中间结构可以通过释放层附接到载体衬底112。释放层可以由基于聚合物的材料形成,其可以与载体衬底112一起从上面的结构去除。在一些实施例中,载体衬底112是诸如体半导体或玻璃衬底的衬底,并且可以具有任何厚度,例如约300mm的厚度。在一些实施例中,释放层是基于环氧树脂的热释放材料,其在加热时失去其粘合性,例如光转换(LTHC)释放涂层。
在图7中,减薄衬底72以暴露导通孔74,使得导通孔74从衬底72的背侧突出。导通孔74的暴露可以在两步减薄工艺中完成。首先,可以实施研磨工艺直到暴露导通孔74。研磨工艺可以是例如CMP或其他可接受的去除工艺。在研磨工艺之后,衬底72的背侧和通孔74可以是齐平的。其次,可以实施凹进工艺以使导通孔74周围的衬底72凹进。凹进工艺可以是例如合适的回蚀刻工艺。
在图8中,绝缘层114形成在衬底72的背侧上,围绕导通孔74的突出部分。在一些实施例中,绝缘层114由含硅绝缘体形成,例如氮化硅、氧化硅、氧氮化硅等,并且可以通过适当的沉积方法形成,诸如旋涂、CVD、PECVD、HDP-CVD等。在沉积之后,可以实施诸如CMP的平坦化工艺以去除多余的电介质材料,使得绝缘层114和导通孔74的表面齐平。
在图9中,在绝缘层114和导通孔74上方形成介电层116。介电层116可以是光敏聚合物材料,例如聚苯并恶唑(PBO)、聚酰亚胺、苯并环丁烯(BCB)等,可以使用光刻掩模进行图案化。在其他实施例中,介电层116由诸如氮化硅的氮化物;诸如氧化硅、PSG、硼硅酸盐玻璃(BSG)、BPSG的氧化物等形成。介电层116可以通过旋涂、层压、CVD等或它们的组合形成。
然后图案化介电层116。图案化形成开口118的图案以暴露导通孔74的部分。图案化可以通过可接受的工艺,例如在介电层116是光敏材料时通过将介电层116暴露于光,或通过蚀刻,例如,使用各向异性蚀刻。如果介电层116是光敏材料,则可以在曝光之后显影介电层116。
在图10中,在介电层116上方和穿过介电层116的开口118中形成晶种层120。在一些实施例中,晶种层是金属层,其可以是单层或具有由不同材料形成的多个子层的复合层。在一些实施例中,晶种层包括钛层和位于钛层上方的铜层。可以使用例如PVD等形成晶种层。
在图11中,在晶种层120上方形成并且图案化第一光刻胶122。第一光刻胶122可以通过旋涂等形成,并且可以暴露于光以进行图案化。第一光刻胶122的图案对应于随后将形成的UBM。图案化形成穿过第一光刻胶122的开口124的图案,暴露出晶种层120的部分。开口124还暴露开口118,并且位于导通孔74上方。
在图12中,导电材料形成在第一光刻胶122的开口124中,晶种层120的暴露部分上。导电材料可以通过镀形成,例如电镀或化学镀等。导电材料可以是金属,如铜、钛、钨、铝等。导电材料和晶种层120的组合形成UBM 126。UBM 126具有穿过介电层116中的开口118延伸的通孔部分以接触晶种层120,并且具有沿着介电层116的顶面延伸的线部分。
在图13中,在UBM 126和第一光刻胶122上形成并且图案化第二光刻胶128。第二光刻胶128可以通过旋涂等形成,并且可以暴露于光以进行图案化。第二光刻胶128可以由与第一光刻胶122相同的材料形成。第二光刻胶128的图案对应于随后将形成的导电凸块。图案化形成穿过第二光刻胶128的开口130的图案,从而暴露部分UBM 126。
在图14中,在第二光刻胶128的开口130中、UBM 126的暴露部分上形成导电材料,从而形成导电凸块132。导电材料可以通过镀形成,例如电镀或化学镀等。导电材料可以是金属,如铜、钛、钨、铝等。因为UBM126通过开口130暴露,所以在开口130中没有形成晶种层。相反,导电材料直接且物理地形成在UBM 126上。通过实施具有与用于形成UBM 126的导电材料的镀工艺相同的工艺参数的镀工艺来形成导电材料。值得注意的是,在UBM 126和导电凸块132之间没有形成晶种层。相反,导电凸块132的导电材料通过实施使用晶种层120的镀工艺形成。
此外,在第二光刻胶128的开口130中的导电凸块132上形成可回流材料134。可回流材料134是诸如焊料、锡、银等的材料,并且可以通过、镀、蒸发、电镀、印刷、焊料转移等形成。因为在UBM 126和导电凸块132之间没有形成晶种层,所以导电凸块132是从UBM 126连续延伸到可回流材料134的导电材料。
在图15中,通过可接受的灰化或剥离工艺(例如使用氧等离子体等)去除第一光刻胶122和第二光刻胶128。值得注意的是,第一光刻胶122和第二光刻胶128在相同的去除工艺中被去除,在去除第二光刻胶128和去除第一光刻胶122之间没有中间步骤。在相同工艺中去除两个光刻胶允许降低去除成本。一旦去除光刻胶,就去除晶种层120的暴露部分,例如通过使用可接受的蚀刻工艺,例如通过湿蚀刻或干蚀刻。
此外,可以实施回流以将可回流材料134成形为期望的凸块形状,从而形成导电连接件136。导电连接件136可以是球栅阵列(BGA)连接件、焊球、可控塌陷芯片连接(C4)凸块等。
UBM 126使导电凸块132和导电连接件136与导通孔74横向偏移。换句话说,导电凸块132和导电连接件136沿第一轴对齐,并且导通孔74沿着不同的第二轴对齐。此外,介电层116的聚合物材料用作绝缘层114和UBM 126之间的缓冲层。在热测试期间,器件可以循环加热和冷却,导致导电连接件136的反复膨胀和收缩。缓冲层吸收来自导电连接件136的膨胀的力,从而减少热测试期间的互连结构76的各个层中破裂和/或分层的机会。此外,根据一些实施例,UBM 126和导电凸块132仅使用一个晶种层、一个光刻胶去除工艺和一个晶种层去除工艺形成。因此可以降低UBM 126和缓冲介电层116的制造成本。
在图16中,实施载体脱粘以将载体衬底112与密封剂110分离(脱粘)。根据一些实施例,脱粘包括在释放层上投射诸如激光或者紫外(UV)光的光,使得释放层在光的热量下分解,并且可以去除载体衬底112。然后翻转该结构并放置在胶带(未示出)上。随后,沿着划线区域138在相邻的器件区域100A和100B之间分割晶圆70,以形成半导体器件100。分割可以通过锯切、切割等。
图17示出了在分割之后得到的半导体器件100。在分割工艺期间,形成中介层140,其包括晶圆70、绝缘层114、介电层116和UBM 126的分割部分。每个半导体器件100具有中介层140。作为分割工艺的结果,中介层140和密封剂110的边缘是共末端的。换句话说,中介层140的外侧壁具有与密封剂110的外侧壁相同的宽度。
在图18中,通过将半导体器件100安装到封装衬底202来形成器件封装件200。封装衬底202可以由诸如硅、锗等的半导体材料制成。或者,也可以使用诸如硅锗、碳化硅、砷化镓、砷化铟、磷化铟、碳化硅锗、磷化镓砷、磷化镓铟、它们的组合等的化合物材料。另外,封装衬底202可以是SOI衬底。通常,SOI衬底包括半导体材料层,例如外延硅、锗、硅锗、SOI或它们的组合。在一个可选实施例中,封装衬底202基于绝缘芯,例如玻璃纤维增强树脂芯。一种示例芯材料是玻璃纤维树脂,例如FR4。芯材料的替代物包括双马来酰亚胺-三嗪(BT)树脂,或者可选地,其他印刷电路板(PCB)材料或膜。诸如味之素积层膜(ABF)或其他层压板的构建膜可用于封装衬底202。
封装衬底202可以包括有源和无源器件。如本领域普通技术人员将认识到的,可以使用诸如晶体管、电容器、电阻器、这些的组合等的各种各样的器件来产生器件封装件200的设计的结构和功能要求。可以使用任何合适的方法形成器件。
封装衬底202还可以包括金属化层和通孔以及位于金属化层和通孔上方的接合焊盘204。金属化层可以形成在有源和无源器件上方,并且设计成连接各种器件以形成功能电路。金属化层可以由交替的介电层(例如,低k介电材料)和导电材料(例如,铜)形成,其中通孔互连导电材料的各个层并且可以通过任何合适的工艺(例如沉积、镶嵌、双镶嵌等)形成。在一些实施例中,封装衬底202基本上没有有源和无源器件。
回流导电连接件136以将半导体器件100附接到接合焊盘204,从而将中介层140接合到封装衬底202。导电连接件136将封装衬底202(包括封装衬底202中的金属化层)电连接和物理连接到半导体器件100。在一些实施例中,无源器件(例如,表面安装器件(SMD),未示出)可以在安装在器件封装件200上之前之前附接到器件封装件200(例如,接合到接合焊盘204)。在这样的实施例中,无源器件可以接合到第二器件封装件200的与导电连接件136相同的表面。
导电连接件136可在其回流之前在其上形成环氧树脂焊剂,其中在半导体器件100附接到封装衬底202之后剩余环氧树脂焊剂的至少一些环氧树脂部分。该剩余的环氧树脂部分可以用作底部填充物,以减少应力并保护由回流导电连接件136所产生的接头。
底部填充物206可以形成在半导体器件100和封装衬底202之间,围绕导电连接件136、导电凸块132和UBM 126。由于形成UBM 126的工艺,UBM 126在形成之后不被介电层或绝缘层围绕。这样,底部填充物206直接接触UBM 126并且沿着UBM 126的侧壁延伸。此外,底部填充物206是从封装衬底202延伸到介电层116的连续材料。底部填充物206可以在附接半导体器件100之后通过毛细管流动工艺形成,或者可以在附接半导体器件100之前通过合适的沉积方法形成。
可选地,散热器可以附接到器件封装件200,覆盖并且围绕半导体器件100。散热器可以由具有高导热率的材料形成,例如钢、不锈钢、铜等或它们的组合。散热器保护半导体器件100并且形成热路径以传导来自器件封装件200的各种部件的热量。
实施例可以实现许多优势。通过使用UBM 126使导电连接件136与导通孔74横向偏移,导电连接件136在热测试(例如,膨胀)期间不会在导通孔74上施加力。此外,介电层116用作UBM 126的缓冲层。结果,可以减少热测试期间的互连结构76的各个层中破裂和/或分层的可能性。此外,因为UBM 126和导电凸块132仅使用一个晶种层、一个光刻胶去除工艺和一个晶种层去除工艺形成,所以可以降低制造成本。
在一个实施例中,一种方法包括:将集成电路器件附接到中介层的第一侧,该中介层包括电连接到集成电路器件的导通孔;在中介层的第二侧上方沉积介电层;图案化介电层以暴露导通孔;在介电层上方形成第一掩模层,第一掩模层在导通孔上方具有第一图案;在第一掩模层的第一图案中镀凸块下金属(UBM);在凸块下金属和第一掩模层上形成第二掩模层,第二掩模层具有暴露凸块下金属的部分的第二图案;在第二掩模层的第二图案中镀导电凸块,导电凸块与导通孔横向偏移;以及去除第一掩模层和第二掩模层。
在该方法的一些实施例中,在相同的去除工艺中去除第一掩模层和第二掩模层。在一些实施例中,该方法还包括:在集成电路器件和中介层之间形成底部填充材料。在一些实施例中,该方法还包括:用模塑料包封集成电路器件和底部填充材料,模塑料和中介层是共末端的。在该方法的一些实施例中,图案化介电层形成暴露导通孔的第一开口,并且还包括:在介电层上方和第一开口中沉积晶种层,第一掩模层形成在晶种层上方,第一个图案暴露晶种层。在该方法的一些实施例中,在凸块下金属和导电凸块之间没有形成晶种层。在该方法的一些实施例中,用第一镀工艺镀凸块下金属,用第二镀工艺镀导电凸块,第一镀工艺和第二镀工艺用相同的镀工艺参数实施。在一些实施例中,该方法还包括:在第二掩模层的第二图案中的导电凸块上镀可回流材料。在一些实施例中,该方法还包括:在去除第一掩模层和第二掩模层之后,回流可回流材料以在导电凸块上形成导电连接件。
在一个实施例中,一种方法包括:在中介层上形成介电层,该中介层包括导通孔;在介电层中图案化开口;在开口中并且沿着介电层沉积晶种层;在晶种层上镀第一导电材料以形成沿着介电层并且穿过开口延伸的凸块下金属(UBM),利用晶种层镀第一导电材料;在第一导电材料上镀第二导电材料,以形成与导通孔横向偏移的导电凸块,利用晶种层镀第二导电材料。
在一些实施例中,该方法还包括:在介电层上方形成第一掩模层,第一掩模层具有暴露晶种层的第一图案,第一导电材料镀在第一图案中;在凸块下金属和第一掩模层上方形成第二掩模层,第二掩模层具有暴露部分凸块下金属的第二图案,第二导电材料镀在第二图案中。在一些实施例中,该方法还包括:在相同的去除工艺中去除第一掩模层和第二掩模层。在该方法的一些实施例中,在镀第二导电材料之前,在凸块下金属上没有形成晶种层。在一些实施例中,该方法还包括:利用导电连接件将导电凸块接合到封装衬底;以及形成围绕凸块下金属、导电凸块和导电连接件的底部填充物。
在一个实施例中,一种器件包括:衬底,具有第一侧和与第一侧相对的第二侧;互连结构,与衬底的第一侧相邻;以及集成电路器件,附接到互连结构;导通孔,从衬底的第一侧延伸到衬底的第二侧,导通孔电连接到集成电路器件;凸块下金属(UBM),与衬底的第二侧相邻并且接触导通孔;导电凸块,位于凸块下金属上,导电凸块和凸块下金属是连续的导电材料,导电凸块与导通孔横向偏移;以及底部填充物,围绕凸块下金属和导电凸块。
在器件的一些实施例中,底部填充物接触凸块下金属的侧面和导电凸块的侧面。在一些实施例中,该器件还包括:与衬底的第二侧相邻的介电层,凸块下金属延伸穿过介电层。在一些实施例中,该器件还包括:晶种层,延伸穿过介电层以接触导通孔,凸块下金属接触晶种层,其中在导电凸块和凸块下金属之间没有晶种层。在一些实施例中,该器件还包括:封装衬底;以及导电连接件,将封装衬底接合到导电凸块,底部填充物围绕导电连接件。在器件的一些实施例中,底部填充物是从封装衬底延伸到介电层的连续材料。
上面概述了若干实施例的特征,使得本领域人员可以更好地理解本发明的方面。本领域人员应该理解,它们可以容易地使用本发明作为基础来设计或修改用于实施与本文所介绍实施例相同的目的和/或实现相同优势的其它工艺和结构。本领域技术人员也应该意识到,这种等同构造并不背离本发明的精神和范围,并且在不背离本发明的精神和范围的情况下,本文中它们可以做出多种变化、替换以及改变。
Claims (10)
1.一种形成器件封装件的方法,包括:
将集成电路器件附接到中介层的第一侧,所述中介层包括电连接到所述集成电路器件的导通孔;
在所述中介层的第二侧上方沉积介电层;
图案化所述介电层以暴露所述导通孔;
在所述介电层上方形成第一掩模层,所述第一掩模层在所述导通孔上方具有第一图案;
在所述第一掩模层的所述第一图案中镀凸块下金属(UBM);
在所述凸块下金属和所述第一掩模层上形成第二掩模层,所述第二掩模层具有暴露所述凸块下金属的部分的第二图案;
在所述第二掩模层的所述第二图案中镀导电凸块,所述导电凸块与所述导通孔横向偏移;以及
去除所述第一掩模层和所述第二掩模层。
2.根据权利要求1所述的方法,其中,在相同的去除工艺中去除所述第一掩模层和所述第二掩模层。
3.根据权利要求1所述的方法,还包括:
在所述集成电路器件和所述中介层之间形成底部填充材料。
4.根据权利要求3所述的方法,还包括:
用模塑料包封所述集成电路器件和所述底部填充材料,所述模塑料和所述中介层是共末端的。
5.根据权利要求1所述的方法,其中,图案化所述介电层形成暴露所述导通孔的第一开口,并且还包括:
在所述介电层上方和所述第一开口中沉积晶种层,所述第一掩模层形成在所述晶种层上方,所述第一个图案暴露所述晶种层。
6.根据权利要求1所述的方法,其中,在所述凸块下金属和所述导电凸块之间没有形成晶种层。
7.根据权利要求1所述的方法,其中,用第一镀工艺镀所述凸块下金属,用第二镀工艺镀所述导电凸块,所述第一镀工艺和所述第二镀工艺用相同的镀工艺参数实施。
8.根据权利要求1所述的方法,还包括:
在所述第二掩模层的所述第二图案中的所述导电凸块上镀可回流材料。
9.一种形成器件封装件的方法,包括:
在中介层上形成介电层,所述中介层包括导通孔;
在所述介电层中图案化开口;
在所述开口中并且沿着所述介电层沉积晶种层;
在所述晶种层上镀第一导电材料以形成沿着所述介电层并且穿过开口延伸的凸块下金属(UBM),利用所述晶种层镀所述第一导电材料;
在所述第一导电材料上镀第二导电材料,以形成与所述导通孔横向偏移的导电凸块,利用所述晶种层镀所述第二导电材料。
10.一种半导体器件,包括:
衬底,具有第一侧和与所述第一侧相对的第二侧;
互连结构,与所述衬底的第一侧相邻;以及
集成电路器件,附接到所述互连结构;
导通孔,从所述衬底的第一侧延伸到所述衬底的第二侧,所述导通孔电连接到所述集成电路器件;
凸块下金属(UBM),与所述衬底的第二侧相邻并且接触所述导通孔;
导电凸块,位于所述凸块下金属上,所述导电凸块和所述凸块下金属是连续的导电材料,所述导电凸块与所述导通孔横向偏移;以及
底部填充物,围绕所述凸块下金属和所述导电凸块。
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US20210210399A1 (en) | 2021-07-08 |
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US10957616B2 (en) | 2021-03-23 |
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