CN109994421B - 形成接触洞的方法 - Google Patents

形成接触洞的方法 Download PDF

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CN109994421B
CN109994421B CN201711470650.2A CN201711470650A CN109994421B CN 109994421 B CN109994421 B CN 109994421B CN 201711470650 A CN201711470650 A CN 201711470650A CN 109994421 B CN109994421 B CN 109994421B
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layer
oxide layer
mask
metal oxide
contact hole
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CN109994421A (zh
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张峰溢
邹世芳
李甫哲
蒋欣妤
陈昱磬
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Fujian Jinhua Integrated Circuit Co Ltd
United Microelectronics Corp
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United Microelectronics Corp
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Abstract

本发明公开一种形成接触洞的方法，包含提供一导电线，一掩模层覆盖并接触导电线，一高介电常数层覆盖并接触掩模层，一第一氧化硅层覆盖并接触高介电常数层，其中高介电常数层包含一第一金属氧化物层、一第二金属氧化物层和一第三金属氧化物层由下至上堆叠，接着进行一干蚀刻，蚀刻第一氧化硅层、高介电常数层和掩模层直至曝露出导电线，以形成一接触洞，最后进行一湿蚀刻，蚀刻第一氧化硅层、第三金属氧化物层和第二金属氧化物层并且保留第一金属氧化物层，以扩大接触洞。

Description

形成接触洞的方法
技术领域
本发明涉及一种形成接触洞的方法，特别是涉及一种先用干蚀刻形成接触洞，再用湿蚀刻扩大接触洞孔径的制作方法。
背景技术
集成电路的流程非常复杂，基本上大致可分为芯片的制造、集成电路的制作与集成电路的封装，半导体工业因为技术的提升而朝向将元件的尺寸缩小迈进，将各种电子元件及线路缩小并制作更小的面积上，在集成电路体制作工艺目前趋向于多重内连线的制作，为了达到不同膜层间的电性接触，接触洞的制作是必要的制作步骤。
接触洞是在层间介电层(inter-layer dielectric；ILD)内挖开通下方底材做连接金属导电线路的通路。随着集成电路的线宽不断地缩小，这使得接触洞的制作越来越困难，特别是高深宽比的开口，难度日益升高，举例而言，在蚀刻接触洞时，由于接触洞的孔径和下方底材的宽度接近，因此些许偏移就会造成接触洞错过下方底材，进而连通到更下方的线路。
由此可知，现有技术关于形成接触洞的方法仍有诸多缺点待改善。
发明内容
有鉴于此，本发明提供数种形成接触洞的方法，以克服上述缺点。
根据本发明的第一优选实施例，一种形成接触洞的方法，包含提供一导电线，一掩模层覆盖并接触导电线，一高介电常数层覆盖并接触掩模层，一第一氧化硅层覆盖并接触高介电常数层，其中高介电常数层包含一第一金属氧化物层、一第二金属氧化物层和一第三金属氧化物层由下至上堆叠，接着进行一干蚀刻，蚀刻第一氧化硅层、高介电常数层和掩模层直至曝露出导电线，以形成一接触洞，最后进行一湿蚀刻，蚀刻第一氧化硅层、第三金属氧化物层和第二金属氧化物层并且保留第一金属氧化物层，以扩大接触洞。
根据本发明的第二优选实施例，一种形成接触洞的方法，包含：提供一导电线，一掩模层覆盖并接触导电线，一高介电常数层覆盖并接触掩模层，一第一氧化硅层覆盖并接触高介电常数层，其中高介电常数层仅包含一金属氧化层，然后进行一干蚀刻，蚀刻第一氧化硅层、高介电常数层和掩模层直至曝露出导电线，以形成一接触洞，最后进行一湿蚀刻，蚀刻第一氧化硅层、高介电常数层，以扩大接触洞。
根据本发明的第三优选实施例，一种形成接触洞的方法，包含：
提供一导电线，一掩模层覆盖并接触导电线，一氧化硅层覆盖并接触掩模层，接着进行一干蚀刻，蚀刻氧化硅层和掩模层直至曝露出导电线，以形成一接触洞，最后进行一湿蚀刻，蚀刻氧化硅层以扩大接触洞。
附图说明
图1至图3、图6至图8和图11为本发明的第一优选实施例所绘示的形成接触洞的方法示意图，其中：
图2为接续图1的步骤示意图；
图3为本发明的第一优选实施例所绘示的图2中圆圈区域的放大图；
图6为接续图2的步骤示意图；
图7为接续图6的步骤示意图；
图8为本发明的第一优选实施例所绘示的图7中圆圈区域的放大图；
图11为第一优选实施例中接续图8的步骤示意图。
图4、图9和图12为本发明的第二优选实施例所绘示的形成接触洞的方法示意图，其中：
图4为本发明的第二优选实施例所绘示的图2中圆圈区域的放大图；
图9为本发明的第二优选实施例所绘示的图7中圆圈区域的放大图；
图12为第二优选实施例中接续图9的步骤示意图。
图5、图10和图13为本发明的第三优选实施例所绘示的形成接触洞的方法示意图，其中：
图5为本发明的第三优选实施例所绘示的图2中圆圈区域的放大图；
图10为本发明的第三优选实施例所绘示的图7中圆圈区域的放大图；
图13为第三优选实施例中接续图10的步骤示意图。
主要元件符号说明
10 介电层 12 电容插塞
14 导电线 16 电容下电极
18 掩模层 20 高介电常数层
20a 第一金属氧化物层 20b 第二金属氧化物层
20c 第三金属氧化物层 22 电容上电极
24 保护层 26 电容
28 蚀刻掩模 30 圆圈区域
32 第一氧化硅层 34 蚀刻掩模
36 接触洞图案 37 圆圈区域
38 接触洞 40 第二氧化硅层
D 孔径 D1 孔径
D2 孔径
具体实施方式
如图1所示，首先提供一介电层10，介电层10中设置有电容插塞12，以及一导电线14，例如为一金属插塞，介电层10上设置有一电容下电极16，一掩模层18覆盖在部分介电层10上并且延伸至导电线14之上以覆盖导电线14，一高介电常数层20顺应的覆盖电容下电极16并且延伸至导电线14之上以覆盖导电线14，一电容上电极22覆盖高介电常数层20并且延伸至导电线14之上以覆盖导电线14，一保护层24覆盖电容上电极22并且延伸至导电线14之上以覆盖导电线14，电容插塞12电连结电容下电极16。电容下电极16、高介电常数层20和电容上电极22共同组成电容26。
介电层10可以为氮化硅、氧化硅、氮氧化硅(SiON)等绝缘的材料，掩模层18可以为氮化硅或是氮碳化硅等绝缘的材料，若使用氮碳化硅，则氮碳化硅中的含碳量较佳介于5原子百分比至40原子百分比之间，电容上电极22和电容下电极16可以为铂、钨、氮化钨、氮化钛或是氮化钽等导电材料，保护层24可以包含硅锗、钨或氧化硅。
根据本发明的第一和第二优选实施例，高介电常数层20包含了一第一金属氧化物层、一第二金属氧化物层和一第三金属氧化物层由下至上堆叠，第一金属氧化物层较佳为氧化锆，第二金属氧化物层为氧化铝，第三金属氧化物层为氧化锆，也就是说第一金属氧化物层和第三金属氧化物层为相同材料。
如图2所示，形成一蚀刻掩模28覆盖电容26和未覆盖电容下电极16的部分的掩模层18、高介电常数层20、电容上电极22和保护层24，此时在导电线14正上方的掩模层18、高介电常数层20、电容上电极22和保护层24未被蚀刻掩模28覆盖，接着移除未被蚀刻掩模28覆盖的保护层24、电容上电极22，并且选择性的移除部分的高介电常数层20。图2中以一圆圈区域30标示导电线14和其上方的掩模层18和高介电常数层20的位置，后续图3、图4和图5中所绘示的为圆圈区域30的放大图。
图3为本发明的第一优选实施例所绘示的图2中圆圈区域的放大图。图4为本发明的第二优选实施例所绘示的图2中圆圈区域的放大图，图5为本发明的第三优选实施例所绘示的图2中圆圈区域的放大图。根据本发明的第一优选实施例，请同时参阅图2和图3，如前文所述，高介电常数层20中包含有第一金属氧化物层20a、一第二金属氧化物层20b和一第三金属氧化物层20c由下至上堆叠，接着以蚀刻掩模28为掩模蚀刻保护层24、电容上电极22，并且以高介电常数层20中的第三金属氧化物层20c作为停止层，详细来说高介电常数层20的第三金属氧化物层20c被保留，但保留的第三金属氧化物层20c的表面在蚀刻时被损伤。根据本发明的第二优选实施例，请同时参阅图2和图4，以蚀刻掩模28为掩模蚀刻保护层24、电容上电极22，并且以高介电常数层20中的第一金属氧化物层20a作为停止层，也就是说高介电常数层20中的第三金属氧化物层20c和第二金属氧化物层20b都被移除，而且留下的第一金属氧化物层20a的表面在蚀刻时被损伤。根据第三优选实施例，蚀刻掩模28未覆盖区域的高介电常数层20被全部移除，请同时参阅图2和图5，以蚀刻掩模28为掩模蚀刻时，因为没有高介电常数层20，所以是以掩模层18作为停止层。
图6为接续图2的步骤，如图6所示，先移除蚀刻掩模28，然后形成一第一氧化硅层32覆盖并接触高介电常数层20，然后在第一氧化硅层32上形成一蚀刻掩模34覆盖第一氧化硅层32，蚀刻掩模34上有一接触洞图案36，然后，利用蚀刻掩模34为掩模，干蚀刻第一氧化硅层32、高介电常数层20和掩模层18直至曝露出导电线14以形成一接触洞38，接触洞具有一孔径D。图7为接续图6的步骤，如图7所示，移除蚀刻掩模34，举例而言，可利用氧气氧化蚀刻掩模34以去除蚀刻掩模34，在移除蚀刻掩模34的过程中，部分的掩模层18会被氧化而形成一第二氧化硅层，图7中以一圆圈区域37标示导电线14和其上方的掩模层18、高介电常数层20以及接触洞38的位置，后续图8、图9和图10分别为依据第一、第二和第三优选实施例所绘示的圆圈区域37的放大图，为了使图7简单明了，将第二氧化硅层的位置绘示在图8、图9和图10中。
图8根据本发明的第一优选实施例所绘示的图7中圆圈区域的放大图、图9根据本发明的第二优选实施例所绘示的图7中圆圈区域的放大图，图10根据本发明的第三优选实施例所绘示的图7中圆圈区域的放大图。根据本发明的第一优选实施例，请同时参阅图7和图8，在蚀刻掩模34移除后，部分的掩模层18被氧化成为第二氧化硅层40围绕接触洞38。根据本发明的第二优选实施例，请同时参阅图7和图9，在蚀刻掩模34移除后，部分的掩模层18被氧化成为第二氧化硅层40围绕接触洞38。根据本发明的第三优选实施例，请同时参阅图7和图10，在蚀刻掩模34移除后，部分的掩模层18被氧化成为第二氧化硅层40围绕接触洞38。在第一优选实施例、第二优选实施例和第三优选实施例中，掩模层18可以为氮化硅或是氮碳化硅，其差别在于若是使用氮化硅，其所形成的第二氧化硅层40会较使用氮碳化硅所形成的第二氧化硅层薄。而氮碳化硅中含碳的百分比也会影响第二氧化硅层的厚度，若是含碳量越高，其所形成的第二氧化硅层40的厚度越厚。
图11为依据第一优选实施例中接续图8的步骤，在移除蚀刻掩模34后，进行一湿蚀刻以扩大接触洞38，根据第一优选实施例，由于在图2的步骤中第三金属氧化物层20c的表面已被损伤，所以在湿蚀刻时，蚀刻剂能够移除受损的第三金属氧化物层20c但不能移除未受损的第一金属氧化物层20a，另外蚀刻剂原本就可以移除第二金属氧化物层20b和氧化硅，所以在湿蚀刻后由掩模层18转变成的第二氧化硅层40完全被移除，但掩模层18不会被移除，湿蚀刻较佳使用稀释的氢氟酸，此外第一氧化硅层32不但厚度变薄，原本定义接触洞38侧壁的第一氧化硅层32也被部分移除，使得在第一氧化硅层32中的接触洞孔径扩大，再者，由于部分的第一氧化硅层32被移除，所以部分的第三金属氧化物层20c曝露出来，因此也会被蚀刻剂移除，而移除了第三金属氧化物层20c后曝露出第二金属氧化物层20b因此也会被蚀刻剂移除，最后只剩下第一金属氧化物层20a中的接触洞维持原始的孔径D，在第一氧化硅层32、第三金属氧化物20c、第二金属氧化物层20b和掩模层18中的接触洞的孔径都从原本孔径D被扩大，值得注意的是在第一氧化硅层32、第三金属氧化物20c、第二金属氧化物层20b和掩模层18中的孔径可以彼此不同，也可以相同。一般而言，在掩模层18中的接触洞的孔径扩大的程度会比在第一氧化硅层32中的接触洞的孔径扩大的程度小，根据本发明的优选实施例，在第一氧化硅层32、第三金属氧化物20c和第二金属氧化物层20b中的孔径D1彼此相同，并且大于原始孔径D，在掩模层18中的接触洞的孔径D2小于孔径D1。
图12为依据第二优选实施例中接续图9的步骤，在移除蚀刻掩模34后，进行一湿蚀刻以扩大接触洞38，湿蚀刻较佳使用稀释的氢氟酸，根据第二优选实施例，由于在图2的步骤中第三金属氧化物层20c和第二金属氧化物层20b都已被移除，高介电常数层20中只剩下表面受损的第一金属氧化物层20a，所以在湿蚀刻时部分的第一氧化硅层32被移除后，曝露出部分的第一金属氧化物层20a，因此曝露的第一金属氧化物层20a也被移除，另外由掩模层18转变的第二氧化硅层40也完全被移除，但掩模层18不会被移除，最后在第一氧化硅层32、第一金属氧化物层20a和掩模层18中的接触洞38的孔径都被扩大，值得注意的是在第一氧化硅层32、第一金属氧化物层20a和掩模层18的孔径可以彼此不同，也可以相同。在图12中以在第一氧化硅层32和第一金属氧化物层20a中的孔径彼此相同，都被扩大为孔径D1为例，此外通常在掩模层18中的孔径D2会小于孔径D1，但大于原始的孔径D。
图13为依据第三优选实施例中接续图10的步骤，在移除蚀刻掩模34后，进行一湿蚀刻以扩大接触洞38，湿蚀刻较佳使用稀释的氢氟酸，在第三优选实施例中，原本就没有设置高介电常数层20，在湿蚀刻时由掩模层18转变的第二氧化硅层40完全被移除，但掩模层18不会被移除，此时部分的第一氧化硅层32也被移除，也就是说在第一氧化硅层32和掩模层中18的接触洞38的孔径都被扩大，值得注意的是在第一氧化硅层32和掩模层18的孔径可以彼此不同，也可以相同，在图13中以在第一氧化硅层32中的孔径D1大于和在掩模层18中的孔径D2为例。
本发明利用干蚀刻先形成一较小孔径的接触洞，之后再利用湿蚀刻将孔径扩大，使得后续接触插塞的半径增加，以降低阻值，由于干蚀刻时特意蚀刻出较小的孔径，因此对于干蚀刻过程中所发生的偏移和误差容许度较大，可以降低干蚀刻时接触洞超出导电线范围的情形。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (6)

1.一种形成接触洞的方法，其特征在于，包含：
提供一导电线，一掩模层覆盖并接触该导电线，一高介电常数层覆盖并接触该掩模层，一第一氧化硅层覆盖并接触该高介电常数层，其中该高介电常数层包含一第一金属氧化物层、一第二金属氧化物层和一第三金属氧化物层由下至上堆叠；
进行一干蚀刻，蚀刻该第一氧化硅层、该高介电常数层和该掩模层直至曝露出该导电线，以形成一接触洞；以及
进行一湿蚀刻，蚀刻该第一氧化硅层、该第三金属氧化物层和该第二金属氧化物层并且保留该第一金属氧化物层，以扩大该接触洞。
2.如权利要求1所述的形成接触洞的方法，其中该第一金属氧化物层为氧化锆，第二金属氧化物层为氧化铝，第三金属氧化物层为氧化锆。
3.如权利要求1所述的形成接触洞的方法，另包含：
进行该干蚀刻之前，形成一蚀刻掩模覆盖该第一氧化硅层；
进行该干蚀刻时，利用该蚀刻掩模为掩模，蚀刻该第一氧化硅层、该高介电常数层和该掩模层以形成该接触洞；以及
在该湿蚀刻之前，形成该接触洞之后，移除该蚀刻掩模。
4.如权利要求3所述的形成接触洞的方法，其中该掩模层为氮碳化硅，在进行移除该蚀刻掩模时，部分的该掩模层同时被氧化成一第二氧化硅层，并且在进行该湿蚀刻时，移除该第二氧化硅层。
5.如权利要求4所述的形成接触洞的方法，其中该掩模层的碳含量介于5原子百分比至40原子百分比之间。
6.如权利要求3所述的形成接触洞的方法，其中该掩模层为氮化硅，在进行移除该蚀刻掩模时，部分的该氮化硅同时被氧化成一第二氧化硅层，并且在进行该湿蚀刻时，移除该第二氧化硅层。
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