CN109980017A - 一种新型sgt超级结mosfet结构 - Google Patents
一种新型sgt超级结mosfet结构 Download PDFInfo
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- 239000004065 semiconductor Substances 0.000 claims abstract description 36
- 230000005669 field effect Effects 0.000 claims abstract description 23
- 229910044991 metal oxide Inorganic materials 0.000 claims description 23
- 150000004706 metal oxides Chemical class 0.000 claims description 23
- 239000000126 substance Substances 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 16
- 239000000463 material Substances 0.000 claims description 12
- 230000005611 electricity Effects 0.000 claims description 7
- 230000015556 catabolic process Effects 0.000 description 17
- 239000002019 doping agent Substances 0.000 description 5
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 240000002853 Nelumbo nucifera Species 0.000 description 3
- 235000006508 Nelumbo nucifera Nutrition 0.000 description 3
- 235000006510 Nelumbo pentapetala Nutrition 0.000 description 3
- 230000004913 activation Effects 0.000 description 3
- 239000003795 chemical substances by application Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 240000007594 Oryza sativa Species 0.000 description 1
- 235000007164 Oryza sativa Nutrition 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 235000009566 rice Nutrition 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
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Abstract
本发明是一种沟槽金属‑氧化物‑半导体场效应晶体管(MOSFET)器件,包括屏蔽沟槽栅极结构和超级结结构的组合,在含有漂流区中交替的n‑掺杂和p‑掺杂立柱的外延层内。在一个示例中,栅极沟槽形成在n‑掺杂立柱中和n‑掺杂立柱上方,n‑掺杂立柱在相应的栅极沟槽底部附近和周围具有一个多余的电荷区域。由于栅极沟槽中的屏蔽电极,多余的电荷是平衡的。
Description
技术领域
本发明主要涉及金属-氧化物-半导体场效应晶体管(MOMSFET),更确切地说是一种改良的超级结器件及其制备方法。
背景技术
微处理器和存储器件等集成电路含有多个金属-氧化物-半导体场效应晶体管(MOSFET),提供基本的开关功能,以配置逻辑门、数据存储和功率开关等功能。功率MOSFET通常用于需要功率切换和功率放大的应用中。在一个功率MOSFET中,必须降低传导时的器件电阻(Rds-on),并且提高其击穿电压(BV)。在一个晶体管中,大多数的击穿电压(BV)由漂流区承载,漂流区轻掺杂,以便提供较高的击穿电压BV。然而,轻掺杂的漂流区也会产生很高的导通电阻(Rds-on)。换言之,导通电阻(Rds-on)和击穿电压(BV)相互竞争博弈。事实上,导通电阻Rds-on正比于BV2.5。也就是说,对于传统的晶体管来说,导通电阻(Rds-on)随着击穿电压(BV)的增大而急剧增大。
超级结器件结构实现了获得低导通电阻(Rds-on),同时保持很高的断开状态击穿电压(BV)的方法。超级结器件包括交替的p-型和n-型掺杂立柱,平行排布,在漂流区中相互连接起来。交替的p-型和n-型立柱在本质上是电荷平衡的。当漏极和源极之间加载反向偏压时,这些立柱相互耗尽(即水平地)在一个相对低的电压下,从而在垂直方向上承受很高的击穿电压。用于超级结器件的导通电阻(Rds-on)与击穿电压BV成正比地增大,比传统的半导体结构中增大得剧烈。因此,对于同样高的击穿电压(BV),超级结器件可以比传统的MOSFET器件的导通电阻(Rds-on)更低(或者说对于指定的导通电阻Rds-on,超级结器件比传统的MOSFET的击穿电压BV更高)。
屏蔽栅沟槽(SGT)MOSFET是另一种类型的功率MOS器件。由于它们具有很低的晶体管栅极至漏极电容Cgd、很低的导通电阻Rds-on以及很高的击穿电压BV等优势,因此它们比传统的MOSFET更加适合某些特殊应用。
正是在这样的背景下,提出了本发明的实施例。
发明内容
本发明为解决上述已有技术当中存在的问题,提供以下技术方案来实现。
一种金属-氧化物-半导体场效应晶体管器件,包含:
一个第一导电类型的漂流区,位于相同导电类型的重掺杂衬底上方;
一个第二导电类型的本体区,位于漂流区上方,第二导电类型与第一导电类型相反;
多个沟槽,位于本体区中,并延伸到漂流区内;
一个第一导电类型的重掺杂源极区,位于本体区中;以及
一个超级结结构,位于漂流区中,包括交替的第一导电类型的第一掺杂立柱以及平行排布的第二导电类型的第二掺杂立柱,其中第二掺杂立柱的每个立柱都位于两个相邻的沟槽之间,其中第一掺杂立柱的每个立柱都有一个多余的电荷浓度区,在多个沟槽中相应的一个沟槽附近和周围,其中交替的第一掺杂立柱和第二掺杂立柱都在漂流区中处于基本的电荷平衡。
优选地,其中多个沟槽中的每个沟槽的中心都在第一掺杂立柱的顶部,并且在两个相邻的第二掺杂立柱之间。
优选地,其中多个沟槽的每个沟槽都具有一个底部,端接在多余的电荷浓度区。
优选地,其中多个沟槽的每个沟槽宽度都不大于相应的第一掺杂立柱的宽度。
优选地,其中第一掺杂立柱具有在漂流区上变化的掺杂结构,其中底部区域上方和多余的电荷浓度区域下方的区域,具有比底部区域中净电荷浓度更低的净电荷浓度。
优选地,其中与第一掺杂立柱中的其他区域相比,相应的沟槽底部附近和周围的多余的电荷浓度区具有最大的掺杂浓度。
优选地,其中多个沟槽中的每个沟槽都内衬电介质材料,每个沟槽的顶部都有一个栅极电极,底部都有一个屏蔽电极。
优选地,其中多个沟槽中的每个沟槽都内衬电介质材料,每个沟槽的顶部都有一个栅极电极,并且电介质材料填充多个沟槽中每个沟槽的底部。
优选地,其中多余的电荷区域具有比第一掺杂立柱的其他部分高20%至50%的电荷浓度。
优选地,其中栅极沟槽的宽度与超级结间距的比值约为0.175。
一种金属-氧化物-半导体场效应晶体管器件,包括:
一个第一导电类型的漂流区,位于相同导电类型的重掺杂衬底上方;
一个第二导电类型的本体区,位于漂流区上方,第二导电类型与第一导电类型相反;
多个沟槽,位于本体区中,并延伸到漂流区内;
一个第一导电类型的重掺杂源极区,位于本体区中;以及
一个超级结结构,位于漂流区中,包括交替的第一导电类型的第一掺杂立柱以及平行排布的第二导电类型的第二掺杂立柱,其中第二掺杂立柱的每个立柱都位于两个相邻的沟槽之间,其中第一掺杂立柱和第二掺杂立柱中的每个立柱在沟槽底部下方延伸,其中交替的第一掺杂立柱和第二掺杂立柱都在漂流区中处于基本的电荷平衡。
优选地,其中多个沟槽的每个沟槽中心都在第一掺杂立柱上方,以及两个相邻的第二掺杂立柱之间。
优选地,其中多个沟槽中的每个沟槽都有一个底部,端接在相应的一个掺杂立柱的顶部。
优选地,其中多个沟槽中的每个沟槽宽度都小于第一掺杂立柱中相应的掺杂立柱的宽度。
优选地,其中第一掺杂立柱在漂流区上具有变化的掺杂结构,其中底部区域上方和顶部区域下方的区域具有比底部区域中净电荷浓度更低的净电荷浓度。
优选地,其中与第一掺杂立柱中的其他区域相比,相应的沟槽的底部附近和周围的第一掺杂立柱的顶部区域具有最大的净电荷掺杂浓度。
优选地,其中内衬电介质材料的多个沟槽中的每个沟槽都在顶部具有一个栅极电极,在底部具有一个屏蔽电极。
优选地,其中内衬电介质材料的多个沟槽中的每个沟槽都在顶部具有一个栅极电极,以及电介质材料填充多个沟槽中每个沟槽的底部。
一种超级结半导体器件,包括:
一个第一导电类型的漂流区,位于相同导电类型的重掺杂衬底上方;
一个第二导电类型的本体区,位于漂流区上方,第二导电类型与第一导电类型相反;以及
一个超级结结构,位于漂流区中,包括交替的第一导电类型的第一掺杂立柱以及平行排布的第二导电类型的第二掺杂立柱,其中第一掺杂立柱在漂流区上具有不同的掺杂结构,其中底部区域上方和上部区域下方的中间区域具有的净电荷浓度,低于底部区域和上部区域中净电荷浓度,其中交替的第一掺杂立柱和第二掺杂立柱都在漂流区中处于基本的电荷平衡。
优选地,其中第一掺杂立柱中每个立柱的底部区域、中间区域和上部区域都包括多个掺杂第一导电类型的外延层。
优选地,其中掺杂第一导电类型的中间区域中多个外延层的每个外延层的剂量,都低于底部区域和上部区域中每个外延层的剂量。
优选地,其中第一掺杂立柱中的每个掺杂立柱都包括一个在上部区域上方的顶部区域。
优选地,其中第一掺杂立柱的每个掺杂立柱的底部区域、中间区域、上部区域和顶部区域都包括掺杂第一导电类型的多个外延层,其中掺杂顶部区域中第一导电类型的多个外延层的每个外延层的剂量,高于底部区域、中间区域和上部区域中每个外延层的剂量。
优选地,其中第一掺杂立柱的每个立柱还包括一个在上部区域之上的顶部区域,其中掺杂顶部区域中第一导电类型的多个外延层的每个外延层剂量,都高于底部区域、中间区域和上部区域中每个外延层的剂量。
一种超级结半导体器件,包括:
一个漂流区,由一个位于漂流区中的超级结结构构成,包括交替的第一导电类型的第一掺杂立柱和平行排布的第二导电类型的第二掺杂立柱,其中第一掺杂立柱包括掺杂第一导电类型的多个外延层,在漂流区上具有变化的掺杂结构,其中底部区域上方和上部区域下方的中间区域中每个外延层的剂量,低于底部区域和上部区域中每个外延层的剂量,其中交替的第一掺杂立柱和第二掺杂立柱都在漂流区中处于基本的电荷平衡。
依据本发明的各个方面,与传统的超级结器件相比,在超级结器件中增加SGT结构可以降低15%左右的导通电阻Rds-on。
附图说明
图1表示依据本发明的各个方面,一个超级结器件的有源晶胞部分的剖面图;
图2表示依据本发明的各个方面,用于超级结器件漂流区的掺杂结构的剖面图;
图3表示依据本发明的各个方面,用于屏蔽栅沟槽(SGT)超级结器件的漂流区的掺杂结构的部分剖面图;
图4表示依据本发明的各个方面,一种SGT超级结器件配置示例的剖面图;
图5表示依据本发明的各个方面,一种超级结器件的配置示例的剖面图;
图6表示依据本发明的各个方面,另一种可选配置的平面栅超级结器件的剖面图。
具体实施方式
在以下详细说明中,参照附图,该附图形成了本发明的一部分,并且在其中表示出了可以实施本发明的图示特定实施例的方式。为方便起见,在特定的导电或净杂质载流子类型(p或p)之后使用+或-,通常指的是半导体材料中指定类型的净杂质载流子的相对浓度。一般而言,n+材料具有比n材料更高的n型净掺杂物(例如,电子)浓度,并且n材料具有比n材料更高的载流子浓度。与之类似,p+材料具有比p材料更高的p型净掺杂物(例如空穴)浓度,并且p材料具有比p材料更高的浓度。要注意的是,相关的是载流子的净浓度,而不一定是掺杂物。例如,材料可以重掺杂n-型掺杂物,但是如果材料也充分反向掺杂p-型掺杂物,那么仍然具有相对低的净载流子浓度。此处所用的掺杂物浓度小于1016/cm3可以认为是“轻掺杂”,掺杂物浓度大于1017/cm3可以认为是“重掺杂”。
为了尽可能地降低导通电阻Rds-on,本发明的各个方面提出了一种功率MOSFET的改良结构,在超级结器件中引入了一个屏蔽栅沟槽(SGT)结构。确切地说,SGT结构中的屏蔽电极提供了一种除了超级结结构之外额外的电荷平衡结构。这使得n立柱中的掺杂浓度较高,从而降低导通电阻Rds-on。
图1表示依据本发明的各个方面,超级结器件100的有源晶胞的一部分的剖面图。器件100的有源晶胞包括一个适当掺杂(例如n+)的衬底102,作为带有漏极接头105的漏极区,以及一个适当掺杂(例如n漂流)的区域104,位于衬底102上方。结合下文所述的超级结较高,n漂流区104部分可以用作n立柱,在n漂流区104的顶面和衬底102之间,具有变化的(即非均匀的)掺杂结构。器件100还包括一个p-型本体区106、一个n+源极区108,形成在p本体区106中,以及一个内衬电介质材料114的栅极沟槽110。栅极沟槽110具有一个栅极电极112a和一个屏蔽电极112b。栅极电极112a位于栅极沟槽110的顶部,屏蔽电极112b位于沟槽110的底部。如图1所示,沿着栅极沟槽底部的内表面的电介质材料114,比沿着沟槽顶部的内表面的电介质材料更厚。沟槽110底部中较厚的那部分电介质材料114使屏蔽电极112b和漂流区104绝缘,沟槽110顶部中较薄的那部分电介质材料114使栅极电极112a与本体区106绝缘。栅极电极112a的底部延伸到本体区106的底部下方。要注意的是,屏蔽电极112b也与栅极电极112a绝缘,并且使栅极电极112a与漂流区104中的电场绝缘。还可选择,用氧化物等电介质材料代替屏蔽电极112b。
器件100还包括一个绝缘层116,形成在栅极沟槽110上,一个栅极电极(图中没有表示出)以及一个源极金属118,形成在绝缘层116上并且连接到源极区108。
器件100包括一个超级结结构,具有交替的p掺杂立柱和n掺杂立柱。如图1所示,p立柱120形成在漂流区104中两个相邻的栅极沟槽110之间,从本体区106的底部开始穿过屏蔽电极112b的整个深度,延伸到比栅极沟槽110底部更深的深处。在一个较佳实施例中,p立柱120的总深度至少是屏蔽电极112b深度的三倍。N立柱可以由n漂流区104的一部分构成,n漂流区104的一部分位于p立柱120附近。P立柱120可以触及衬底层102或衬底层102上方的端接结构。在图2所示的一个可选实施例中,轻n型掺杂的缓冲层103位于衬底层102和n漂流区104之间,将p立柱120和衬底层102隔开。如图1和图2所示,p立柱120和n立柱由n漂流区104构成,实现了操作中的电荷平衡。利用栅极沟槽110中的屏蔽电极112b,n漂流区104在相邻的p立柱120之间的顶部被栅极沟槽110的底部占据。因此,n立柱中的n电荷浓度必须增大,以补偿屏蔽电极的存在,保持漂流区中的电荷平衡。在这种情况下,n立柱具有多余的n电荷浓度区,形成在栅极沟槽110的底部附近和周围。为了增大n电荷浓度,n立柱中的掺杂浓度(尤其是在栅极沟槽110的底部附近和周围)增大。因此,导通电阻Rds-on进一步降低。
要注意的是,半导体衬底102、漂流区104和源极区108都是相同的导电类型(例如n-型)。本体区106和掺杂立柱120的导电类型都与衬底102的导电类型相反(例如p-型)。
在一个实施例中,n和p立柱都用传统的工艺制备(例如制备多个外延硅层,然后在通过热激活形成立柱之前,注入一个或两个掺杂物)。n和p立柱可以在漂流区上具有不同的掺杂结构。图3表示依据本发明的各个方面,用于超级结器件的n立柱的激活净掺杂物结构。n和p立柱从上到下可以分成四个区域R1、R2、R3和R4。n和p立柱的每四个区域都包括一个或多个外延层,每个层的特点是都有一个p注入扩散物的裂片在每个外延层中。在每四个区域R1、R2、R3和R4中的n立柱都分别有净电荷浓度D1、D2、D3和D4。如图3所示,栅极沟槽110在R4区域内端接。n立柱在顶区R4中(即p本体区106附近)的掺杂浓度D4比n立柱在衬底102附近的区域R1的掺杂浓度D1更高。与n漂流区104中的其他区域相比,形成在栅极沟槽110附近和周围的多余的n电荷区具有最大的n-型掺杂浓度,因此有最大的净电荷浓度。作为示例,但不作为局限,对于漂流区104的顶部来说,多余的n电荷区可以通过提高注入剂量而形成。在一个实施例中,屏蔽电极112a附近的多余的n电荷区比传统的超级结器件多20-50%的电荷,n立柱具有的顶部净电荷浓度,不少于底部的净电荷浓度。在图3所示的一个较佳实施例中,顶部区域R4中的n立柱具有的电荷浓度D4比底部区域R1中的n立柱电荷浓度D1高20-50%。在另一个实施例中,靠近顶部区域R 4的R3区域中的n立柱具有的电荷浓度D3,与底部区域R1中的n立柱电荷浓度D1基本相同,但是比顶部区域R4中的n立柱电荷浓度D4要小。在另一个实施例中,顶部区域R4下方的每个区域R1、R2和R3中的n立柱的电荷浓度D1、D2和D3都与顶部区域R4中的n立柱电荷浓度D4基本相同,但比D4更小。在另一个实施例中,底部区域R1上方的R2区域中的n立柱的电荷浓度D2,小于底部区域R1中n立柱的电荷浓度D1。在另一个实施例中,顶部区域R4附近的R3区域中的n立柱电荷浓度D3与底部区域R1中的n立柱电荷浓度D1基本相同,但高于底部区域R1上方的区域R 2中的n立柱电荷浓度D2,小于顶部区域R4中的n立柱电荷浓度D4。底部区域R1正上方的区域R2中较低的掺杂浓度,有利于增大击穿电压,在传统的超级结器件中传统的掺杂等级体系往往造成击穿电压的降低。这种传统的掺杂等级牺牲了峰值击穿电压,对p和n立柱中的电荷失配具有较大的容忍度,从而使制造商可以轻松地降低电荷注入控制的精度,增大了器件性能的不均匀性。在一些实施例中,区域R2中的n立柱电荷浓度D2可以低至区域R2上方R3区域中n立柱电荷浓度D3以及区域R2下方的底部区域R1中n立柱电荷浓度D1的60%。
图4表示依据本发明的各个方面,用于超级结器件的n立柱和p立柱的激活净掺杂物结构。n和p立柱都可以从上到下分成四个区域R1、R2、R3和R4。n和p立柱的每四个区域都可以包括一个或多个外延层,每个层的特点是都有一个p注入扩散物的裂片在每个外延层中。在图4所示的实施例中,顶部区域R4包括两个外延层Ln和Ln-1,但是却含有更多或更少的外延层。每个栅极沟槽110都在R4区域内端接。靠近顶部区域R4的R3区域包括一个外延层Ln-3,但是可以包括多个外延层。底部区域R1包括一个外延层L1,但是包括多个外延层。在底部区域R1上方附近的R2区域包括两个或多个外延层L2到Ln-3。四个区域R1、R2、R3和R4中每个外延层里的n立柱都分别有一个净电荷剂量Qn1、Qn2、Qn3和Qn4。四个区域R1、R2、R3和R4的外延层里的p立柱分别具有净电荷剂量Qp1、Qp2、Qp3和Qp4。为了获得稳定的高击穿电压,Qn2最好与Qp2基本相等,使得R2区域中每个外延层里的n和p立柱中的电荷平衡,同时与n立柱相比,顶部区域中的p立柱具有多余的电荷,与p立柱相比,底部区域中的n立柱具有多余的电荷。
在图4所示的配置中,Qn4大于Qp4,Qn3小于Qp3。在该配置中的一个较佳实施例中,Qn4比Qp4大30%至70%,Qn3比Qp3小4%至8%。在另一个实施例中,Qn4大于Qp4,Qn1大于Qp1。在另一个实施例中,Qn4大于Qp4,Qn3小于Qp3,并且Qn1大于Qp1。
对于上述图3和图4所示的配置中,对于不同的区域,每个外延层中n立柱的剂量都可以变化。在一个较佳实施例中,n立柱在顶部区域R4中每个外延层里的剂量Qn4,大于n立柱在底部区域R1中每个外延层里的剂量Qn1。在另一个实施例中,n立柱在顶部区域R4附近的R3区域中的n立柱在每个外延层中具有剂量Qn3,与底部区域R1中每个外延层里的n立柱剂量Qn1基本相等。在另一个实施例中,顶部区域R4附近的R3区域中n立柱在每个外延层中具有剂量Qn3,与底部区域R1中每个外延层里的n立柱剂量Qn1基本相等,但小于顶部区域R4中每个外延层里的n立柱剂量Qn4。在另一个实施例中,在顶部区域R4下方的每个区域R1、R2和R3的每个外延层中n立柱剂量Qn1、Qn2和Qn3,与顶部区域R4中每个外延层里的n立柱剂量Qn4基本相等,但小于Qn4。在另一个实施例中,底部区域R1上方的区域R2中n立柱在每个外延层中具有剂量Qn2,小于底部区域R1中每个外延层里的n立柱剂量Qn1。在另一个实施例中,顶部区域R4附近的R3区域中每个外延层里的n立柱剂量Qn3,与底部区域R1中每个外延层里的n立柱剂量Qn1基本相等,但大于底部区域R1上方的区域R 2中每个外延层里的n立柱剂量Qn2,小于顶部区域R4中每个外延层里的n立柱剂量Qn4。底部区域R1正上方的区域R2中较低的掺杂物浓度,有利于增大击穿电压,在传统的超级结器件中传统的掺杂等级体系往往造成击穿电压的降低。这种传统的掺杂等级牺牲了峰值击穿电压,对p和n立柱中的电荷失配具有较大的容忍度,从而使制造商可以轻松地降低电荷注入控制的精度,增大了器件性能的不均匀性。在一些实施例中,区域R2中的n立柱电荷浓度Qn2可以低至区域R2上方R3区域中n立柱电荷浓度Qn3以及区域R2下方的底部区域R1中n立柱电荷浓度Qn1的60%。在所有的实施例中,Qn4可以比Qn1高70%。还可选择,调节p立柱中的剂量,使得顶部区域R4下方的每个区域R1、R2和R3的每个外延层中p立柱剂量Qp1、Qp2和Qp3,与顶部区域R4中每个外延层里的p立柱剂量Qp4基本相等,或者顶部区域R4附近的R3区域中每个外延层里的p立柱剂量Qp3,与底部区域R1中每个外延层里的p立柱剂量Qp1基本相等,但大于底部区域R1上方的区域R2中每个外延层里p立柱剂量Qp2。依据本发明的各个方面,与传统的超级结器件相比,在超级结器件中增加SGT结果可以降低15%的导通电阻Rds-on。为了补偿屏蔽电极112b的存在,获得增大n电荷的良好效果,可以在n立柱上方和内部(即n漂流区104)形成栅极沟槽110,屏蔽电极的底部应比多余的n电荷区更浅。栅极沟槽110不能比n立柱更宽。作为示例,但不作为局限,栅极沟槽的宽度与超级结间距之比约为0.175。在一个实施例中,对于5-6微米深度的沟槽来说,沟槽的宽度为0.9微米。另外,为了保持漂流区中的电荷平衡,栅极沟槽110的中心应在n-立柱中,以及两个相邻的p立柱之间。如果栅极沟槽110偏离中心,会导致电荷平衡受损。作为示例,但不作为局限,对于具有8微米间距的超级结结构中的沟槽宽度1.4微米来说,不对准容差约为0.1至0.2微米。还可选择,调节漂流区104中的n电荷,补偿可能的不对准。
图5表示一种超级结器件的可选配置,在这种器件中沟槽的不对准效果可以降低。图5所示的器件与图4所示的器件基本相同,除了栅极沟槽110’比栅极沟槽110浅得多之外,以便于只有栅极电极112a形成在沟槽110’中。栅极氧化物114’在栅极沟槽110’的底部较厚。由于栅极沟槽110’很浅,所以顶部区域R4只包括一个外延层Ln。栅极沟槽110’在顶部区域R4中端接。靠近顶部区域R4的区域R3包括一个外延层Ln-1,但是可以包括更多的外延层。底部区域R1包括两个外延层L1和L2,但可以包括更少或更多的外延层。除了降低Qn4,以便降低D4之外,在底部区域R1上方的区域R2包括两个或多个外延层L3至Ln-2。P和n立柱中每个外延层的剂量都与图3和图4所示的剂量类似。在一个较佳实施例中,Qn4比Qp4大10%至30%,Qn3比Qp3小4%至8%。在另一个较佳实施例中,Qn4可以比Qn1大30%以上。
图6表示一种带有平面栅结构的可选配置,其中没有了沟槽不对准效果。除了平面栅极112a’形成在半导体上方的栅极电介质层114”上,而不是在沟槽内部之外,图6所示的器件与图5所示的器件相同。由于没有了沟槽,所以每个p和n立柱的顶部区域R4都省略了。本体区106附近的区域R3包括两个外延层Ln和Ln-1,但是可以包括更少或更多的外延层。底部区域R1包括两个外延层L1和L2,但可以包括更少或更多的外延层。底部区域R1上方的中间区域R2包括两个或多个外延层L3至Ln-2。区域R1、R2和R3中p和n立柱中每个外延层的剂量都与图3和图4所示的区域R1、R2和R3中p和n立柱中每个外延层相应的剂量接近。
依据本发明的各个方面,与传统的超级结器件相比,在超级结器件中增加SGT结构可以降低15%左右的导通电阻Rds-on。
尽管本发明的内容已经通过上述优选实例作了详细介绍,但应当认识到上述的描述不应被认为是本发明的限制。在本领域技术人员阅读了上述内容后,对于本发明的多种修改和替代都将是显而易见的。因此,本发明的保护范围应由所附的权利要求来限定。
Claims (25)
1.一种金属-氧化物-半导体场效应晶体管器件,其特征在于,包含:
一个第一导电类型的漂流区,位于相同导电类型的重掺杂衬底上方;
一个第二导电类型的本体区,位于漂流区上方,第二导电类型与第一导电类型相反;
多个沟槽,位于本体区中,并延伸到漂流区内;
一个第一导电类型的重掺杂源极区,位于本体区中;以及
一个超级结结构,位于漂流区中,包括交替的第一导电类型的第一掺杂立柱以及平行排布的第二导电类型的第二掺杂立柱,其中第二掺杂立柱的每个立柱都位于两个相邻的沟槽之间,其中第一掺杂立柱的每个立柱都有一个多余的电荷浓度区,在多个沟槽中相应的一个沟槽附近和周围,其中交替的第一掺杂立柱和第二掺杂立柱都在漂流区中处于基本的电荷平衡。
2.如权利要求1所述的一种金属-氧化物-半导体场效应晶体管器件,其特征在于,其中多个沟槽中的每个沟槽的中心都在第一掺杂立柱的顶部,并且在两个相邻的第二掺杂立柱之间。
3.如权利要求1所述的一种金属-氧化物-半导体场效应晶体管器件,其特征在于,其中多个沟槽的每个沟槽都具有一个底部,端接在多余的电荷浓度区。
4.如权利要求1所述的一种金属-氧化物-半导体场效应晶体管器件,其特征在于,其中多个沟槽的每个沟槽宽度都不大于相应的第一掺杂立柱的宽度。
5.如权利要求1所述的一种金属-氧化物-半导体场效应晶体管器件,其特征在于,其中第一掺杂立柱具有在漂流区上变化的掺杂结构,其中底部区域上方和多余的电荷浓度区域下方的区域,具有比底部区域中净电荷浓度更低的净电荷浓度。
6.如权利要求1所述的一种金属-氧化物-半导体场效应晶体管器件,其特征在于,其中与第一掺杂立柱中的其他区域相比,相应的沟槽底部附近和周围的多余的电荷浓度区具有最大的掺杂浓度。
7.如权利要求1所述的一种金属-氧化物-半导体场效应晶体管器件,其特征在于,其中多个沟槽中的每个沟槽都内衬电介质材料,每个沟槽的顶部都有一个栅极电极,底部都有一个屏蔽电极。
8.如权利要求1所述的一种金属-氧化物-半导体场效应晶体管器件,其特征在于,其中多个沟槽中的每个沟槽都内衬电介质材料,每个沟槽的顶部都有一个栅极电极,并且电介质材料填充多个沟槽中每个沟槽的底部。
9.如权利要求1所述的一种金属-氧化物-半导体场效应晶体管器件,其特征在于,其中多余的电荷区域具有比第一掺杂立柱的其他部分高20%至50%的电荷浓度。
10.如权利要求1所述的一种金属-氧化物-半导体场效应晶体管器件,其特征在于,其中栅极沟槽的宽度与超级结间距的比值约为0.175。
11.一种金属-氧化物-半导体场效应晶体管器件,其特征在于,包括:
一个第一导电类型的漂流区,位于相同导电类型的重掺杂衬底上方;
一个第二导电类型的本体区,位于漂流区上方,第二导电类型与第一导电类型相反;
多个沟槽,位于本体区中,并延伸到漂流区内;
一个第一导电类型的重掺杂源极区,位于本体区中;以及
一个超级结结构,位于漂流区中,包括交替的第一导电类型的第一掺杂立柱以及平行排布的第二导电类型的第二掺杂立柱,其中第二掺杂立柱的每个立柱都位于两个相邻的沟槽之间,其中第一掺杂立柱和第二掺杂立柱中的每个立柱在沟槽底部下方延伸,其中交替的第一掺杂立柱和第二掺杂立柱都在漂流区中处于基本的电荷平衡。
12.如权利要求11所述的一种金属-氧化物-半导体场效应晶体管器件,其特征在于,其中多个沟槽的每个沟槽中心都在第一掺杂立柱上方,以及两个相邻的第二掺杂立柱之间。
13.如权利要求12所述的一种金属-氧化物-半导体场效应晶体管器件,其特征在于,其中多个沟槽中的每个沟槽都有一个底部,端接在相应的一个掺杂立柱的顶部。
14.如权利要求11所述的一种金属-氧化物-半导体场效应晶体管器件,其特征在于,其中多个沟槽中的每个沟槽宽度都小于第一掺杂立柱中相应的掺杂立柱的宽度。
15.如权利要求11所述的一种金属-氧化物-半导体场效应晶体管器件,其特征在于,其中第一掺杂立柱在漂流区上具有变化的掺杂结构,其中底部区域上方和顶部区域下方的区域具有比底部区域中净电荷浓度更低的净电荷浓度。
16.如权利要求11所述的一种金属-氧化物-半导体场效应晶体管器件,其特征在于,其中与第一掺杂立柱中的其他区域相比,相应的沟槽的底部附近和周围的第一掺杂立柱的顶部区域具有最大的净电荷掺杂浓度。
17.如权利要求11所述的一种金属-氧化物-半导体场效应晶体管器件,其特征在于,其中内衬电介质材料的多个沟槽中的每个沟槽都在顶部具有一个栅极电极,在底部具有一个屏蔽电极。
18.如权利要求11所述的一种金属-氧化物-半导体场效应晶体管器件,其特征在于,其中内衬电介质材料的多个沟槽中的每个沟槽都在顶部具有一个栅极电极,以及电介质材料填充多个沟槽中每个沟槽的底部。
19.一种超级结半导体器件,其特征在于,包括:
一个第一导电类型的漂流区,位于相同导电类型的重掺杂衬底上方;
一个第二导电类型的本体区,位于漂流区上方,第二导电类型与第一导电类型相反;以及
一个超级结结构,位于漂流区中,包括交替的第一导电类型的第一掺杂立柱以及平行排布的第二导电类型的第二掺杂立柱,其中第一掺杂立柱在漂流区上具有不同的掺杂结构,其中底部区域上方和上部区域下方的中间区域具有的净电荷浓度,低于底部区域和上部区域中净电荷浓度,其中交替的第一掺杂立柱和第二掺杂立柱都在漂流区中处于基本的电荷平衡。
20.如权利要求19所述的一种超级结半导体器件,其特征在于,其中第一掺杂立柱中每个立柱的底部区域、中间区域和上部区域都包括多个掺杂第一导电类型的外延层。
21.如权利要求20所述的一种超级结半导体器件,其特征在于,其中掺杂第一导电类型的中间区域中多个外延层的每个外延层的剂量,都低于底部区域和上部区域中每个外延层的剂量。
22.如权利要求19所述的一种超级结半导体器件,其特征在于,其中第一掺杂立柱中的每个掺杂立柱都包括一个在上部区域上方的顶部区域。
23.如权利要求22所述的一种超级结半导体器件,其特征在于,其中第一掺杂立柱的每个掺杂立柱的底部区域、中间区域、上部区域和顶部区域都包括掺杂第一导电类型的多个外延层,其中掺杂顶部区域中第一导电类型的多个外延层的每个外延层的剂量,高于底部区域、中间区域和上部区域中每个外延层的剂量。
24.如权利要求19所述的一种超级结半导体器件,其特征在于,其中第一掺杂立柱的每个立柱还包括一个在上部区域之上的顶部区域,其中掺杂顶部区域中第一导电类型的多个外延层的每个外延层剂量,都高于底部区域、中间区域和上部区域中每个外延层的剂量。
25.一种超级结半导体器件,其特征在于,包括:
一个漂流区,由一个位于漂流区中的超级结结构构成,包括交替的第一导电类型的第一掺杂立柱和平行排布的第二导电类型的第二掺杂立柱,其中第一掺杂立柱包括掺杂第一导电类型的多个外延层,在漂流区上具有变化的掺杂结构,其中底部区域上方和上部区域下方的中间区域中每个外延层的剂量,低于底部区域和上部区域中每个外延层的剂量,其中交替的第一掺杂立柱和第二掺杂立柱都在漂流区中处于基本的电荷平衡。
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