CN109980002A - Transistor device and preparation method thereof - Google Patents
Transistor device and preparation method thereof Download PDFInfo
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- CN109980002A CN109980002A CN201910360966.9A CN201910360966A CN109980002A CN 109980002 A CN109980002 A CN 109980002A CN 201910360966 A CN201910360966 A CN 201910360966A CN 109980002 A CN109980002 A CN 109980002A
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- 238000002360 preparation method Methods 0.000 title claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 76
- 229910002601 GaN Inorganic materials 0.000 claims description 61
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims description 54
- 230000004888 barrier function Effects 0.000 claims description 31
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 26
- 229910052733 gallium Inorganic materials 0.000 claims description 26
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims description 24
- 230000015572 biosynthetic process Effects 0.000 claims description 20
- 230000005533 two-dimensional electron gas Effects 0.000 claims description 20
- 229910052782 aluminium Inorganic materials 0.000 claims description 18
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 18
- 239000004411 aluminium Substances 0.000 claims description 18
- 239000011248 coating agent Substances 0.000 claims description 14
- 238000000576 coating method Methods 0.000 claims description 14
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 12
- 229910052757 nitrogen Inorganic materials 0.000 claims description 12
- 229910017083 AlN Inorganic materials 0.000 claims description 10
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 claims description 10
- -1 aluminium indium nitrogen Chemical compound 0.000 claims description 9
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 claims description 7
- 230000008859 change Effects 0.000 claims description 6
- 239000011787 zinc oxide Substances 0.000 claims description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- AUCDRFABNLOFRE-UHFFFAOYSA-N alumane;indium Chemical compound [AlH3].[In] AUCDRFABNLOFRE-UHFFFAOYSA-N 0.000 claims description 4
- 229910052710 silicon Inorganic materials 0.000 claims description 4
- 239000010703 silicon Substances 0.000 claims description 4
- 229910052582 BN Inorganic materials 0.000 claims description 3
- PZNSFCLAULLKQX-UHFFFAOYSA-N Boron nitride Chemical compound N#B PZNSFCLAULLKQX-UHFFFAOYSA-N 0.000 claims description 3
- 230000007423 decrease Effects 0.000 claims description 3
- 229910003460 diamond Inorganic materials 0.000 claims description 3
- 239000010432 diamond Substances 0.000 claims description 3
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 claims description 3
- 229910001195 gallium oxide Inorganic materials 0.000 claims description 3
- 229910052594 sapphire Inorganic materials 0.000 claims description 3
- 239000010980 sapphire Substances 0.000 claims description 3
- 238000003763 carbonization Methods 0.000 claims 1
- 230000003245 working effect Effects 0.000 abstract description 6
- 239000010410 layer Substances 0.000 description 315
- 239000000463 material Substances 0.000 description 17
- IWBUYGUPYWKAMK-UHFFFAOYSA-N [AlH3].[N] Chemical compound [AlH3].[N] IWBUYGUPYWKAMK-UHFFFAOYSA-N 0.000 description 14
- 238000010586 diagram Methods 0.000 description 11
- 229910052738 indium Inorganic materials 0.000 description 7
- 230000000694 effects Effects 0.000 description 6
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 description 6
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 4
- 229910052799 carbon Inorganic materials 0.000 description 4
- 239000002131 composite material Substances 0.000 description 4
- JEIPFZHSYJVQDO-UHFFFAOYSA-N iron(III) oxide Inorganic materials O=[Fe]O[Fe]=O JEIPFZHSYJVQDO-UHFFFAOYSA-N 0.000 description 4
- 238000003475 lamination Methods 0.000 description 4
- 239000002356 single layer Substances 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000003139 buffering effect Effects 0.000 description 2
- 239000012141 concentrate Substances 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000001737 promoting effect Effects 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- NWAIGJYBQQYSPW-UHFFFAOYSA-N azanylidyneindigane Chemical compound [In]#N NWAIGJYBQQYSPW-UHFFFAOYSA-N 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 235000013399 edible fruits Nutrition 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000000053 physical method Methods 0.000 description 1
- 230000002035 prolonged effect Effects 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
- H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Junction Field-Effect Transistors (AREA)
Abstract
The present invention relates to a kind of transistor devices and preparation method thereof.The transistor device only forms gap in the part in device layer corresponding substrate second area and third region, and extends source electrode and drain electrode along the gap.The transistor device can increase the Ohmic contact between source electrode and drain electrode and device layer, reduce the resistance between source electrode and drain electrode and device layer, increase the working effect of transistor device.
Description
Technical field
The present invention relates to transistor device technical fields, more particularly to transistor device and preparation method thereof.
Background technique
Transistor device is trigistor, is now widely used for radar, satellite, base station, electronic device and nothing
Line charge electric appliance etc..
Traditional transistor device, grid generally with device layer Schottky contacts；Source electrode and drain electrode is generally and device layer
Ohmic contact.
Applicant has found during realizing traditional technology: traditional transistor device, source electrode and drain electrode and device
Ohmic contact effect between layer is poor, and contact resistance is larger.
Summary of the invention
Based on this, it is necessary between the source electrode and drain electrode and device layer of transistor device present in traditional technology
Ohmic contact effect is poor, the larger problem of contact resistance, provides a kind of transistor device and preparation method thereof.
A kind of transistor device, comprising: substrate has the first surface and second surface being oppositely arranged, first table
Face includes first area, and second area adjacent with the first area respectively and third region；Patterned layer covers institute
State first area；Buffer layer, covers the patterned layer and the second area, third region, and the buffer layer has separate
The planarization surface of the substrate；Device layer, covers the planarization surface, and the device layer includes far from the planarization table
The device layer surface in face；Along the opposite direction of the stacking direction of the transistor device, the device layer is located at the second area
There is the gap extended from the device layer surface to the substrate with the part in third region；Grid covers the device layer
Surface, and the upright projection of the grid on the first surface is located in the first area；Source electrode and drain electrode covers institute
Device layer surface is stated, and the upright projection of the source electrode on the first surface is located in the second area, the drain electrode
Upright projection on the first surface is located in the third region, and the source electrode and the drain electrode are also prolonged along the gap
It stretches.
Above-mentioned transistor device only forms gap in the part in device layer corresponding substrate second area and third region,
And extend source electrode and drain electrode along the gap.The transistor device can increase the Europe between source electrode and drain electrode and device layer
Nurse contact, reduces the resistance between source electrode and drain electrode and device layer, increases the working effect of transistor device.
A kind of preparation method of transistor device, comprising:
There is provided substrate, the substrate has the first surface and second surface that are oppositely arranged, and the first surface includes the
One region, and second area adjacent with the first area respectively and third region；
Patterned layer is prepared, the first area is covered；
Buffer layer is prepared, the patterned layer and the second area, third region are covered, the buffer layer has separate
The planarization surface of the patterned layer；
Device layer is prepared, the planarization surface is covered, the device layer includes the device far from the planarization surface
Layer surface；
Grid is prepared, the device layer surface is covered, and is located at the grid in the upright projection of the first surface
In the first area；Below with reference to modification
Source electrode and drain electrode is prepared, covers the device layer surface, and make the source electrode in the vertical throwing of the first surface
Shadow is located in the second area, and the drain electrode is located in the third region in the projection of the first surface；
The device layer is heated, forms the gap extended from the device layer surface to the substrate, and make the source electrode
It is penetrated into the gap with the drain electrode.
The preparation method of above-mentioned transistor device can make device by preparing patterned layer on the first area of substrate
The gap that part layer generates when heating is only located at the part that device layer corresponds to second area and third region.With this, when source electrode and leakage
When pole extends along the gap, can be increased the Ohmic contact between source electrode and drain electrode and device layer, reduce source electrode and drain electrode with
Resistance between device layer increases the working effect of transistor device.
Detailed description of the invention
Fig. 1 is the preparation technology flow chart of transistor device in the application one embodiment.
Fig. 2 is the schematic diagram of the section structure of transistor device in the application one embodiment.
Fig. 3 is the schematic diagram of the section structure of transistor device in another embodiment of the application.
Fig. 4 is the schematic diagram of the section structure of transistor device in another embodiment of the application.
Fig. 5 is the schematic perspective view of patterned layer in the application one embodiment.
Fig. 6 is the schematic perspective view of patterned layer in another embodiment of the application.
Fig. 7 is the schematic perspective view of patterned layer in another embodiment of the application.
Fig. 8 is the schematic perspective view of patterned layer in another embodiment of the application.
Fig. 9 is the schematic diagram of the section structure of transistor device in another embodiment of the application.
Figure 10 is the schematic diagram of the section structure of transistor device in another embodiment of the application.
Wherein, meaning representated by each drawing reference numeral is respectively as follows:
10, transistor device；
110, substrate；
112, second surface；
114, first surface；
1141, first area；
1142, second area；
1143, third region；
120, patterned layer；
1204, the 4th surface；
122, graphical unit；
124, pit；
130, buffer layer；
132, surface is planarized；
140, device layer；
1401, device layer surface；
1402, gap；
141, high value layer；
142, channel layer；
143, Two-dimensional electron gas-bearing formation；
144, barrier layer；
145, coating；
151, grid；
152, source electrode；
153, it drains.
Specific embodiment
In order to make the foregoing objectives, features and advantages of the present invention clearer and more comprehensible, with reference to the accompanying drawing to the present invention
Specific embodiment be described in detail.Many details are explained in the following description in order to fully understand this hair
It is bright.But the invention can be embodied in many other ways as described herein, those skilled in the art can be not
Similar improvement is done in the case where violating intension of the present invention, therefore the present invention is not limited by the specific embodiments disclosed below.
The application provides a kind of transistor device and preparation method thereof, and described transistor device and preparation method thereof can have
Effect increases the Ohmic contact effect between source electrode and drain electrode and device layer, and reduces the contact between source electrode and drain electrode and device layer
Resistance.
A kind of preparation method of transistor device includes the following steps: as depicted in figs. 1 and 2
S100, provides substrate 110, and the substrate 110 has the first surface 114 and second surface 112 being oppositely arranged.Institute
State first surface 114 include first area 1141, and second area 1142 adjacent with the first area 1141 respectively and
Third region 1143.
Specifically, providing the substrate 110 for being used to prepare transistor device 10.The substrate 110 has 114 He of first surface
Second surface 112, the second surface 112 are oppositely arranged with first surface 114.Wherein, the first surface 114 has first
Region 1141, and the second area 1142 adjacent with the first area 1141 and third region 1143.In other words, in institute
On the longitudinal profile for stating substrate 110, the first surface 114 is divided into first area 1141, second area 1142 and third
Region 1143.The first area 1141 is located at the center of the first surface 114, the second area 1142 and the third
Region 1143 is located at 1141 two sides of first area.
S200 prepares patterned layer 120, covers the first area 1141.
Specifically, the patterned layer 120, which refers to, utilizes light shield or mask plate, rear resulting tool is etched to a certain material
There is the material layer of certain figure.Wherein, it covers the covering in the first area 1141 and refers to and be completely covered.The i.e. described patterned layer
120 are completely covered the first area 1141.
S300 prepares buffer layer 130, covers the patterned layer 120 and the second area 1142, the third region
1143.The buffer layer 130 has the planarization surface 132 far from the patterned layer 120.
Specifically, preparing one layer of buffer layer 130 in the top of the substrate 110 and the patterned layer 120.The buffering
The exposed second area 1142 and the third region 1143 in 130 covering step S200 of layer, and in covering step S200
The patterned layer 120 of preparation.Here covering, which refers to, to be completely covered, i.e., the described buffer layer 130 is completely covered described graphical
The second area 1142 and the third region 1143 of layer 120 and the first surface 114.Meanwhile the buffer layer 130
A flat surface is also provided for, in order to continue to prepare other hierarchical structures in subsequent technique.At this point, the buffer layer
130 have a planarization surface 132 far from the substrate 110 and the patterned layer 120.
S400 prepares device layer 140, covers the planarization surface 132, and the device layer 140 includes far from described flat
The device layer surface 1401 on smoothization surface 132.
Device layer 140 is prepared on the planarization surface 132, and by the device layer 140 far from the planarization
One surface on surface 132 is named as device layer surface 1401.
S500 prepares grid 151, covers the device layer surface 1401, and makes the grid 151 in the first surface
114 upright projection is located in the first area 1141.
Grid 151 is prepared on the device layer surface 1401.The grid 151 covers the device layer surface 1401.
Here covering refers to that part covers, i.e., the described grid 151 covers a part of the device layer surface 1401.Meanwhile the grid
Pole 151 should also be located in the first area 1141 in the upright projection on the first surface 114, in other words, along described
The stacking direction of transistor device 10, the grid 151 are located in the first area 1141.
S600 prepares source electrode 152 and drain electrode 153, covers the device layer surface 1401, and make the source electrode 152 in institute
The upright projection for stating first surface 114 is located in the second area 1142, described to drain 153 in the first surface 114
Upright projection is located in the third region 1143.
Source electrode 152 and drain electrode 153 are prepared on the device layer surface 1401.The source electrode 152 covers the device layer
Surface 1401, and the drain electrode 153 also covers the device layer surface 1401.Here covering refers to that part covers, i.e., the described source
Pole 152 covers a part of the device layer surface 1401；It drains and 153 also covers one of the device layer surface 1401
Point.Meanwhile the source electrode 152 should also be located in the second area 1142 in the upright projection on the first surface 114；Institute
Stating drain electrode 153 should also be located in the third region 1143 in the upright projection on the first surface 114.In other words, edge
The stacking direction of the transistor device 10, the source electrode 152 are located in the second area 1142, and the drain electrode 153 is located at
In the third region 1143.
S700 heats the device layer 140, the source electrode 152 and the drain electrode 153, is formed from the device layer surface
1401 gaps 1402 extended to the substrate 110, and the source electrode 152 and the drain electrode 153 is made to penetrate into the gap 1402
It is interior.
Specifically, after successively forming patterned layer 120, buffer layer 130 and device layer 140 on substrate 110, to the device
Part layer 140 is heated.Since the beneath portions of the corresponding first area 1141 of the device layer 140 are equipped with patterned layer
120, generated stress point can will be heated to the corresponding second area 1142 of the device layer 140 and the third region
1143 part.At this point, can make the device layer 140 heat caused by concentrate on the device layer 140 right in gap 1402
The part of the second area 1142 and third region 1143 is answered, and makes the part of the corresponding first area 1141 of device layer 140 not
Generate gap 1402.
Meanwhile source electrode 152 and drain electrode 153 are heated, penetrate into source electrode 152 and drain electrode 153 in the gap 1402.Source electrode
After 152 penetrate into the gap 1402 with drain electrode 153, extended along the gap 1402, source electrode 152 can be increased and is drained
153 with the contact area of the device layer 140.The preparation method of the transistor device can effectively increase the source electrode 152
Ohmic contact between drain electrode 153 and the device layer 140, to reduce the source electrode 152 and drain electrode 153 and the device
Resistance between layer 140 increases the working effect of transistor device 10.
In one embodiment, the preparation method of the transistor device, in the step S100, the substrate 110 can
To be gallium nitride substrate 110, silicon carbide substrates 110, Sapphire Substrate 110, silicon substrate 110, diamond substrate 110, boron nitride lining
Bottom 110, aluminium nitride substrate 110, zinc oxide substrate 110, gallium oxide substrate 110 and aluminium-doped zinc oxide substrate 110 it is any one
Kind.
In one embodiment, the preparation method of the transistor device, the step S200 specifically may is that
S201 forms the graphical of a material identical as the substrate 110 on the first surface 114 of the substrate 110
Substrate 110, the patterned substrate 110 cover and only cover the first area 1141.
S202 provides the light shield of corresponding preset pattern, and is etched by the light shield to the patterned substrate 110
To prepare the patterned layer 120.
Wherein, the etching can be any one of dry-etching or wet etching.By light shield to described graphical
After substrate 110 is etched, the patterned layer 120 for covering the first area 1141 can be obtained.The preset pattern
Should can provide the figure of stress peptizaiton for the device layer 140.
In one embodiment, the preparation method of the transistor device, in the step S300, the buffer layer 130
Material can be at least one of aluminium nitride, gallium nitride, aluminum gallium nitride, aluminium indium nitrogen and aluminium indium gallium nitrogen.The buffer layer 130 can be with
It is the single layer structure that a certain material or multiple material are mixed to form, is also possible to multilayer lamination structure.When the buffer layer 130 is
When multilayer lamination structure, it can make along the transistors during the preparation process for the effect of further Promoting Layered Buffer layer 130
The aluminium content of the stacking direction of part 10, the buffer layer 130 gradually decreases.Such as:
In a specific embodiment, the step S300 can specifically include: S311 and prepare aln layer, covering
The patterned layer 120 and the second area 1142, the third region 1143.S312 prepares mixed layer, covers the nitrogen
Change aluminium layer, the mixed layer includes gallium nitride and aluminium nitride.S313 prepares gallium nitride layer, covers the mixed layer.S314, system
Standby gallium nitride layer, covers the gallium nitride layer.Wherein, in each hierarchical structure, the relationship of aluminium content are as follows: aln layer > mixed layer
> gallium nitride layer > gallium nitride layer.
In another specific embodiment, the step S300 can specifically include: S321 and prepare aln layer, cover
Cover the patterned layer 120 and the second area 1142, the third region 1143.S322 prepares the first gallium nitride layer, covers
Cover the aln layer.S323 prepares the second gallium nitride layer, covers first gallium nitride layer, second gallium nitride layer
Aluminium content is less than the aluminium content of first gallium nitride layer.S324 prepares gallium nitride layer, covers second gallium nitride layer.Its
In, in each hierarchical structure, the relationship of aluminium content are as follows: aln layer > the first gallium nitride layer > the second gallium nitride layer > gallium nitride
Layer.First gallium nitride layer and second gallium nitride layer can be superlattice structure.
In another specific embodiment, the step S300 can specifically include: S331 and prepare aln layer, cover
Cover the patterned layer 120 and the second area 1142, the third region 1143.S332 prepares the first gallium nitride layer, covers
Cover the patterned layer 120.S333 prepares the second gallium nitride layer, covers first gallium nitride layer.S334 prepares third aluminium
Gallium nitrogen layer covers second gallium nitride layer.S335 prepares gallium nitride layer, covers the third gallium nitride layer.Wherein, each layer
In level structure, the relationship of aluminium content are as follows: aln layer > the first gallium nitride layer > the second gallium nitride layer > third gallium nitride layer >
Gallium nitride layer.
In one embodiment, the step S400, can specifically include:
S401 prepares high value layer 141, covers the planarization surface 132.
Specifically, the high value layer on the planarization surface 132 is completely covered in preparation on the planarization surface 132
141.The high value layer 141 can be the gallium nitride layer of high value or the aluminium nitrogen gallium layer of high value.The nitridation of the high value
Gallium layer can be the gallium nitride layer of carbon doping, be also possible to the gallium nitride layer of Fe2O3 doping.The aluminium nitrogen gallium layer of the high value can be with
It is the aluminium nitrogen gallium layer of carbon doping, is also possible to the aluminium nitrogen gallium layer of Fe2O3 doping.
S402 prepares channel layer 142, covers the high value layer 141.
Specifically, the channel layer 142 of the high value layer 141 is completely covered in preparation on the high value layer 141.It is described
The material of channel layer 142 can be at least one of gallium nitride and aluminum gallium nitride.
S403 prepares Two-dimensional electron gas-bearing formation 143, covers the channel layer 142.
Specifically, the Two-dimensional electron gas-bearing formation 143 of the channel layer 142 is completely covered in preparation on the channel layer 142.Its
In, two-dimensional electron gas refers to makes the movement of electronic population in one direction be limited to one very with physical methods such as quantum confinements
In small range, and can be with the system of free movement on other two directions.Therefore, the Two-dimensional electron gas-bearing formation 143 has
It in two directions can be with the electronic population of free movement.
S404 prepares barrier layer 144, covers the Two-dimensional electron gas-bearing formation 143.
Specifically, the barrier layer of the Two-dimensional electron gas-bearing formation 143 is completely covered in preparation on the Two-dimensional electron gas-bearing formation 143
144.The material of the barrier layer 144 can be at least one of aluminum gallium nitride, aluminium indium nitrogen and aluminium nitride.
Wherein, the lattice coefficient of the barrier layer 144 is less than the lattice coefficient of the channel layer 142.
Further, the barrier layer 144 can be single-layer or multi-layer stacking.When the barrier layer 144 is multiple-level stack, institute
State the stacking principle of barrier layer 144 are as follows: the level lattice coefficient closer to the channel layer 142 is smaller.
S405 prepares coating 145, covers the barrier layer 144.
Specifically, the coating 145 of the barrier layer 144 is completely covered in preparation in the barrier layer 144.The coating
145 material can be gallium nitride, n type gallium nitride, p-type gallium nitride, indium gallium nitrogen, p-type indium gallium nitrogen, N-type indium gallium nitrogen, aluminium nitrogen gallium, N
Any one of type aluminium nitrogen gallium, p-type aluminium nitrogen gallium, aluminium indium nitrogen, N-type aluminium indium nitrogen and p-type aluminium indium nitrogen.In this embodiment, shape is prepared
At transistor device 10 it is as shown in Figure 3.
In one embodiment, the preparation method of above-mentioned transistor device, the preparation process in each step is chemistry
Vapour deposition process.
The application also provides a kind of transistor device 10, as shown in Fig. 2, including substrate 110, patterned layer 120, buffer layer
130, device layer 140, grid 151, source electrode 152 and drain electrode 153.
Specifically, the substrate 110 is located at the bottom of the transistor device 10, for providing shape for other hierarchical structures
At basis.The substrate 110 has first surface 114 and second surface 112, the second surface 112 and 114 phase of first surface
To setting.Wherein, the first surface 114 has first area 1141, and adjacent with the first area 1141 second
Region 1142 and third region 1143.In other words, on the longitudinal profile of the substrate 110, the first surface 114 is drawn
It is divided into first area 1141, second area 1142 and third region 1143.The first area 1141 is located at the first surface
114 center, the second area 1142 and the third region 1143 are located at 1141 two sides of first area.
The patterned layer 120, which refers to, utilizes light shield or mask plate, is etched to a certain material rear resulting with certain
The material layer of figure.The patterned layer 120 is completely covered by 1141 top of first area of the substrate 110.
The buffer layer 130 covers the second area 1142 and the third region 1143, and covers described graphical
Layer 120.Here covering, which refers to, to be completely covered, i.e., the patterned layer 120 and first table is completely covered in the described buffer layer 130
The second area 1142 in face 114 and the third region 1143.Meanwhile to also provide for one flat for the buffer layer 130
Surface, in order to the stacking of other hierarchical structures.At this point, the buffer layer 130 has one far from the substrate 110 and described
The planarization surface 132 of patterned layer 120.
The device layer 140 covers the planarization surface 132.The i.e. described device layer 140 is completely covered by the buffering
130 top of layer.A surface of the device layer 140 far from the planarization surface 132 is device layer surface 1401.Wherein,
Gap 1402 is also formed with inside the device layer 140.The gap 1402 since the device layer surface 1401 to described
110 direction of substrate extends.The i.e. described extending direction is the opposite direction of the stacking direction of transistor device 10.Meanwhile the gap
1402 are formed in the part that the device layer 140 is located at the second area 1142 and the third region 1143.
Grid 151 is covered in a part of the device layer surface 1401, and the grid 151 is in the first surface
Upright projection on 114 is located in the first area 1141.In other words, along the stacking direction of the transistor device 10
Opposite direction, the grid 151 are located in the first area 1141 in the projection on the first surface 114.
Source electrode 152 is covered in a part of the device layer surface 1401, and the source electrode 152 is in the first surface
Upright projection on 114 is located in the second area 1142.In other words, along the stacking direction of the transistor device 10
Opposite direction, the source electrode 152 are located in the second area 1142 in the projection on the first surface 114.Meanwhile the source
The suitable gap 1402 is gone back to 140 internal stretch of device layer in pole 152.The i.e. described source electrode 152 is in molten state, along the seam
Gap 1402 is penetrated into the device layer 140.Here, it is located at the device layer 140 for permeating the gap 1402 of the source electrode 152
The interior part corresponding to the second area 1142.
Drain electrode 153 is covered in a part of the device layer surface 1401, and the drain electrode 153 is in the first surface
Upright projection on 114 is located in the third region 1143.In other words, along the stacking direction of the transistor device 10
Opposite direction, the drain electrode 153 are located in the third region 1143 in the projection on the first surface 114.Meanwhile the leakage
The suitable gap 1402 is gone back to 140 internal stretch of device layer in pole 153.The i.e. described drain electrode 153 is in molten state, along the seam
Gap 1402 is penetrated into the device layer 140.Here, it is located at the device layer 140 for permeating the gap 1402 of the drain electrode 153
The interior part corresponding to the third region 1143.
Above-mentioned transistor device 10, only in 140 corresponding substrate of device layer, 110 second area 1142 and third region 1143
Part formed gap 1402, and make source electrode 152 and drain electrode 153 along the gap 1402 extend.The transistor device 10, can be with
Increase the Ohmic contact between source electrode 152 and drain electrode 153 and device layer 140, reduces source electrode 152 and drain electrode 153 and device layer 140
Between resistance, increase transistor device 10 working effect.
In one embodiment, the substrate 110 is gallium nitride substrate 110, silicon carbide substrates 110, Sapphire Substrate
110, silicon substrate 110, diamond substrate 110, boron nitride substrate 110, aluminium nitride substrate 110, zinc oxide substrate 110, gallium oxide lining
Any one of bottom 110 and aluminium-doped zinc oxide substrate 110.
In one embodiment, as shown in figure 4, the patterned layer 120 includes multiple adjacent graphical units 122.
Along the stacking direction of the transistor device 10, at least part of cross-sectional area of the graphical unit 122 is gradually reduced.
Specifically, the patterned layer 120 may include multiple identical graphical units 122.Multiple graphical units
122 stackings are repeatedly formed patterned layer 120.The patterned layer 120 is used for when heating the device layer 140, by the device
Stress point caused by heating in part layer 140 corresponds to the second area 1142 and the third region to the device layer 140
1143 part.With secondary, the device layer 140 plus thermogenetic gap 1402 can concentrate on the corresponding institute of the device layer 140
State the part of second area 1142 and third region 1143.
Disperse preferably to realize that patterned layer 120 heats generated stress to device layer 140, constitutes graphical
The graphical unit 122 of layer 120 answers at least part of cross-sectional area to be gradually reduced.Here the cross section of graphical unit 122
Area is gradually reduced the stacking direction referred to along the transistor device 10, and the cross-sectional area of the graphical unit 122 is gradually
Reduce.Meanwhile the part that the cross-sectional area of the graphical unit 122 is gradually reduced, the graphical unit should be located at
122 parts far from the substrate 110.As shown in Figure 4.
Further, along the stacking direction of the transistor device 10, the section shape of the graphical unit 122 can be with
It is triangle, trapezoidal or half elliptic.When the section shape of the graphical unit 122 is triangle, the triangle
On one side should be Chong Die with the first area 1141, the angle opposite with the side is close to the device layer 140.When the graphical list
When the section shape of member 122 is trapezoidal, the trapezoidal long bottom edge should be Chong Die with the first area 1141, described trapezoidal
It short bottom edge should be close to the device layer 140.When the section shape of the graphical unit 122 is half elliptic, described half
The straight line of ellipse should be Chong Die with the first area 1141, and point corresponding with the straight line should be close to the device layer
140。
It is understood that corresponding graphical unit 122 is all that cross-sectional area is gradually reduced in above-described embodiment
's.When the cross-sectional area of the graphical unit 122 is only partially gradually reduced, the section of the graphical unit 122
Shape can also be rectangle and above-mentioned triangle, trapezoidal and half elliptic composite figure.
Further, along the stacking direction of the transistor device 10, when the section shape of the graphical unit 122
When for triangle, the graphical unit 122 can be any one of triangular prism, pyramid and cone.When the graphical unit
When 122 section shape is trapezoidal, the graphical unit 122 can be any one of quadrangular, terrace with edge and rotary table.
5 above-described embodiment is illustrated to attached drawing 7 with reference to the accompanying drawing.
When the section shape of the graphical unit 122 is the trapezoidal composite figure with rectangle, the graphical unit
122 three-dimensional structure diagram can be as shown in Figure 5.At this point, it is trapezoidal quadrangular and section that the graphical unit 122, which is section,
For the assembled unit of the quadrangular of rectangle.It is when the section shape of the graphical unit 122 is only trapezoidal, then described graphical
The three-dimensional structure diagram of unit 122 should be a part in Fig. 5.At this point, it is trapezoidal tetragonous that the graphical unit 122, which is section,
Column.In the present embodiment, the section refers both to the section of the stacking direction along the transistor device 10.
When the section shape of the graphical unit 122 is the composite figure of triangle and rectangle, the graphical list
The three-dimensional structure diagram of member 122 can be as shown in Figure 6.At this point, the graphical unit 122 is triangular prism and section is the four of rectangle
The assembled unit of prism.When the section shape of the graphical unit 122 is only triangle, then the graphical unit 122
Three-dimensional structure diagram should be a part in Fig. 6.At this point, it is trapezoidal triangular prism that the graphical unit 122, which is section,.This implementation
In example, the section refers both to the section of the stacking direction along the transistor device 10.
When the section shape of the graphical unit 122 is the trapezoidal composite figure with rectangle, the graphical unit
122 three-dimensional structure diagram can also be as shown in Figure 7.At this point, the graphical unit 122 is that section is trapezoidal quadrangular and cuts open
Face is the assembled unit of the quadrangular of rectangle.When the section shape of the graphical unit 122 is only trapezoidal, then the figure
The three-dimensional structure diagram for changing unit 122 should be a part in Fig. 7.At this point, it is trapezoidal four that the graphical unit 122, which is section,
Prism.In the present embodiment, the section refers both to the section of the stacking direction along the transistor device 10.
In other embodiments, the graphical unit 122 can also be including pyramid, circular cone or rotary table, can also be into one
Step includes assembled unit, the assembled unit of circular cone and cylinder or the assembled unit of rotary table and cylinder of pyramid and quadrangular.These
All it is the rational modification that those skilled in the art can make according to the application, repeats no more.
It is to be appreciated that be that patterned layer 120 is divided into multiple graphical units 122 in above-described embodiment, into
The graphical result of the patterned layer 120 is described.In other embodiments, the patterned layer 120 graphical as a result,
It can be as shown in Figure 8.
In embodiment as shown in Figure 8, the patterned layer 120 has the 4th surface 1204 far from the substrate 110.
4th surface 1204 has two or more pits 124.The pit 124 is concaved towards from the 4th surface 1204
The inside of the patterned layer 120.
Wherein, the opening area of the pit 124 is greater than the bottom area of the pit 124.In other words, described
On four surfaces 1204, the area of the pit 124 is greater than the bottom area of the 120 inside pit 124 of patterned layer.This
When, along the stacking direction of the transistor device 10, the section shape of the pit 124 is inverted trapezoidal or up-side down triangle.
From above-described embodiment as can be seen that the transistor device 10 of the application, the cross section of the patterned layer 120
Area are as follows: along the stacking direction of the transistor device 10, the cross-sectional area of the patterned layer 120 is gradually reduced.With this,
When the device layer 140 of the transistor device 10 heats, it can be realized and device layer 140 is heated into generated stress point to device
The part of the layer 140 corresponding second area 1142 and third region 1143, so that device layer 140 be made to heat generated gap
1402 are only located at the part of the device layer 140 corresponding second area 1142 and third region 1143.Therefore, all along the crystalline substance
The stacking direction of body tube device 10, the embodiment that the cross-sectional area of the patterned layer 120 is gradually reduced, is understood to
In the protection scope of the application.
In one embodiment, the material of the buffer layer 130 can be aluminium nitride, gallium nitride, aluminum gallium nitride, aluminium indium nitrogen and
At least one of aluminium indium gallium nitrogen.The buffer layer 130 can be the single layer structure that a certain material or multiple material are mixed to form,
It can be multilayer lamination structure.It is the effect of further Promoting Layered Buffer layer 130 when the buffer layer 130 is multilayer lamination structure
Fruit can make the stacking direction along the transistor device 10, the aluminium content of the buffer layer 130 is gradually during the preparation process
It reduces, the lattice constant of the buffer layer 130 is gradually increased.
For example, the hierarchical structure of the buffer layer 130 may is that aln layer, mixed layer, gallium nitride layer and gallium nitride
Layer.Wherein, aln layer covers the patterned layer 120 and the second area 1142, the third region 1143.Mixed layer
The aln layer is covered, the mixed layer includes gallium nitride and aluminium nitride.Gallium nitride layer covers the mixed layer.Gallium nitride
Layer covers the gallium nitride layer.
Further, in the buffer layer 130, the variation of the aluminium content can be stepped variation.For example, described
When buffer layer 130 is multilayered structure, the first level close to the substrate 110, aluminium content 30% may is that；Covering institute
State the second level of the first level, aluminium content 15%, the third level far from the substrate 110, aluminium content 0.Institute
The variation for stating aluminium content is also possible to change linearly, i.e., in the buffer layer 130, along the stacking of the transistor device 10
Direction, the aluminium content gradually decrease.Likewise, the variation of the lattice constant of the buffer layer 130 stepped can also become
Change or linear change.I.e. along the stacking direction of the transistor device 10, the lattice constant of the buffer layer 130 increases in interim
Big or gradual linear increase.
In one embodiment, as shown in figure 9, the device layer 140 of the transistor device 10 includes: high value layer
141, channel layer 142, Two-dimensional electron gas-bearing formation 143, barrier layer 144 and coating 145.
Specifically, the planarization surface 132 is completely covered in the high value layer 141.The high value layer 141 can be
The gallium nitride layer of high value or the aluminium nitrogen gallium layer of high value.The gallium nitride layer of the high value can be the gallium nitride of carbon doping
Layer, is also possible to the gallium nitride layer of Fe2O3 doping.The aluminium nitrogen gallium layer of the high value can be the aluminium nitrogen gallium layer of carbon doping, can also be with
It is the aluminium nitrogen gallium layer of Fe2O3 doping.
The high value layer 141 is completely covered in the channel layer 142.The material of the channel layer 142 can be gallium nitride
With at least one of aluminum gallium nitride.
The channel layer 142 is completely covered in the Two-dimensional electron gas-bearing formation 143.The Two-dimensional electron gas-bearing formation 143 has on edge
It can be with the electronic population of free movement on 10 stacking direction of transistor device.
Two-dimensional electron gas-bearing formation 143 described in 144 all standing of barrier layer.The material of the barrier layer 144 can be aluminum gallium nitride, aluminium
At least one of indium nitrogen and aluminium nitride.Wherein, the lattice coefficient of the barrier layer 144 is less than the lattice coefficient of the channel layer 142.
The barrier layer 144 can be single-layer or multi-layer stacking.When the barrier layer 144 is multiple-level stack, the stacking of the barrier layer 144 is former
Then are as follows: the level lattice coefficient closer to the channel layer 142 is smaller, and the maximum lattice coefficient of the barrier layer 144 is less than institute
State the lattice coefficient of channel layer 142.
The barrier layer 144 is completely covered in the coating 145.The material of the coating 145 can be gallium nitride, N-type
Gallium nitride, p-type gallium nitride, indium gallium nitrogen, p-type indium gallium nitrogen, N-type indium gallium nitrogen, aluminium nitrogen gallium, N-type aluminium nitrogen gallium, p-type aluminium nitrogen gallium, aluminium indium
Any one of nitrogen, N-type aluminium indium nitrogen and p-type aluminium indium nitrogen.
Further, in one of the embodiments, as shown in figure 9, the grid 151 is set to the coating 145 far
Surface from the barrier layer 144, and upright projection of the grid 151 on the first surface 114 is located at firstth area
In domain 1141.
In another embodiment, as shown in Figure 10, the grid 151 is embedded in inside the coating 145, and to described
Barrier layer 144 extends, to contact with the barrier layer 144.
In the embodiment, the grid 151 is contacted with the barrier layer 144, can increase the grid 151 and the device
Schottky contacts between layer 140, to reinforce the working effect of the transistor device 10.
In one embodiment, the gap 1402 extends since the device layer surface 1401 to the substrate 110.
Wherein, the gap 1402 at least extends to the Two-dimensional electron gas-bearing formation 143 from the device layer surface 1401.
Specifically, when the device layer 140 includes high value layer 141, channel layer 142, Two-dimensional electron gas-bearing formation 143, barrier layer
144 and when coating 145, surface of the coating 145 far from the barrier layer 144 is device layer surface 1401.At this point, described
Since the device layer surface 1401, the opposite direction along the stacking direction of the transistor device 10 extends in gap 1402, and
At least extend to the Two-dimensional electron gas-bearing formation 143.10 layers of the transistor device, allows gap 1402 at least extend to Two-dimensional electron
Gas-bearing formation 143, source electrode 152 and drain electrode 153 can extend to the Two-dimensional electron gas-bearing formation 143 along the gap 1402.Due to two dimension
There is the electronic population that largely can move freely in electronics gas-bearing formation 143, therefore, can be increased source electrode 152 and drain electrode 153 and the device
Ohmic contact between part layer 140, to reduce contact resistance.
Each technical characteristic of embodiment described above can be combined arbitrarily, for simplicity of description, not to above-mentioned reality
It applies all possible combination of each technical characteristic in example to be all described, as long as however, the combination of these technical characteristics is not deposited
In contradiction, all should be considered as described in this specification.
The embodiments described above only express several embodiments of the present invention, and the description thereof is more specific and detailed, but simultaneously
It cannot therefore be construed as limiting the scope of the patent.It should be pointed out that coming for those of ordinary skill in the art
It says, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to protection of the invention
Range.Therefore, the scope of protection of the patent of the invention shall be subject to the appended claims.
Claims (16)
1. a kind of transistor device characterized by comprising
Substrate (110) has the first surface (114) and second surface (112) being oppositely arranged, first surface (114) packet
First area (1141) are included, and second area (1142) adjacent with the first area (1141) respectively and third region
(1143)；
Patterned layer (120) covers the first area (1141)；
Buffer layer (130) covers the patterned layer (120) and the second area (1142), third region (1143), described
Buffer layer (130) has the planarization surface (132) far from the substrate (110)；
Device layer (140), covers the planarization surface (132), and the device layer (140) includes far from the planarization surface
(132) device layer surface (1401)；Along the opposite direction of the stacking direction of the transistor device (10), the device layer
(140) positioned at the second area (1142) and third region (1143) part with from the device layer surface (1401) to
The gap (1402) that the substrate (110) extends；
Grid (151) covers the device layer surface (1401), and the grid (151) is on the first surface (114)
Upright projection is located in the first area (1141)；
Source electrode (152) and drain electrode (153), cover the device layer surface (1401), and the source electrode (152) is in first table
Upright projection on face (114) is located in the second area (1142), and the drain electrode (153) is in the first surface (114)
On upright projection be located in the third region (1143), the source electrode (152) and the drain electrode (153) are also along the gap
(1402) extend.
2. transistor device according to claim 1, which is characterized in that the substrate (110) is gallium nitride substrate, carbonization
Silicon substrate, Sapphire Substrate, silicon substrate, diamond substrate, boron nitride substrate, aluminium nitride substrate, zinc oxide substrate, gallium oxide substrate
With aluminium-doped zinc oxide substrate any one.
3. transistor device according to claim 1, which is characterized in that the patterned layer (120) includes multiple adjacent
Graphical unit (122)；
Stacking direction along the transistor device (10), at least part of cross-sectional area of the graphical unit (122)
It is gradually reduced.
4. transistor device according to claim 3, which is characterized in that along the stacking side of the transistor device (10)
To the section shape of the graphical unit (122) is triangle or trapezoidal.
5. transistor device according to claim 4, which is characterized in that the graphical unit (122) include triangular prism,
At least one of quadrangular, pyramid, circular cone, terrace with edge or rotary table.
6. transistor device according to claim 1, which is characterized in that the patterned layer (120) has far from described
4th surface (1204) of substrate (110)；
4th surface (1204) has two or more pits (124), and the pit (124) is from the 4th table
Face (1204) concaves towards the inside of the patterned layer (120).
7. transistor device according to claim 6, which is characterized in that the opening area of the pit (124) is greater than institute
State the bottom area of pit (124).
8. transistor device according to claim 7, which is characterized in that along the stacking side of the transistor device (10)
To the section shape of the pit (124) is inverted trapezoidal or up-side down triangle.
9. transistor device according to claim 8, which is characterized in that the buffer layer (130) includes aluminium nitride, nitridation
At least one of gallium, aluminum gallium nitride, aluminium indium nitrogen and aluminium indium gallium nitrogen.
10. transistor device according to claim 9, which is characterized in that along the stacking side of the transistor device (10)
To the lattice constant of the buffer layer (130) is bigger, and the aluminium content in the buffer layer (130) gradually decreases.
11. transistor device according to claim 10, which is characterized in that the aluminium content in the buffer layer (130) is in
Change in ladder shape or linear change.
12. transistor device according to claim 1, which is characterized in that the device layer (140) includes:
High value layer (141) covers the buffer layer (130)；
Channel layer (142) covers the high value layer (141)；
Two-dimensional electron gas-bearing formation (143) covers the channel layer (142)；
Barrier layer (144) covers the Two-dimensional electron gas-bearing formation (143)；
Coating (145) covers the barrier layer (144).
13. transistor device according to claim 12, which is characterized in that the grid (151) is set to the coating
(145) surface of separate barrier layer (144), and upright projection position of the grid (151) on the first surface (114)
In the first area (1141).
14. transistor device according to claim 13, which is characterized in that the grid (151) is embedded in the coating
(145) internal, and extend to the barrier layer (144), to be contacted with the barrier layer (144).
15. transistor device according to claim 12, which is characterized in that the gap (1402) is from the device layer table
Face (1401) extends to the Two-dimensional electron gas-bearing formation (143).
16. a kind of preparation method of transistor device characterized by comprising
It provides substrate (110), the substrate (110) has the first surface (114) and second surface (112) being oppositely arranged, institute
Stating first surface (114) includes first area (1141), and second area adjacent with the first area (1141) respectively
(1142) and third region (1143)；
It prepares patterned layer (120), covers the first area (1141)；
Buffer layer (130) are prepared, the patterned layer (120) and the second area (1142), third region (1143) are covered,
The buffer layer (130) has the planarization surface (132) far from the patterned layer (120)；
It prepares device layer (140), covers the planarization surface (132), the device layer (140) includes far from the planarization
The device layer surface (1401) on surface (132)；
Grid (151) are prepared, the device layer surface (1401) are covered, and make the grid (151) in the first surface
(114) upright projection is located in the first area (1141)；
Source electrode (152) and drain electrode (153) are prepared, covers the device layer surface (1401), and make the source electrode (152) described
The upright projection of first surface (114) is located in the second area (1142), and the drain electrode (153) is in the first surface
(114) projection is located in the third region (1143)；
Heat the device layer (140), the source electrode (152) and drain electrode (153), formed from the device layer surface (1401) to
The gap (1402) that the substrate (110) extends, and the source electrode (152) and the drain electrode (153) is made to penetrate into the gap
(1402) in.
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| CN201910360966.9A CN109980002A (en) | 2019-04-30 | 2019-04-30 | Transistor device and preparation method thereof |
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| CN201910360966.9A CN109980002A (en) | 2019-04-30 | 2019-04-30 | Transistor device and preparation method thereof |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113257675A (en) * | 2021-05-12 | 2021-08-13 | 智程半导体设备科技(昆山)有限公司 | Preparation method of semiconductor device with high heat dissipation performance and semiconductor device |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113257675A (en) * | 2021-05-12 | 2021-08-13 | 智程半导体设备科技(昆山)有限公司 | Preparation method of semiconductor device with high heat dissipation performance and semiconductor device |
| CN113257675B (en) * | 2021-05-12 | 2022-02-01 | 智程半导体设备科技(昆山)有限公司 | Preparation method of semiconductor device with high heat dissipation performance and semiconductor device |
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