CN113257675B - Preparation method of semiconductor device with high heat dissipation performance and semiconductor device - Google Patents
Preparation method of semiconductor device with high heat dissipation performance and semiconductor device Download PDFInfo
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- CN113257675B CN113257675B CN202110513855.4A CN202110513855A CN113257675B CN 113257675 B CN113257675 B CN 113257675B CN 202110513855 A CN202110513855 A CN 202110513855A CN 113257675 B CN113257675 B CN 113257675B
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 32
- 230000017525 heat dissipation Effects 0.000 title claims abstract description 23
- 238000002360 preparation method Methods 0.000 title claims abstract description 15
- 239000010432 diamond Substances 0.000 claims abstract description 115
- 229910003460 diamond Inorganic materials 0.000 claims abstract description 107
- 239000000758 substrate Substances 0.000 claims abstract description 41
- 238000000034 method Methods 0.000 claims abstract description 27
- 238000005530 etching Methods 0.000 claims abstract description 25
- 238000000151 deposition Methods 0.000 claims abstract description 14
- 238000004528 spin coating Methods 0.000 claims abstract description 12
- 238000001035 drying Methods 0.000 claims abstract description 5
- 229910002704 AlGaN Inorganic materials 0.000 claims description 25
- 230000004888 barrier function Effects 0.000 claims description 25
- 238000004519 manufacturing process Methods 0.000 claims description 16
- 238000001312 dry etching Methods 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 9
- 230000006911 nucleation Effects 0.000 claims description 9
- 238000010899 nucleation Methods 0.000 claims description 9
- 238000004140 cleaning Methods 0.000 claims description 8
- 238000002161 passivation Methods 0.000 claims description 8
- 238000005229 chemical vapour deposition Methods 0.000 claims description 6
- 239000000377 silicon dioxide Substances 0.000 claims description 6
- 239000003153 chemical reaction reagent Substances 0.000 claims description 4
- XEMZLVDIUVCKGL-UHFFFAOYSA-N hydrogen peroxide;sulfuric acid Chemical group OO.OS(O)(=O)=O XEMZLVDIUVCKGL-UHFFFAOYSA-N 0.000 claims description 4
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 claims description 4
- 239000011148 porous material Substances 0.000 claims description 4
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 3
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 3
- 238000001259 photo etching Methods 0.000 claims description 3
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 3
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims description 3
- 239000013043 chemical agent Substances 0.000 claims description 2
- 238000005516 engineering process Methods 0.000 claims description 2
- 235000012239 silicon dioxide Nutrition 0.000 claims description 2
- 239000000463 material Substances 0.000 abstract description 7
- 238000000206 photolithography Methods 0.000 abstract description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 58
- 229910002601 GaN Inorganic materials 0.000 description 57
- 238000009616 inductively coupled plasma Methods 0.000 description 6
- 229910052681 coesite Inorganic materials 0.000 description 4
- 229910052906 cristobalite Inorganic materials 0.000 description 4
- 239000013078 crystal Substances 0.000 description 4
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 4
- 229910052682 stishovite Inorganic materials 0.000 description 4
- 229910052905 tridymite Inorganic materials 0.000 description 4
- 230000007547 defect Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 239000002159 nanocrystal Substances 0.000 description 3
- 239000002245 particle Substances 0.000 description 3
- 239000011248 coating agent Substances 0.000 description 2
- 238000000576 coating method Methods 0.000 description 2
- 238000009826 distribution Methods 0.000 description 2
- -1 hydrogen sulfate peroxide Chemical class 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 238000001039 wet etching Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 239000008204 material by function Substances 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910010271 silicon carbide Inorganic materials 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3672—Foil-like cooling fins or heat sinks
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/373—Cooling facilitated by selection of materials for the device or materials for thermal expansion adaptation, e.g. carbon
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/107—Substrate region of field-effect devices
- H01L29/1075—Substrate region of field-effect devices of field-effect transistors
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
- H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
- H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
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Abstract
The invention provides a preparation method of a semiconductor device with high heat dissipation performance, which comprises the following steps: s1 preparation of a substrate: uniformly spin-coating a spin-coating solution of diamond nano-grains on the surface of the Si substrate, drying, and depositing a polycrystalline diamond film; s2: preparing a mask: depositing SiO on the polycrystalline diamond film2Layer on SiO by photolithography and etching process2Forming a periodically patterned SiO layer on the layer2A hole; the semiconductor device embeds diamond materials with ultrahigh heat conductivity between GaN, so that the prepared GaN epitaxial structure has good heat conductivity, and lays a foundation for the realization of follow-up GaN-based microwave high-power devices.
Description
Technical Field
The invention relates to the field of semiconductor preparation, in particular to a preparation method of a semiconductor device with high heat dissipation performance and the semiconductor device.
Background
Gallium nitride (GaN) is used as a wide bandgap semiconductor material, has an excellent material quality factor, and most of high-efficiency power devices and power electronic devices, such as High Electron Mobility Transistor (HEMT) devices, are made of GaN materials. At present, a substrate commonly adopted by a GaN HEMT device is GaN, silicon carbide (SiC) or silicon (Si), and with the continuous improvement of the power density of the device, the heat dissipation of the GaN HEMT device based on the substrate becomes an important problem which restricts the performance of the device. The heat dissipation performance of the semiconductor device is poor, and the actual performance of the device is greatly influenced.
The diamond material has ultrahigh heat dissipation performance, and the thermal conductivity of the single crystal diamond at room temperature is generally more than 2000W/mK, which is equivalent to 5 times that of metallic copper. The thermal conductivity of diamond polycrystalline films prepared by artificial Chemical Vapor Deposition (CVD) is influenced by the structure and quality of the films, and the thermal conductivity of high-quality polycrystalline films can approach or reach to dayBut the level of diamond. The diamond has extremely low thermal expansion coefficient of 1.0 × 10 at room temperature-6 K-1. The excellent thermal properties enable the diamond to have very important application prospects in the aspect of thermal management of semiconductor optoelectronic devices, and are incomparable with other functional materials. However, in the prior art, for example, patent publication numbers are as follows: the invention of CN110223918B adopts deep-hole internal growth diamond, and it is difficult to directly grow diamond crystal without using nucleation material on heterogeneous substrate, even if it is possible, the plasma (plasma) concentration and growth gas distribution in deep hole are very difficult to ensure, which causes the deep-hole internal growth diamond extremely difficult, and it is difficult to obtain stable diamond film layer. Even if the diamond layer is prepared in the deep groove, because the subsequent GaN growth lacks continuous height gradient, as shown in FIG. 2, cavities are easily formed on the top of the diamond when the GaN grows transversely, and the cavities become the heat dissipation bottleneck of the whole material, thereby greatly reducing the final heat dissipation effect.
Disclosure of Invention
In order to solve the technical problem, the invention provides a method for preparing a semiconductor device with high heat dissipation performance, which comprises the following steps:
s1 preparation of a substrate: selecting and cleaning a Si substrate, uniformly spin-coating a spin-coating solution of diamond nano-grains on the surface of the Si substrate, drying, and depositing a polycrystalline diamond film;
s2: preparing a mask: depositing a mask layer on the polycrystalline diamond film, and forming periodically patterned holes on the mask layer through photoetching and etching processes until the diamond is exposed;
s3: etching the polycrystalline diamond film until the Si substrate is partially exposed by dry etching; forming a conical or truncated cone-shaped diamond structure by controlling the etching angle;
s4: cleaning the etched Si substrate and diamond structure by using a chemical reagent;
s5: depositing an AlN nucleating layer and a GaN buffer layer on the Si substrate by an MOCVD transverse epitaxial growth technology, wherein the GaN buffer layer grows transversely on the diamond structures and fills the diamond structures until all the diamond structures are covered and a plane is formed;
s6: growing an AlN insert layer and an AlGaN barrier layer on the GaN buffer layer in sequence; and manufacturing a source electrode and a drain electrode on the AlGaN barrier layer, and manufacturing a gate electrode on the AlGaN barrier layer between the source electrode and the gate electrode to obtain the GaN semiconductor device.
Preferably, the polycrystalline diamond film is deposited by microwave plasma chemical vapor deposition, and the thickness of the polycrystalline diamond film is 1-2 microns.
Preferably, the period of the holes is 2-4 microns, and the pore diameter is 1-3 microns.
Preferably, the etching angle in S3 is controlled by the upper and lower electrode power of the ICP process.
Preferably, the AlN nucleation layer is 1-5 nm.
Preferably, the GaN buffer layer is 2-5 microns.
Preferably, in S6, performing active region mesa isolation on the GaN buffer layer to divide the GaN buffer layer into 3 regions, and after preparing source and drain regions on both sides, fabricating passivation layers on the source, the drain, and the GaN buffer layer; and removing the passivation layer on the source electrode and the drain electrode after preparing the grid electrode at the middle position.
Preferably, the mask layer is one of silicon dioxide, silicon nitride or titanium oxide.
Preferably, the chemical agent is sulfuric acid hydrogen peroxide.
A semiconductor device comprises a substrate, wherein a plurality of conical diamonds are arranged on the substrate, an AlN nucleating layer is arranged between the diamonds, a GaN buffer layer is arranged on the AlN nucleating layer, the GaN buffer layer is filled between diamond structures and forms a plane at the top of the diamond structures, an AlN inserting layer and an AlGaN barrier layer are arranged at the upper part of each diamond structure, and a grid electrode, a source electrode and a drain electrode are arranged on the AlGaN barrier layer.
The semiconductor device and the preparation method thereof with high heat dissipation have the following beneficial effects: in addition, the used spin-coating diamond nanocrystalline coating and the conical diamond growing process simplify the diamond growing process, the diamond is uniformly distributed, and no cavity exists after the gallium nitride grows, so that the heat dissipation capacity of the semiconductor device is greatly improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below.
FIG. 1 is a schematic process flow diagram of example 1 of the present invention;
FIG. 2 is a schematic diagram of GaN growth after deep trench embedding of diamond;
FIG. 3 is a schematic process flow diagram of example 2 of the present invention;
wherein, 1, a substrate; 2. a polycrystalline diamond film; 3. a mask layer; 4. a hole; 5. a diamond structure; 6. an AlN nucleating layer; 7. a GaN buffer layer; 8. an AlN insertion layer; 9. an AlGaN barrier layer; 10. a source electrode; 11. a gate electrode; 12. and a drain electrode.
Detailed Description
The technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention.
Example 1
The invention provides a preparation method of a semiconductor device with high heat dissipation performance, which comprises the following steps: the diamond structure comprises a substrate 1, wherein a plurality of conical diamond structures 5 are arranged on the substrate 1 in an arrayed mode, an AlN nucleating layer 6 is arranged between the diamond structures 5, a GaN buffer layer 7 is arranged on the AlN nucleating layer 6, the GaN buffer layer 7 is filled between the diamond structures 5, a plane is formed at the top of each diamond structure 5, an AlN insert layer 8 and an AlGaN barrier layer 9 are arranged on the upper portion of each diamond structure 5, and a grid 11, a source electrode 10 and a drain electrode 12 are arranged on the AlGaN barrier layer 9.
The preparation process comprises the following steps: as shown in figure 1 of the drawings, in which,
s1 preparation of substrate 1: selecting and cleaning a Si or sapphire and silicon carbide substrate 1, selecting and using Si in the embodiment, uniformly spin-coating a spin-coating solution of diamond nano-grains on the surface of the Si substrate 1, drying, and depositing a polycrystalline diamond film 2; the nanocrystals will provide nucleation for subsequent polycrystalline diamond growth. Depositing a high-quality polycrystalline diamond film 2 with the thickness of 1-2 microns by Microwave Plasma Chemical Vapor Deposition (MPCVD); compared with the diamond generated in a deep groove mode in the prior art, the diamond coating can be generated in a mode of spin-coating the diamond nano crystal grains, and because the plasma gas concentration and the growth gas distribution in the groove are extremely difficult to ensure, the growth in the deep groove is difficult, and a stable diamond film layer cannot be obtained.
S2: preparing a mask: depositing a mask layer 3 on the polycrystalline diamond film 2, wherein the mask layer can be made of SiO2Or silicon nitride or titanium oxide, the mask layer in this embodiment is preferably SiO2By photolithography and etching processes, dry etching or wet etching can be used here on SiO2Forming periodically patterned holes 4 in the layer until the diamond 2 is exposed; the holes 4 have a period of 3 microns and a pore diameter of 2 microns. SiO 22The layer serves as a mask for subsequent etching of the polycrystalline diamond film 2.
S3: etching the polycrystalline diamond film 2, and etching the polycrystalline diamond film 2 by dry etching, preferably by ICP (inductively coupled plasma) dry etching, until the Si substrate 1 is partially exposed; forming a conical diamond structure 5 by controlling the etching angle, etching the diamond into the conical structure by ICP dry etching and controlling the voltage of the upper electrode and the lower electrode, the etching time and other process parameters, and simultaneously etching the SiO on the upper part of the diamond2The layer is also etched away; the conical structure of etching can guarantee that when follow-up growth GaN, GaN lateral growth reaches the toper top, can not form the cavity at the diamond top, and current deep groove diamond structure 5 lacks high gradient during GaN lateral growth, leads to the lateral growth to merge back top position and has more cavities, can cause the heat-sinking capability greatly reduced in the in-service use.
S4: cleaning the etched Si substrate 1 and the diamond structure 5 by using a chemical reagent, wherein the chemical reagent can be acid solution such as hydrogen sulfate peroxide, and the like, and the surface is cleaned by using the hydrogen sulfate peroxide to clean the surface because the surface has more particles (particles) after dry etching;
s5: the AlN nucleation layer 6 and the GaN buffer layer 7 are deposited on the Si substrate 1 by MOCVD epitaxial growth techniques. The AlN nucleating layer 6 is 3nm, the GaN buffer layer 7 grows around the diamond structures 5 in a transverse mode, and the diamond structures 5 are filled until all the diamond structures 5 are covered and a plane is formed; because the nucleation energy of GaN and/or AlN on the surface of polycrystalline diamond is much larger than that on monocrystalline silicon, selective growth of GaN can be controlled under proper growth conditions, i.e. GaN starts to nucleate and grow only on monocrystalline silicon substrate 1, and after the thickness of GaN is larger than that of diamond film, GaN grows laterally while continuing to grow thick. The GaN of the adjacent opening areas grows transversely until being combined to form a continuous GaN buffer layer. The GaN buffer layer 7 is 3 micrometers, and due to the fact that the combined GaN buffer layer is provided with the diamond gradient at the lower portion, no cavity exists after combination, crystal quality is high, defect density is low, and heat conductivity is greatly improved.
S6: an AlN insert layer 8 and an AlGaN barrier layer 9 are sequentially grown on the GaN buffer layer 7; and manufacturing a source electrode and a drain electrode on the AlGaN barrier layer 9, and manufacturing a gate electrode on the AlGaN barrier layer 9 between the source electrode 10 and the gate electrode 11 to obtain the GaN semiconductor device, wherein the specific mode is as follows: performing active region mesa isolation on the AlGaN barrier layer 9, dividing the AlGaN barrier layer into 3 regions, preparing source 10 and drain 12 regions on two sides, and then manufacturing passivation layers on the source 10, the drain 12 and the GaN buffer layer to prevent the GaN buffer layer from being affected when a grid 11 is prepared; after the gate electrode 11 is formed at the middle position, the passivation layer on the source electrode and the drain electrode is removed.
Example 2
In this example, similarly to example 1, the difference is that the diamond structure 5 is in the form of a truncated cone with a very small top, specifically:
the invention provides a preparation method of a semiconductor device with high heat dissipation performance, which comprises the following steps: the diamond substrate comprises a substrate 1, wherein a plurality of truncated cone-shaped diamonds are arranged on the substrate 1 in an arrayed manner, an AlN nucleating layer 6 is arranged between the diamonds, a GaN buffer layer 7 is arranged on the AlN nucleating layer 6, the GaN buffer layer 7 is filled between the diamonds and forms a plane on the tops of the diamonds, an AlN insert layer 8 and an AlGaN barrier layer 9 are arranged on the upper portion of the diamond, and a grid 11, a source electrode 10 and a drain electrode 12 are arranged on the AlGaN barrier layer 9.
The preparation process comprises the following steps: as shown in figure 3 of the drawings,
s1 preparation of substrate 1: selecting and cleaning a Si substrate 1, uniformly spin-coating a spin-coating solution of diamond nano-crystalline grains on the surface of the Si substrate 1, drying, and depositing a polycrystalline diamond film 2; the nanocrystals will provide nucleation for subsequent polycrystalline diamond growth. Depositing a high-quality polycrystalline diamond film 2 with a thickness of 1 micron by Microwave Plasma Chemical Vapor Deposition (MPCVD);
s2: preparing a mask: depositing a mask layer 3 on the polycrystalline diamond film 2, wherein the mask layer is still SiO2,Forming a periodically patterned hole 4 on the mask layer 3 by photoetching and etching processes, wherein dry etching or wet etching can be used; the holes 4 have a period of 2 microns and a pore diameter of 1 micron. SiO 22The layer serves as a mask for subsequent etching of the polycrystalline diamond film 2.
S3: etching the polycrystalline diamond film 2, and etching the polycrystalline diamond film 2 by ICP dry etching until part of the polycrystalline diamond film 2 is exposed out of the Si substrate 1; forming a truncated cone-shaped diamond structure 5 by controlling the etching angle, etching the diamond into a truncated cone shape by ICP dry etching and controlling the voltage of two electrodes, wherein partial SiO is still arranged on the top of the truncated cone-shaped diamond2Masking film, reducing the requirement for dry etching process, and etching the residual SiO by wet method2Removing; the structure of sculpture round platform shape can guarantee horizontal growth when follow-up growth GaN, and round platform top diameter is 0.3 micron, compares vertical diamond structure 5, and complete fore-and-aft growth, top position have more hole, can cause the heat-sinking capability greatly reduced in the in-service use.
S4: cleaning the etched Si substrate 1 and the diamond structure 5 by using sulfuric acid hydrogen peroxide, wherein the surface is cleaned by using sulfuric acid hydrogen peroxide because the surface is etched by a dry method and has more particles;
s5: the AlN nucleation layer 6 and the GaN buffer layer 7 are deposited on the Si substrate 1 by MOCVD lateral epitaxial growth techniques. The AlN nucleating layer 6 is 4nm, the GaN buffer layer 7 grows transversely on the diamond structures 5 and fills the diamond structures 5 until all the diamond structures 5 are covered and a plane is formed; because the nucleation energy of GaN and/or AlN on the surface of polycrystalline diamond is much larger than that on monocrystalline silicon, selective growth of GaN can be controlled under proper growth conditions, i.e. GaN starts to nucleate and grow only on monocrystalline silicon substrate 1, and after the thickness of GaN is larger than that of diamond film, GaN grows laterally while continuing to grow thick. The GaN of the adjacent opening areas grows transversely until being combined to form a continuous GaN buffer layer. The GaN buffer layer 7 is 3 micrometers, and due to the fact that the combined GaN buffer layer is provided with the diamond at the lower portion in a gradient mode, no cavity exists after combination, crystal quality is high, defect density is low, and thermal conductivity is greatly improved without defects.
S6: an AlN insert layer 8 and an AlGaN barrier layer 9 are sequentially grown on the GaN buffer layer 7; a source 10 and a drain 12 are formed on the AlGaN barrier layer 9, and a gate electrode is formed on the AlGaN barrier layer 9 between the source 10 and the gate 11, so as to obtain the GaN semiconductor device, specifically: performing active region mesa isolation on the AlGaN barrier layer 9, dividing the AlGaN barrier layer into 3 regions, preparing source 10 and drain 12 regions on two sides, and then manufacturing passivation layers on the source 10, the drain 12 and the GaN buffer layer to prevent the GaN buffer layer from being affected when a grid 11 is prepared; after the gate electrode 11 is formed at the middle position, the passivation layer on the source electrode and the drain electrode is removed.
Claims (10)
1. A method for manufacturing a semiconductor device with high heat dissipation performance is characterized by comprising the following steps:
s1 preparation of a substrate: selecting and cleaning a Si substrate, uniformly spin-coating a spin-coating solution of diamond nano-grains on the surface of the Si substrate, drying, and depositing a polycrystalline diamond film;
s2: preparing a mask: depositing a mask layer on the polycrystalline diamond film, and forming periodically patterned holes on the mask layer through photoetching and etching processes until the diamond is exposed;
s3: etching the polycrystalline diamond film until the Si substrate is partially exposed by dry etching; forming a conical or truncated cone-shaped diamond structure by controlling the etching angle;
s4: cleaning the etched Si substrate and diamond structure by using a chemical reagent;
s5: depositing an AlN nucleating layer and a GaN buffer layer on the Si substrate by an MOCVD transverse epitaxial growth technology, wherein the GaN buffer layer grows transversely on the diamond structures and fills the diamond structures until all the diamond structures are covered and a plane is formed;
s6: growing an AlN insert layer and an AlGaN barrier layer on the GaN buffer layer in sequence; and manufacturing a source electrode and a drain electrode on the AlGaN barrier layer, and manufacturing a gate electrode on the AlGaN barrier layer between the source electrode and the gate electrode to obtain the GaN semiconductor device.
2. The method for manufacturing a semiconductor device having high heat dissipation property as claimed in claim 1, wherein the polycrystalline diamond film is deposited by microwave plasma chemical vapor deposition, and the thickness of the polycrystalline diamond film is 1-2 μm.
3. The method for manufacturing a semiconductor device with high heat dissipation performance as recited in claim 1, wherein the hole period is 2-4 μm and the pore size is 1-3 μm.
4. The method for manufacturing a semiconductor device having high heat dissipation property as recited in claim 1, wherein the etching angle in S3 is controlled by upper and lower electrode powers of the ICP process.
5. The method for manufacturing a semiconductor device with high heat dissipation performance as recited in claim 1, wherein the AlN nucleation layer is 1-5 nm.
6. The method for manufacturing a semiconductor device with high heat dissipation performance as recited in claim 1, wherein the GaN buffer layer is 2-5 μm.
7. The method for fabricating a semiconductor device with high heat dissipation capability as claimed in claim 1, wherein the GaN buffer layer is mesa-isolated in active region to be divided into 3 regions in S6, and a passivation layer is formed on the source electrode, the drain electrode and the GaN buffer layer after source and drain regions are formed on both sides; and removing the passivation layer on the source electrode and the drain electrode after preparing the grid electrode at the middle position.
8. The method for manufacturing a semiconductor device with high heat dissipation performance as recited in claim 1, wherein the mask layer is one of silicon dioxide, silicon nitride, and titanium oxide.
9. The method for manufacturing a semiconductor device with high heat dissipation performance as recited in claim 1, wherein the chemical agent is hydrogen peroxide sulfate.
10. A semiconductor device is characterized by comprising a substrate, wherein a plurality of conical diamond structures are arranged on the substrate, an AlN nucleating layer is arranged between the diamond structures, a GaN buffer layer is arranged on the AlN nucleating layer, the GaN buffer layer is filled between the diamond structures and forms a plane on the top of the diamond, an AlN inserting layer and an AlGaN barrier layer are arranged on the upper portion of the diamond, and a grid electrode, a source electrode and a drain electrode are arranged on the AlGaN barrier layer.
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| CN114038750B (en) * | 2021-11-05 | 2022-12-02 | 西安电子科技大学芜湖研究院 | Preparation method of gallium nitride power device |
| CN115663015B (en) * | 2022-10-19 | 2023-12-15 | 上海新微半导体有限公司 | Semiconductor device structure and preparation method thereof |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109980002A (en) * | 2019-04-30 | 2019-07-05 | 芜湖德豪润达光电科技有限公司 | Transistor device and preparation method thereof |
| CN110223918A (en) * | 2019-04-23 | 2019-09-10 | 西安电子科技大学 | A kind of aperture formula compound substrate gallium nitride device and preparation method thereof |
| CN110867483A (en) * | 2018-08-28 | 2020-03-06 | 江西兆驰半导体有限公司 | Epitaxial layer structure of GaN-based power semiconductor device on Si substrate and preparation method thereof |
| WO2020242494A1 (en) * | 2019-05-31 | 2020-12-03 | Texas State University | Incorporating semiconductors on a polycrystalline diamond substrate |
| CN112509996A (en) * | 2021-02-05 | 2021-03-16 | 浙江工商大学 | GaN device structure and preparation method |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TWI420693B (en) * | 2008-07-17 | 2013-12-21 | Advanced Optoelectronic Tech | Light emitting device and fabrication thereof |
| US9728483B2 (en) * | 2015-12-09 | 2017-08-08 | Honeywell Federal Manufacturing & Technologies, Llc | Method of forming an integrated circuit with heat-mitigating diamond-filled channels |
| CN108321270A (en) * | 2018-01-30 | 2018-07-24 | 安徽三安光电有限公司 | A kind of preparation method of light emitting diode |
-
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110867483A (en) * | 2018-08-28 | 2020-03-06 | 江西兆驰半导体有限公司 | Epitaxial layer structure of GaN-based power semiconductor device on Si substrate and preparation method thereof |
| CN110223918A (en) * | 2019-04-23 | 2019-09-10 | 西安电子科技大学 | A kind of aperture formula compound substrate gallium nitride device and preparation method thereof |
| CN109980002A (en) * | 2019-04-30 | 2019-07-05 | 芜湖德豪润达光电科技有限公司 | Transistor device and preparation method thereof |
| WO2020242494A1 (en) * | 2019-05-31 | 2020-12-03 | Texas State University | Incorporating semiconductors on a polycrystalline diamond substrate |
| CN112509996A (en) * | 2021-02-05 | 2021-03-16 | 浙江工商大学 | GaN device structure and preparation method |
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