CN109980000A - 增强型高电子迁移率晶体管元件及其形成方法 - Google Patents
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Abstract
本发明提供一种增强型高电子迁移率晶体管元件及其形成方法。该增强型高电子迁移率晶体管元件包括基板、通道层、阻挡层、P型半导体层、载子供应层、栅极、源极与漏极。通道层配置于基板上。阻挡层配置于通道层上。P型半导体层配置于阻挡层上。载子供应层配置于P型半导体层的侧壁上并侧向延伸以远离P型半导体层。栅极配置于P型半导体层上。源极与漏极配置于栅极两侧的载子供应层上。另提供一种增强型高电子迁移率晶体管元件的形成方法。本发明可有效增加输出电流,提升元件的效能。
Description
技术领域
本发明是有关于一种半导体元件,且特别是有关于一种增强型(enhancementmode)高电子迁移率晶体管(high electron mobility transistor;HEMT)元件及其形成方法。
背景技术
近年来,以III-V族化合物半导体为基础的HEMT元件因为其低阻值、高崩溃电压以及快速开关切换频率等特性,在高功率电子元件领域被广泛地应用。
一般来说,HEMT元件可分为消耗型或常开型晶体管元件,以及增强型或常关型晶体管元件。增强型晶体管元件因为其提供的附加安全性以及其更易于由简单、低成本的驱动电路来控制,因而在业界获得相当大的关注。
发明内容
有鉴于此,本发明提供一种增强型HEMT元件,通过配置载子供应层于栅极区域外的阻挡层或通道层上,可有效增加输出电流,提升元件的效能。
本发明提供一种增强型HEMT元件,其包括基板、通道层、阻挡层、P型半导体层、载子供应层、栅极、源极与漏极。通道层配置于基板上。阻挡层配置于通道层上。P型半导体层配置于阻挡层上。载子供应层配置于P型半导体层的侧壁上并侧向延伸以远离P型半导体层。栅极配置于P型半导体层上。源极与漏极配置于栅极两侧的载子供应层上。
在本发明的一实施例中,上述载子供应层的铝含量大于阻挡层的铝含量。
在本发明的一实施例中,上述载子供应层为单层结构。
在本发明的一实施例中,上述载子供应层为多层结构,且其铝含量随着远离通道层而减少。
在本发明的一实施例中,上述载子供应层的材料包括InAlGaN、AlGaN、AlInN、AlN、GaN或其组合。
在本发明的一实施例中,上述载子供应层于P型半导体层的侧壁上的厚度小于载子供应层于阻挡层的顶面上的厚度。
在本发明的一实施例中,上述增强型高电子迁移率晶体管元件更包括介电层,其配置于载子供应层上以及栅极与P型半导体层之间。
在本发明的一实施例中,上述载子供应层与阻挡层接触。
在本发明的一实施例中,上述阻挡层位于P型半导体层下方的厚度大于阻挡层位于P型半导体层两侧的厚度。
在本发明的一实施例中,上述P型半导体层具有倾斜侧壁。
在本发明的一实施例中,上述P型半导体层具有实质上垂直侧壁。
在本发明的一实施例中,上述载子供应层与通道层接触。
在本发明的一实施例中,上述通道层位于阻挡层下方的厚度大于通道层位于阻挡层两侧的厚度。
在本发明的一实施例中,上述P型半导体层具有倾斜侧壁。
本发明提供一种增强型高电子迁移率晶体管元件的形成方法,其包括以下步骤。于基板上依序形成通道层、阻挡层以及P型半导体层。于P型半导体层上形成罩幕层。将罩幕层的图案转移至P型半导体层中。于基板上形成载子供应层,其中载子供应层覆盖P型半导体层的侧壁。于P型半导体层两侧形成源极与漏极。于P型半导体层上形成栅极。
在本发明的一实施例中,上述罩幕层的图案更转移至部分阻挡层中。
在本发明的一实施例中,上述罩幕层的图案更转移至阻挡层以及部分通道层中。
在本发明的一实施例中,上述形成载子供应层的方法包括进行外延再成长工艺。
在本发明的一实施例中,上述载子供应层的铝含量大于阻挡层的铝含量。
在本发明的一实施例中,形成上述源极与漏极之前以及形成载子供应层之后,更包括形成介电层。
基于上述,通过配置载子供应层于栅极区域外的阻挡层或通道层上,可有效增加输出电流,提升元件的效能。此外,本发明的工艺步骤简单,可大幅提升外延成长以及元件设计的弹性。
为让本发明的上述特征和优点能更明显易懂,下文特举实施例,并配合所附图式作详细说明如下。
附图说明
图1A至图1F是依照本发明一些实施例所绘示的一种增强型HEMT元件的形成方法的剖面示意图。
图2至图10是依照本发明替代性实施例所绘示的多种增强型HEMT元件的剖面示意图。
附图标号
10、11、12、13、14、15、16、17、18、19:增强型HEMT元件
100:基板
101:缓冲层
102:通道层
104、104a:阻挡层
105:二维电子气
106、106a:P型半导体层
108:罩幕层
110、202、204、206、302、304、306、308:载子供应层
112:介电层
114:钝化层
D:漏极
G:栅极
S:源极
θ:夹角
具体实施方式
图1A至图1F是依照本发明一些实施例所绘示的一种增强型HEMT元件的形成方法的剖面示意图。
请参照图1A,于基板100上依序形成通道层102、阻挡层104以及P型半导体层106。在一实施例中,基板100的材料包括蓝宝石、Si、SiC或GaN。在一实施例中,通道层102的材料包括III族氮化物或III-V族化合物半导体材料。例如,通道层102的材料包括GaN。此外,通道层102可以是经掺杂或未经掺杂的层。在一实施例中,通道层102的形成方法包括进行外延成长工艺。
在一实施例中,缓冲层101视情况配置于基板100和通道层102之间,用以减少基板100和通道层102之间的晶格常数差异和热膨胀系数差异。在一实施例中,缓冲层101的材料包括III族氮化物或III-V族化合物半导体材料。例如,缓冲层101的材料包括InAlGaN、AlGaN、AlInN、InGaN、AlN、GaN或其组合。此外,缓冲层101可具有单层或多层结构。在一实施例中,缓冲层101的形成方法包括进行外延成长工艺。
在一实施例中,阻挡层104的材料包括III族氮化物或III-V族化合物半导体材料。例如,阻挡层104的材料包括InAlGaN、AlGaN、AlInN、AlN或其组合。在一实施例中,阻挡层104的材料包括AlxGa1-xN,其中x为0~1,例如为0.05~0.5、0.1~0.3或0.2~0.4。此外,阻挡层104可以是经掺杂或未经掺杂的层,并可具有单层或多层结构。在一实施例中,阻挡层104的形成方法包括进行外延成长工艺。
P型半导体层106配置于阻挡层104与后续形成的栅极G之间,用以形成二维电子气的断开区或者具有相对低的电子密度的区域。在一实施例中,P型半导体层106的材料包括III族氮化物或III-V族化合物半导体材料。例如,P型半导体层106的材料包括InAlGaN、AlGaN、InGaN、InAlN、GaN或InN或其组合,并掺杂有P型掺质(例如Mg)。在一实施例中,P型半导体层106可为P型GaN层。在一实施例中,P型半导体层106的形成方法包括进行外延成长工艺。
请参照图1B,于P型半导体层上形成罩幕层108。在一实施例中,罩幕层108的材料包括氧化硅、氮化硅、氮氧化硅或其组合。在一实施例中,罩幕层108的形成方法包括于P型半导体层106上沉积罩幕材料层,以及对罩幕材料层进行图案化工艺(例如光刻刻蚀工艺)。
请参照图1C,将罩幕层108的图案转移至P型半导体层106中。上述图案转移步骤包括将上层图案的形状及/或尺寸大致转移至一个或多个下层中。在一实施例中,以罩幕层108为刻蚀罩幕,进行刻蚀工艺,以将罩幕层108的图案不仅转移至P型半导体层106,更转移至部分阻挡层104中。上述刻蚀工艺包括干刻蚀工艺、湿刻蚀工艺或其组合。于上述图案转移步骤或刻蚀步骤之后,剩余的P型半导体层106称为P型半导体层106a。在一实施例中,于上述图案转移步骤或刻蚀步骤之后,阻挡层104位于P型半导体层106a下方的厚度大于阻挡层104位于P型半导体层106a两侧的厚度。在一实施例中,P型半导体层106a具有倾斜侧壁。更具体地说,P型半导体层106a的侧壁与阻挡层104的顶面之间的夹角θ为钝角。例如,夹角θ可为95、100、105、110、115、120、125、130、135、140、145、150、155、160、165、170、175度,包括任意两个前述数值之间的任何范围。
请参照图1D,于基板100上形成载子供应层110。在一实施例中,载子供应层110覆盖P型半导体层106的侧壁以及P型半导体层106两侧的阻挡层104的顶面。
在一实施例中,载子供应层110的材料包括III族氮化物或III-V族化合物半导体材料。在一实施例中,载子供应层110的材料可为四元氮化物、三元氮化物、二元氮化物或其组合。例如,载子供应层110的材料包括InAlGaN、AlGaN、AlInN、AlN、GaN或其组合。在一实施例中,载子供应层110的材料包括AlyGa1-yN,其中y为0~1,例如为0.05~0.5、0.1~0.3或0.2~0.4。在另一实施例中,载子供应层110的材料包括In1-x-yAlxGayN,其中x为0~1,y为0~1,且x例如为0.05~0.5、0.1~0.3或0.2~0.4。此外,载子供应层110可以是经掺杂或未经掺杂的层。在一实施例中,载子供应层110为单层结构。
在一实施例中,载子供应层110的形成方法包括进行外延再成长工艺。更具体地说,被罩幕层108覆盖的P型半导体层106a的顶面不会成长或形成任何外延层。因此,未被罩幕层108覆盖的P型半导体层106a的侧面以及阻挡层104的顶面可作为形成载子供应层110的再成长表面。在一实施例中,载子供应层110于P型半导体层106a的侧壁上的厚度小于载子供应层110于阻挡层104的顶面上的厚度。于上述外延再成长工艺之后,移除罩幕层108。
特别要注意的是,本发明的载子供应层110用以提供载子给邻接的阻挡层104,以增强阻挡层104的极化量以及载子浓度,进而降低通道层102的阻值,提高输出电流。在一实施例中,载子供应层110的铝含量等于或大于阻挡层104的铝含量。在一实施例中,阻挡层104的材料包括AlxGa1-xN,且载子供应层110的材料包括AlyGa1-yN,其中x为0~1,y为0~1,且y大于等于x。例如,阻挡层104的材料包括Al0.2Ga0.8N,且载子供应层110的材料包括Al0.3Ga0.7N。
在一实施例中,阻挡层104与载子供应层110的组成大致相同,例如均为三元氮化物,仅铝含量不同。在另一实施例中,阻挡层104与载子供应层110的组成可不同,例如阻挡层104为三元氮化物,而载子供应层110为四元化合物,且各自的铝含量也不同。
请参照图1E,于载子供应层110上视情况形成介电层112。在一实施例中,介电层112的材料包括氧化铝,且其形成方法包括进行合适的沉积工艺,例如化学气相沉积工艺。接着,于介电层112上形成钝化层114。在一实施例中,钝化层114的材料包括氧化硅,且其形成方法包括进行合适的沉积工艺,例如化学气相沉积工艺。
请参照图1F,于P型半导体层106a两侧形成源极S与漏极D。在一实施例中,源极S与漏极D配置在P型半导体层106a两侧的阻挡层104上,穿过钝化层114以及介电层112,并延伸至部分载子供应层110中。然而,本发明并不以此为限。在另一实施例中,源极S及/或漏极D中至少一者可延伸至通道层102中并电连接至二维电子气(2DEG)105。在一实施例中,源极S与漏极D的材料包括金属(例如Al、Ti、Ni、Au或其合金),或其他可与III-V族化合物半导体形成欧姆接触(ohmic contact)的材料。
接着,于P型半导体层106a上形成栅极G。在一实施例中,栅极G的材料包括金属或金属氮化物(例如Ta、TaN、Ti、TiN、W、Pd、Ni、Au、Al或其组合)、金属硅化物(例如WSix)或其他可与III-V族化合物半导体形成萧特基接触(Schottky contact)的材料。在一实施例中,栅极G未与P型半导体层106a接触,且介电层112位于栅极G与P型半导体层106a之间。在另一实施例中,当视情况省略介电层112的形成步骤时,栅极G会与P型半导体层106a直接接触。至此,完成本发明的增强型HEMT元件10的制作。
请参照图1F,本发明的增强型HEMT元件10包括基板100、通道层104、阻挡层104、P型半导体层106a、载子供应层110、栅极G、源极S与漏极D。通道层102配置于基板100上。阻挡层104配置于通道层102上。P型半导体层106a配置于阻挡层104上。载子供应层110配置于P型半导体层106a的侧壁上并侧向延伸以远离P型半导体层106a。在一实施例中,载子供应层110形成为单层结构(如图1D所示),且载子供应层110的铝含量大于阻挡层104的铝含量。在一实施例中,载子供应层110与阻挡层104接触。在一实施例中,于图1C的图案转移步骤中,罩幕层的图案转移至P型半导体层以及部分阻挡层中。因此,载子供应层110形成于P型半导体层106a的侧壁上并向外侧向延伸于阻挡层104上,如图1F所示。栅极G配置于P型半导体层106a上。源极S与漏极D配置于栅极G两侧的载子供应层110上。在一实施例中,介电层112配置于载子供应层110上以及栅极G与P型半导体层106a之间。
在上述实施例中,图1C的图案转移步骤的刻蚀深度以及图1D的载子供应层形成步骤的膜层结构,均可依工艺需要调整,而形成各种增强型HEMT元件。例如,图案转移步骤的刻蚀深度可深达通道层。例如,载子供应层为多层结构,且其铝含量随着远离通道层而减少。
图2至图10是依照本发明替代性实施例所绘示的多种增强型HEMT元件的剖面示意图。图2至图10的增强型HEMT元件11~19与图1F的增强型HEMT元件10类似,以下就差异处说明,相同处则不再赘述。
图2的增强型HEMT元件11与图1F的增强型HEMT元件10类似,其差异在于,图1F的增强型HEMT元件10的载子供应层110为单层结构,而图2的增强型HEMT元件11的载子供应层206为双层结构。在一实施例中,图2的载子供应层206包括(由下而上)载子供应层202以及载子供应层204,且载子供应层202的铝含量大于载子供应层204的铝含量。此外,载子供应层206的平均铝含量大于阻挡层104的铝含量。在一实施例中,阻挡层104的材料包括AlxGa1-xN,载子供应层202的材料包括AlyGa1-yN,载子供应层204的材料包括AlzGa1-zN,其中x为0~1,y为0~1,z为0~1,且y大于等于x,且y大于等于z。例如,阻挡层104的材料包括Al0.2Ga0.8N,载子供应层202的材料包括Al0.3Ga0.7N,载子供应层204的材料包括Al0.2Ga0.8N。在一实施例中,载子供应层202的厚度为载子供应层204的厚度的至少10倍或至少15倍。
图3的增强型HEMT元件12与图1F的增强型HEMT元件10类似,其差异在于,图1F的增强型HEMT元件10的载子供应层110为单层结构,而图3的增强型HEMT元件12的载子供应层308为三层结构。在一实施例中,图3的载子供应层308包括(由下而上)载子供应层302、载子供应层304以及载子供应层306,且载子供应层302的铝含量大于载子供应层304的铝含量,且载子供应层304的铝含量大于载子供应层306的铝含量。此外,载子供应层308的平均铝含量大于阻挡层104的铝含量。在一实施例中,阻挡层104的材料包括AlxGa1-xN,载子供应层302的材料包括AlyGa1-yN,载子供应层304的材料包括AlzGa1-zN,载子供应层304的材料包括AliGa1-iN,其中x为0~1,y为0~1,z为0~1,i为0~1,且其中y大于等于x,y大于等于z,且z大于等于i。例如,阻挡层104的材料包括Al0.2Ga0.8N,载子供应层302的材料包括Al0.3Ga0.7N,载子供应层304的材料包括Al0.2Ga0.8N,载子供应层306的材料包括GaN。在一实施例中,载子供应层302或载子供应层304的厚度为载子供应层306的厚度的至少10倍或至少15倍。
图4的增强型HEMT元件13与图1F的增强型HEMT元件10类似,其差异在于,图1F的增强型HEMT元件10的阻挡层104的中间厚度大于其两侧厚度,而图4的增强型HEMT元件13的阻挡层104的厚度大致上相同。更具体地说,在形成图4的增强型HEMT元件13的图案转移步骤中,罩幕层的图案仅转移至P型半导体层中。
图5的增强型HEMT元件14与图1F的增强型HEMT元件10类似,其差异在于,图1F的增强型HEMT元件10的P型半导体层106a具有倾斜侧壁,而图5的增强型HEMT元件14的P型半导体层106a具有实质上垂直侧壁。更具体地说,在图5的增强型HEMT元件14中,P型半导体层106a的侧壁与阻挡层104的顶面之间的夹角θ为直角。例如,夹角θ可为大约90。
图6的增强型HEMT元件15与图1F的增强型HEMT元件10类似,其差异在于,图1F的增强型HEMT元件10的载子供应层110配置于P型半导体层106a的侧壁上并向外侧向延伸于阻挡层104上,而图6的增强型HEMT元件15的载子供应层110配置于P型半导体层106a以及阻挡层104a的侧壁上并向外侧向延伸于通道层102上。在一实施例中,载子供应层110与通道层102接触。更具体地说,于图1C的图案转移步骤中,罩幕层的图案转移至P型半导体层、阻挡层以及部分通道层中。
图7的增强型HEMT元件16与图6的增强型HEMT元件15类似,其差异在于,图6的增强型HEMT元件15的载子供应层110为单层结构,而图7的增强型HEMT元件16的载子供应层206为双层结构。
图8的增强型HEMT元件17与图6的增强型HEMT元件15类似,其差异在于,图6的增强型HEMT元件15的载子供应层110为单层结构,而图8的增强型HEMT元件17的载子供应层308为三层结构。
图9的增强型HEMT元件18与图6的增强型HEMT元件15类似,其差异在于,图6的增强型HEMT元件15的通道层102的中间厚度大于其两侧厚度,而图9的增强型HEMT元件18的通道层102的厚度大致上相同。
图10的增强型HEMT元件19与图9的增强型HEMT元件18类似,其差异在于,图9的增强型HEMT元件18的P型半导体层106a具有倾斜侧壁,而图10的增强型HEMT元件19的P型半导体层106a具有实质上垂直侧壁。
特别要说明的是,在图6至图8的增强型HEMT元件15~17中,于通道层102的厚度不均一,P型半导体层106a的侧壁与通道层102的顶面之间的夹角θ必须为钝角,方能使二维电子气105沿着载子供应层110/206/308的转角形成于通道层102中。另一方面,在图9至图10的增强型HEMT元件18~19中,由于通道层102的厚度均一,P型半导体层106a的侧壁与通道层102的顶面之间的夹角θ可为钝角或直角,两者均能使二维电子气105形成于阻挡层104a与通道层102之界面下方。
综上所述,在本发明实施例中,在元件本质区(device intrinsic region)或栅极区域以外的区域执行载子供应层的外延再成长工艺,不仅可避免电性不均匀以及漏电流的问题,且可增加栅极区域以外的区域的载子浓度,以改善输出电流不足的问题。此外,本发明的工艺步骤简单,可大幅提升外延成长以及元件设计的弹性。
虽然本发明已以实施例揭露如上,然其并非用以限定本发明,任何所属技术领域中相关技术人员,在不脱离本发明的精神和范围内,当可作些许的更动与润饰,故本发明的保护范围当视权利要求所界定者为准。
Claims (12)
1.一种增强型高电子迁移率晶体管元件,其特征在于,包括:
一通道层,配置于一基板上;
一阻挡层,配置于该通道层上;
一P型半导体层,配置于该阻挡层上;
一载子供应层,配置于该P型半导体层的侧壁上并侧向延伸以远离该P型半导体层,且该载子供应层邻接于该阻挡层,其中该载子供应层的铝含量大于该阻挡层的铝含量;
一栅极,配置于该P型半导体层上;以及
一源极与一漏极,配置于该栅极两侧的该载子供应层上。
2.如权利要求1所述的增强型高电子迁移率晶体管元件,其特征在于,该载子供应层为单层结构。
3.如权利要求1所述的增强型高电子迁移率晶体管元件,其特征在于,该载子供应层为多层结构,且其铝含量随着远离该通道层而减少。
4.如权利要求1所述的增强型高电子迁移率晶体管元件,其特征在于,该载子供应层于该P型半导体层的侧壁上的厚度小于该载子供应层于该阻挡层的顶面上的厚度。
5.如权利要求1所述的增强型高电子迁移率晶体管元件,其特征在于,更包括一介电层,其配置于该载子供应层上以及该栅极与该P型半导体层之间。
6.如权利要求1所述的增强型高电子迁移率晶体管元件,其特征在于,该载子供应层与该阻挡层接触,且该阻挡层位于该P型半导体层下方的厚度大于该阻挡层位于该P型半导体层两侧的厚度。
7.如权利要求1所述的增强型高电子迁移率晶体管元件,其特征在于,该载子供应层与该通道层接触,且该通道层位于该阻挡层下方的厚度大于该通道层位于该阻挡层两侧的厚度。
8.一种增强型高电子迁移率晶体管元件的形成方法,其特征在于,包括:
于一基板上依序形成一通道层、一阻挡层以及一P型半导体层;
于该P型半导体层上形成一罩幕层;
将该罩幕层的图案转移至该P型半导体层中;
于该基板上进行外延再成长工艺形成一载子供应层,其中该载子供应层覆盖该P型半导体层的侧壁;
于该P型半导体层两侧形成一源极与一漏极;以及
于该P型半导体层上形成一栅极。
9.如权利要求8所述的增强型高电子迁移率晶体管元件的形成方法,其特征在于,该罩幕层的图案更转移至部分该阻挡层中。
10.如权利要求8所述的增强型高电子迁移率晶体管元件的形成方法,其特征在于,该罩幕层的图案更转移至该阻挡层以及部分该通道层中。
11.如权利要求8所述的增强型高电子迁移率晶体管元件的形成方法,其特征在于,该载子供应层的铝含量大于该阻挡层的铝含量。
12.如权利要求8所述的增强型高电子迁移率晶体管元件的形成方法,其特征在于,于形成该源极与该漏极之前以及形成该载子供应层之后,更包括形成介电层。
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CN111243954A (zh) * | 2020-01-19 | 2020-06-05 | 中国科学院半导体研究所 | GaN基常关型高电子迁移率晶体管及制备方法 |
CN112397584A (zh) * | 2019-08-14 | 2021-02-23 | 新唐科技股份有限公司 | 增强型高电子迁移率晶体管元件 |
CN112397583A (zh) * | 2019-08-13 | 2021-02-23 | 新唐科技股份有限公司 | 增强型高电子迁移率晶体管器件 |
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US11715790B2 (en) * | 2019-04-22 | 2023-08-01 | Intel Corporation | Charge-induced threshold voltage tuning in III-N transistors |
CN112447835A (zh) * | 2019-08-30 | 2021-03-05 | 广东致能科技有限公司 | 半导体器件及其制造方法 |
US20230108909A1 (en) * | 2020-06-24 | 2023-04-06 | Guangdong Zhineng Technology Co., Ltd. | Semiconductor Device, Manufacturing Method and Electronic Equipment |
US20240097016A1 (en) * | 2020-12-02 | 2024-03-21 | Analog Devices, Inc. | Compound semiconductor devices with a conductive component to control electrical characteristics |
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