CN107068748B - 半导体功率元件 - Google Patents

半导体功率元件 Download PDF

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CN107068748B
CN107068748B CN201610969377.7A CN201610969377A CN107068748B CN 107068748 B CN107068748 B CN 107068748B CN 201610969377 A CN201610969377 A CN 201610969377A CN 107068748 B CN107068748 B CN 107068748B
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CN107068748A (zh
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林奕志
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Epistar Corp
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Abstract

本发明公开一种半导体功率元件，包含：基板；主动区，具有凹陷区，位于基板上方；第一导电型半导体层，位于凹陷区上方，不与凹陷区相互重叠；栅极，位于该主动区上方，部分设置于凹陷区中；一介电层，位于主动区与栅极之间；以及二维电子气，形成于主动区之中。

Description

半导体功率元件
技术领域
本发明涉及一种半导体元件，更具体而言，是涉及一种半导体功率元件。
背景技术
近几年来，由于高频及高功率产品的需求与日俱增，以氮化镓为材料的半导体功率元件，如氮化铝镓-氮化镓(AlGaN/GaN)，因具高速电子迁移率、可达到非常快速的切换速度、可于高频、高功率及高温工作环境下操作的元件特性，故广泛应用在电源供应器(powersupply)、DC/DC整流器(DC/DC converter)、DC/AC换流器(AC/DC inverter)以及工业运用，其领域包含电子产品、不断电***、汽车、马达、风力发电等。
发明内容
本发明是关于一种半导体功率元件，包含一基板；一主动区具有一凹陷区，位于基板上方；一第一导电型半导体层位于主动区上方，不与该凹陷区相互重叠；一栅极位于主动区上方，部分设置于凹陷区中；一介电层位于主动区以及栅极之间；以及一二维电子气形成于主动区之中。
为让本发明的上述和其他目的、特征和优点能更明显易懂，下文特举较佳实施例，并配合所附附图，作详细说明如下。
附图说明
图1为本发明第一实施例的半导体功率元件的上视图；
图2A为本发明第二实施例的半导体单元的局部放大上视示意图；
图2B为图2A沿剖线FF的剖面示意图；
图2C为图2A中透视保护层及栅极的示意图；
图3A～图3F为本发明第二实施例的半导体单元制作流程图；
图4为本发明第二实施例中半导体单元的开启状态示意图；
图5A为本发明第三实施例的半导体单元的局部放大上视示意图；
图5B为图5A中透视保护层及栅极的示意图；
图5C为图5A沿剖线HH的剖面示意图；及
图6为本发明第四实施例的半导体单元示意图。
符号说明
1、2、3、5 半导体单元
100、300、500 主动区
101、301、501 基板
102、302、502 成核层
103、303、503 缓冲结构
1031、3031、5031 第一半导体叠层
1032、3032、5032 第二半导体叠层
104、304、504 通道层
105、305、505 阻障层
1051、3051、5051 第一上表面
106、106A、106B 第一导电型半导体层
306、506 第一导电型半导体层
1061A、3061、5061 第一侧边
1062A、3062、1062B 上表面
1061B、5063 第二侧边
107、307、507 介电层
108、308、508 源极
109、309、509 漏极
5062 第二上表面
5091、5101 侧边
110、310、510 栅极
111、311、511 保护层
1415、3435、5455 界面
2DEG 二维电子气
R 凹陷区
RW1 第一侧壁
RW2 第二侧壁
B 底部
D 深度
T 厚度
L1 第一长度
L2 第二长度
S 半导体功率元件
S108 源极垫
S109 漏极垫
S110 栅极垫
具体实施方式
以下实施例将伴随着附图说明本发明的概念，在附图或说明中，相似或相同的部分使用相同的标号，并且在附图中，元件的形状或厚度可扩大或缩小。需特别注意的是，图中未绘示或描述的元件，可以是熟悉此技术的人士所知的形式。
请参阅图1为本发明第一实施例的半导体功率元件S的上视图。半导体功率元件S例如为三端点的元件。在本实施例中，半导体功率元件S包含源极垫S108、漏极垫S109、栅极垫S110和至少一个半导体单元1。半导体单元1例如是场效晶体管(FET)，具体来说可以是高电子迁移率晶体管(HEMT)。在第一实施例中，半导体单元1包括与源极垫S108电连接的源极108、与漏极垫S109电连接的漏极109、与栅极垫S110电连接的栅极110，以及半导体叠层(未标示)，叠层的材料、位置与外观设计可依实际的需求而做调整。此外，半导体功率元件S所包含的至少一半导体单元1可被以下实施例中的半导体单元所取代，而半导体单元1的局部区域E也将于以下实施例中描述其细部结构。
请参阅图2A至图2C所示本发明第二实施例的半导体单元2。在本实施例中，半导体单元2可以用于取代图1的半导体单元1以形成半导体功率元件S。为了清楚说明半导体单元2的细部结构，图2A为半导体单元2的局部放大上视示意图，放大位置如图1的区域E所示；图2B为图2A沿剖线FF的剖面示意图。半导体单元2例如为常关型晶体管(Enhancement ModeDevice,E-Mode)，包括基板101、成核层102、缓冲结构103、主动区100、第一导电型半导体层106A、106B、凹陷区R、介电层107、源极108、漏极109、栅极110以及保护层111覆盖源极108、漏极109、栅极110及部分主动区100。在本实施例中，缓冲结构103包含第一半导体叠层1031以及第二半导体叠层1032；主动区100包含通道层104以及阻障层105，靠近通道层104与阻障层105之间的界面1415处形成一二维电子气(2DEG)。图2C为图2A中透视保护层111及栅极110的上视示意图，其中第一导电型半导体层106A、106B位于凹陷区R的两侧，且不与凹陷区R相互重叠。
图3A～图3F所示本发明第二实施例的半导体单元2的制作流程图。参照图3A，首先在基板101上方以外延方式依序成长成核层102、包含第一半导体叠层1031以及第二半导体叠层1032的缓冲结构103、包含通道层104以及阻障层105的主动区100以及第一导电型半导体层106。参照图3B，通过蚀刻方式移除部分的第一导电型半导体层106，以及自主动区100，也就是阻障层105的第一上表面1051向下蚀刻形成一凹陷区R，保留位于凹陷区R两侧的第一导电型半导体层106A、106B。参照第3C～3D图，以物理气相沉积方式(Physical VaporDeposition，PVD)于阻障层105上方形成源极108以及漏极109；接着利用化学气相沉积方式(Chemical Vapor Deposition，CVD)于凹陷区R及第一导电型半导体层106A、106B上方形成介电层107。参照图3E～图3F，再次利用物理气相沉积方式于介电层107上方形成栅极110；接着以化学气相沉积方式形成保护层111以覆盖源极108、漏极109、栅极110以及阻障层105的第一上表面1051。
在本实施例中基板101可为导电基板或者绝缘基板，当基板101为导电基板时，基板101的材料可以是硅(Si)、碳化硅(SiC)、氮化镓(GaN)；当基板101为绝缘基板时，基板10的材料可以是蓝宝石(sapphire)。在本实施例中，基板101例如为硅基板，厚度约为600～1200um，当后续形成本实施例所述的半导体功率元件S时，须利用抛光研磨法或化学机械研磨法(Chemical Mechanical Polishing/Planarization，CMP)将厚度600μm～1200μm的基板101磨薄成为300μm～10μm的基板101，以符合后段制作工艺的封装尺寸，并提升封装元件的散热性能，或通过完全或部分移除基板，以减少元件的漏电路径，达到降低漏电的效果。
成核层102以外延方式成长于基板101上方，外延方式包含金属有机物化学气相外延法(metal-organic chemical vapor deposition,MOCVD)或分子束外延法(molecular-beam epitaxy，MBE)或氢化物气相外延法(hydride vapor phase epitaxy，HVPE)，成核层102的厚度约为20nm～200nm，其材料包含III-V族半导体材料，例如是氮化铝(AlN)、氮化镓(GaN)、或氮化铝镓(AlGaN)等材料。
缓冲结构103以外延方式成长于成核层102上方，其厚度约为1um～10um。缓冲结构103可以是单层、两层或多层；当缓冲结构103为多层时，可包括渐变层(grading layer)或超晶格叠层(super lattice multilayer)或两层以上不同材料的叠层。单层、两层或多层缓冲结构103的材料可包括IIIA-VA族半导体材料，例如是氮化铝(AlN)、氮化镓(GaN)、或氮化铝镓(AlGaN)、氮化铟铝(AlInN)、氮化铟铝镓(AlInGaN)等材料，并且可掺杂其他元素，例如碳，掺杂浓度可为依成长方向渐变或固定。在本实施例中，缓冲结构103包含第一半导体叠层1031以及第二半导体叠层1032，其中第一半导体叠层1031例如是氮化铝镓(AlGaN)渐变层或含碳掺杂的氮化铝镓(AlGaN)渐变层，其厚度约为0.1um～5um；第一半导体叠层1031也可例如是5nm～50nm氮化铝(AlN)与5nm～50nm氮化铝镓(AlGaN)的叠层或含碳掺杂的5nm～50nm氮化铝(AlN)与含碳掺杂的5nm～50nm nm氮化铝镓(AlGaN)的叠层；第二半导体叠层1032的厚度约为1.5μm～3μm，材料例如氮化镓(GaN)或含渐变式碳掺杂的氮化镓(GaN)。此外，若以本实施例的硅基板为例，成核层102以及缓冲结构103依序成长于基板101的(111)面上，并朝[0001]的方向成长，用以减少基板101与通道层104之间的晶格常数差异，以提升外延品质。
主动区100以外延方式依序成长于缓冲结构103上方，可以是两层或多层结构，其材料可包括III-V族半导体材料，例如是氮化铝(AlN)、氮化镓(GaN)、氮化铝镓(AlGaN)、氮化铟铝(AlInN)、氮化铝铟镓(AlInGaN)等材料。在本实施例中，主动区100包含通道层104以及阻障层105，其中通道层104具有第一带隙，阻障层105具有第二带隙大于通道层104的第一带隙，意即阻障层105的晶格常数小于通道层104的晶格常数。通道层104的厚度约为0.15μm～1μm，其材料包含InxGa(1-x)N，其中0≤x<1，例如是氮化镓(GaN)、或氮化铟镓(InGaN)；阻障层105的厚度约为10nm～30nm，其材料包含AlyInzGa(1-y-z)N，其中0<y<1以及0≤z<1，例如是氮化铝铟(AlInN)、氮化铝镓(AlGaN)或氮化铟铝镓(AlInGaN)。通道层104与阻障层105因本身的原子质心与负电荷质心间的位移而造成的自发极化，以及通道层104与阻障层105因异质材料的晶格常数不同，使其磊晶成长时产生张应力造成的压电极化，通过自发极化及压电极化会在通道层104中，且靠近通道层104与阻障层105之间的界面1415处形成一二维电子气(2DEG)。需注意的是，本实施例所述的通道层104及阻障层105皆为未掺杂的半导体材料，但依据实际应用也可为掺杂的半导体材料，掺杂物质例如是硅，其中硅的来源为硅甲烷反应前驱物，用以增加压电极化与自发极化的效果，进而提升界面1415中二维电子气(2DEG)的浓度。
请参阅图3B，本实施例通过蚀刻方式自阻障层105的第一上表面1051向下蚀刻形成凹陷区R，蚀刻方式例如是干式蚀刻(dry etching)或湿式蚀刻(wet etching)。其中，自阻障层105的第一上表面1051至凹陷区R的底部B具有一深度D，且深度D约大于5nm～25nm。若阻障层105的材料例如是氮化铝镓(AlGaN)，铝含量例如是20％，厚度例如是26nm，其深度D大于21nm，意即凹陷区R下方残留的阻障层105的厚度T小于5nm。因此，由于凹陷区R下方的阻障层105厚度T过薄，不足与通道层104产生极化效应，故导致凹陷区R下方无法产生二维电子气(2DEG)，致使半导体单元2达成常关型晶体管的元件特性。需注意的是，在其他实施例中，凹陷区R的形成可经由蚀刻阻障层105至其与通道层104的介面1415(即凹陷区R的底部B为阻障层105与通道层104的介面1415)；或是继续蚀刻穿过阻障层105与通道层104间的介面1415，使得部分通道层104被蚀刻移除形成凹陷区R，以阻断二维电子气(2DEG)的通道，导致凹陷区R下方无法产生二维电子气(2DEG)，致使半导体单元2达成常关型晶体管的元件特性。
第一导电型半导体层106A、106B形成于主动区100上方，具体而言，第一导电型半导体层106A、106B形成于阻障层105上方，其厚度约为30nm～150nm，材料可包括InxGa(1-x)N，其中0≤x<1，或AlyInzGa(1-y-z)N，其中0<y<1以及0≤z<1，例如是氮化铝(AlN)、氮化镓(GaN)、氮化铝镓(AlGaN)、或氮化铟铝镓(AlInGaN)等材料，并且掺杂其他元素，例如镁，掺杂浓度可为依成长方向渐变或固定。请参阅图2C及图3F，本实施例第一导电型半导体层106A、106B可为p型导电型半导体层，载流子浓度大于1E16cm-3，小于1E18cm-3；第一导电型半导体层106A、106B位于凹陷区R的两侧，不与凹陷区R相互重叠，意即第一导电型半导体层106A、106B并非设置于凹陷区R中。具体而言，凹陷区R具有第一侧壁RW1，第一导电型半导体层106A具有第一侧边1061A与凹陷区R的第一侧壁RW1大致对齐；凹陷区R具有第二侧壁RW2，第一导电型半导体层106B具有第二侧边1061B与凹陷区R的第二侧壁RW2大致对齐。
介电层107以化学气相沉积方式形成于主动区100上方，具体而言，介电层107形成于第一导电型半导体层106A、106B上方，且覆盖凹陷区R。化学气相沉积方式可例如为等离子体辅助化学气相沉积法(plasma enhanced chemical vapour deposition，PECVD)、低压化学气相沉积(low-pressure chemical vapour deposition，LPCVD)、原子层沉积(AtomicLayer Deposition，ALD)或金属有机物化学气相沉积法(metal organic chemical-vapordeposition，MOCVD)等。介电层107的材料可为绝缘材料，包含氮化物绝缘材料或氧化物绝缘材料，例如是氮化硅(SiNx)、二氧化硅(SiO2)、氧化铝(Al2O3)、或氮氧化硅(SiONx)。请参阅图3D，介电层107覆盖凹陷区R的底部B、第一侧壁RW1、第二侧壁RW2、第一导电型半导体层106A的上表面1062A及第一侧边1061A以及第一导电型半导体层106B的上表面1062B及第二侧边1061B。在本实施例中，通过第一导电型半导体层106A、106B及介电层107的设置，可改善半导体功率元件S表面的漏电流问题；解决栅极110下方的电场过于集中在凹陷区R的边缘，使栅极110下方的峰值电场通过第一导电型半导体层106A、106B得以降低并分布均匀，避免元件烧毁及提高半导体功率元件S的击穿电压；当半导体功率元件S作动时，防止栅极110控制失效；提升栅极110的操作电压及元件的电流，进而增加半导体功率元件S的输出功率，优化半导体功率元件S的应用面。
源极108、漏极109位于主动区100上方，具体而言，源极108、漏极109位于阻障层105上方，其材料包含钛、铝、金、镍、铂金或钼等，其中还包含上述两种或两种以上的材料所形成的金属叠层。各电极的形成材料可进行后续制作工艺，如施以升温条件下，部分金属叠层可视其共融温度形成合金，并与阻障层105形成欧姆接触；栅极110形成于源极108与漏极109之间，其形成材料包含镍、金、钨、钼、氮化钛、钛化钨、铂金、钛或铝等，其中还包含上述两种或两种以上的材料所形成的叠层，且位于介电层107之上，以作为半导体功率元件S开启及关闭的控制电极。在本实施例中，栅极110部分设置于凹陷区R中，使介电层107同时位于阻障层105与栅极110之间以及第一导电型半导体层106A、106B与栅极110之间，且栅极110可例如是矩形或T型。此外，本实施例所述的栅极110位于远离漏极109且较接近源极108的位置，以利于提高半导体功率元件S的击穿电压，且源极108、漏极109以及栅极110用以作为与外部电连接的端点，并可根据实际需求来控制半导体单元2的操作状态以及二维电子气(2DEG)的分布情况。
保护层111以化学气相沉积方式覆盖半导体单元2的表面，其中化学气相沉积方式可例如为等离子体辅助化学气相沉积法(plasma enhanced chemical vapourdeposition，PECVD)或低压化学气相沉积(low-pressure chemical vapour deposition，LPCVD)或原子层沉积(Atomic Layer Deposition，ALD)或金属有机物化学气相沉积法(metal organic chemical-vapor deposition，MOCVD)等。保护层111的材料可为绝缘材料，包含氮化物绝缘材料或氧化物绝缘材料，例如是氮化硅(SiNx)、二氧化硅(SiO2)、氧化铝(Al2O3)、或氮氧化硅(SiONx)。请参阅图3F，本实施例的保护层111覆盖阻障层105、源极108、漏极109、及栅极110的表面，以改善半导体功率元件S表面的漏电问题；防止水气渗入阻障层105与通道层104，造成元件劣化；避免电极间产生电弧现象，导致电极烧毁。在另一实施例中，也可于半导体单元的表面及部分侧壁覆盖一保护层(未显示)，以避免后续封装对元件的电性造成不良影响。
需注意的是，本实施例的半导体单元2更可包括覆盖层(未显示)形成于主动区100上方，具体而言，覆盖层形成于阻障层105上方，覆盖层具有带隙小于阻障层105的第二带隙，意即覆盖层的晶格常数为大于阻障层105的晶格常数。覆盖层的材料可包括InxGa(1-x)N，其中0≤x<1，例如是氮化镓(GaN)，其可为未掺杂的半导体材料，或为掺杂的半导体材料，掺杂物质例如是硅，其中硅的来源为硅甲烷反应前驱物。此外，覆盖层具有保护层作用以防止阻障层105表面因后续制作工艺受到损害。然而，一般可依实际需求决定将覆盖层省略或设置。
图4显示本发明第二实施例的半导体单元2的开启状态示意图。本实施例的半导体单元2是常关型晶体管，当给予漏极109一正偏压(如+10V)，源极108接地(0V)，给予栅极110一正偏压(如+5V)，半导体单元2因费米能阶位移而开启。此时使栅极110下方的导带(Ec)降至费米能阶(Ef)之下，因而栅极110下方产生二维电子气(2DEG)，半导体单元2呈现开启状态。
请参阅图5A至图5C所示本发明第三实施例的半导体单元3。在本实施例中，半导体单元3可以用于取代图1的半导体单元1以形成半导体功率元件S。其中，图5A为半导体单元3的上视示意图，图5B为半导体单元3透视保护层及栅极的示意图；图5C为图5A沿剖线HH的剖面示意图。本实施例的半导体单元3与图3A～图3F所述的实施例具有相似的结构，除了本实施例仅于栅极310与漏极309之间设置第一导电型半导体层306，且第一导电型半导体层306不与凹陷区R相互重叠，意即第一导电型半导体层306并非设置于凹陷区R中，以解决栅极310与漏极309之间主要的电场集中问题。请参阅图5C，本实施例第一导电型半导体层306可为p型半导体层，载流子浓度大于1E16cm-3，小于1E18cm-3，凹陷区R具有第一侧壁RW1，第一导电型半导体层306具有第一侧边3061与凹陷区R的第一侧壁RW1大致对齐；介电层307形成于阻障层305上方，覆盖凹陷区R的底部B、第一侧壁RW1、第二侧壁RW2，以及第一导电型半导体层306的第一侧边3061及其上表面3062以及部分阻障层305的第一上表面3051；栅极310部分设置于凹陷区R中及部分设置于凹陷区R外，介电层307同时位于阻障层305与栅极310之间以及第一导电型半导体层306与栅极310之间，且栅极310可例如是矩形或T型。在本实施例中，栅极310与漏极309之间为主要的电场分布区域，故通过第一导电型半导体层306及介电层307的设置，可改善半导体功率元件S表面的漏电流问题；改善栅极310与漏极309下方的电场过于集中于凹陷区R的边缘，分散栅极310下方的电场分布，避免半导体功率元件S烧毁及提高半导体功率元件S的击穿电压；当半导体功率元件S作动时，防止栅极310控制失效；提升栅极310的操作电压及半导体功率元件S的电流，进而增加半导体功率元件S的输出功率，优化半导体功率元件S的应用面。
请参阅图6所示本发明第四实施例的半导体单元5。在本实施例中，半导体单元5可以用于取代图1的半导体单元1以形成半导体功率元件S。其中，本实施例的半导体单元5与图5A～图5C所述的实施例具有相似的结构，差异在本实施例增加了介电层507与栅极510的场板设计，使栅极510与漏极509之间的电场分布更加均匀化。本实施例的介电层507包覆第一导电型半导体层506的第一侧边5061、第二上表面5062以及第二侧边5063，并沿着第一导电型半导体层506的第二侧边5063延伸至阻障层505的第一上表面5051，且栅极510完全覆盖于介电层507上方。其中，凹陷区R的第一侧壁RW1至漏极509的一侧边5091具有第一长度L1，凹陷区R的第一侧壁RW1至栅极510的一侧边5101具有第二长度L2，且L2＜1/2L1，以防止栅极510与漏极509之间产生严重的电弧现象，导致电极烧毁。
需了解的是，本发明中上述的实施例在适当的情况下，是可互相组合或替换，而非仅限于所描述的特定实施例。本发明所列举的各实施例仅用以说明本发明，并非用以限制本发明的范围。任何人对本发明所作的任何显而易见的修饰或变更接不脱离本发明的精神与范围。

Claims (10)

1.一种半导体功率元件，包含：
基板；
主动区，位于该基板上方，包含：
通道层；
阻障层，包含上表面，相对于该通道层；及
二维电子气，形成于靠近该通道层与该阻障层之间的界面处；
凹陷区，形成于该阻障层中；
第一导电型半导体层，位于该上表面上方，不与该凹陷区相互重叠；
漏极，位于该主动区上方；
栅极，位于该主动区上方，其中，该栅极的一部分设置于该凹陷区中，该栅极的另一部分覆盖该第一导电型半导体层并延伸至该漏极与该第一导电型半导体层之间；以及
介电层，位于该主动区与该栅极之间。
2.如权利要求1所述的半导体功率元件，该第一导电型半导体层是一p型导电型半导体层，具有一载流子浓度大于1E16cm-3，且小于1E18cm-3。
3.如权利要求1所述的半导体功率元件，其中，该凹陷区自该上表面延伸进该阻障层。
4.如权利要求1所述的半导体功率元件，其中该介电层位于该第一导电型半导体层以及该栅极之间，且设置于该凹陷区中。
5.如权利要求1所述的半导体功率元件，其中该凹陷区具有一底部，该介电层直接接触该底部。
6.如权利要求1所述的半导体功率元件，其中该栅极具有一侧边位于该第一导电型半导体层与该漏极之间，该凹陷区至该漏极之间的一第一距离的一半大于该侧边至该凹陷区之间的一第二距离。
7.如权利要求1所述的半导体功率元件，其中，该介电层同时包覆该凹陷区以及该第一导电型半导体层，并延伸至该阻障层的该上表面。
8.如权利要求1所述的半导体功率元件，还包括源极，位于该主动区上方，其中该第一导电型半导体层位于该源极以及该漏极之间。
9.如权利要求8所述的半导体功率元件，其中该第一导电型半导体层具有多个，且该多个第一导电型半导体层分别位于该凹陷区以及该漏极之间以及该凹陷区以及该源极之间。
10.如权利要求1所述的半导体功率元件，其中第一导电型半导体层的材料包括InxGa(1-x)N，其中0≤x<1；或AlyInzGa(1-y-z)N，其中0<y<1以及0≤z<1。
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