CN109889196B - Small-area low-power-consumption clock data recovery circuit - Google Patents
Small-area low-power-consumption clock data recovery circuit Download PDFInfo
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- CN109889196B CN109889196B CN201910102503.2A CN201910102503A CN109889196B CN 109889196 B CN109889196 B CN 109889196B CN 201910102503 A CN201910102503 A CN 201910102503A CN 109889196 B CN109889196 B CN 109889196B
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Abstract
The invention discloses a small-area low-power-consumption clock data recovery circuitThe circuit comprises a frequency discrimination phase discriminator, a frequency divider, a first charge pump, a second charge pump, a Bang-Bang phase discriminator, a loop filter, a voltage-controlled oscillator and a seventh switch, wherein the input end of the frequency discrimination phase discriminator is connected with an input signal and is connected with the first output end of the voltage-controlled oscillator through the frequency divider; the input end of the voltage-controlled oscillator is connected with the loop filter, the second and third and fourth output ends are connected with the first to fourth input ends of the Bang-Bang phase discriminator, the fifth input end of the Bang-Bang phase discriminator is connected with a positive and negative differential input signal, the first to fourth output ends of the Bang-Bang phase discriminator are used as the output end of the whole circuit, and the fifth output end of the Bang-Bang phase discriminator is connected with the second charge pump; the second charge pump is connected with the power supply through the seventh switch, and the output end of the second charge pump is connected with the second input end of the loop filterAre connected with each other(ii) a The first charge pump is connected with the phase frequency detector, and the output end of the first charge pump is connected with the first input end of the loop filter. The dual-ring alternative working power consumption is lower, the area is reduced, and the establishment speed and the noise performance are considered.
Description
Technical Field
The invention relates to a small-area low-power-consumption clock data recovery circuit, and belongs to the technical field of clock data recovery circuits.
Background
Clock Data Recovery (CDR) is a core module of a high-speed communication interface, and is used to recover high-quality Clock information, and resample a Data signal, which is distorted and superimposed with noise during transmission, with the recovered Clock signal to recover high-quality Data.
Existing CDR design techniques typically employ a double loop structure: the clock Frequency is recovered by using a Frequency-Locked Loop (FLL), and the clock edge is aligned to the data center, i.e. the optimal sampling point, by using a Phase-Locked Loop (PLL), and then the data is resampled. In order to keep the results of the FLL and apply them in the PLL, the dual rings need to be turned on simultaneously. To reduce power consumption, the FLL and PLL can be operated alternately, but the retention of the FLL lock result requires additional loop filter capacitance to achieve. The loop filter capacitor occupies a large area in the whole chip, and taking the CDR of the ring oscillator as an example, the area of the loop filter capacitor occupies about 50% of the total area of the CDR.
The dual loop multiplexing loop filtering technique can alleviate the contradiction between the power consumption and the area, but FLL and PLL have different missions and characteristics: FLLs are generally required to lock quickly with minimal resources, while PLLs are required to have high noise rejection levels and stability. The parameters of the FLL and other blocks of the PLL loop also differ significantly. The simple multiplexing loop filter loses the flexibility of the double loop, loop parameters cannot be reasonably set, and optimization of CDR performance is limited.
Disclosure of Invention
The invention aims to solve the technical problems that the flexibility is lost, loop parameters cannot be reasonably set and the optimization of CDR performance is limited due to the adoption of double loops in the conventional data recovery circuit, and provides a small-area low-power-consumption clock data recovery circuit. Through dicyclo alternate operation and adopt novel electric capacity multiplex type loop filter, both can practice thrift chip area, can not lose the advantage of dicyclo parameter flexibility in CDR performance optimization again.
The invention specifically adopts the following technical scheme to solve the technical problems:
a small-area low-power-consumption clock data recovery circuit comprises a frequency discrimination phase discriminator, a frequency divider, a first charge pump, a second charge pump, a Bang-Bang phase discriminator, a loop filter, a voltage-controlled oscillator and a seventh switch, wherein a first input end of the frequency discrimination phase discriminator is connected with an input signal Fref, a second input end of the frequency discrimination phase discriminator is connected with an output end of the frequency divider, and an input end of the frequency divider is connected with a first output end of the voltage-controlled oscillator; the input end of the voltage-controlled oscillator is connected with the output end of the loop filter, the second, third, fourth and fifth output ends of the voltage-controlled oscillator are respectively connected with the first, second, third and fourth input ends of the Bang-Bang phase discriminator, the fifth and sixth input ends of the Bang-Bang phase discriminator are respectively connected with positive and negative differential input signals, the first, second, third and fourth output ends of the Bang-Bang phase discriminator are used as the output end of the whole circuit to output restored data, and the fifth output end of the Bang-Bang phase discriminator is connected with the input end of the second charge pump; the second charge pump is connected to the power supply through a seventh switch, and the output end of the second charge pump is connected with the second input end of the loop filter; the input end of the first charge pump is connected with the output end of the phase frequency detector, and the output end of the first charge pump is connected to the first input end of the loop filter.
Further, as a preferred technical solution of the present invention, the loop filter includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a first resistor, a second resistor, a third resistor, a first capacitor, a second capacitor, a third capacitor, a fourth capacitor, and a first operational amplifier; a first end of the first switch is used as a first input end of the loop filter and connected with an input signal inf, and a second end of the first switch is respectively connected with a first end of the second switch and a first end of the first resistor; the second end of the second switch is respectively connected with the positive input end of the first operational amplifier and the first end of the second capacitor, and the second end of the second capacitor is grounded; the negative input end of the first operational amplifier is connected to the output end of the first operational amplifier, and the output end of the first operational amplifier is respectively connected with the first end of the third switch, the first end of the fourth switch and the first end of the fifth switch; a second end of the third switch, a first end of the third resistor, a first end of the third capacitor and a first end of the second resistor are connected together and then are used as a second input end of the loop filter to be connected with the input signal inp; the second end of the third capacitor is grounded; the second end of the first resistor and the second end of the second resistor are respectively connected with the first end of the first capacitor, and the second end of the first capacitor is grounded; the second end of the third resistor, the second end of the fourth switch and the first end of the sixth switch are respectively connected with the first end of the fourth capacitor, and the second end of the fourth capacitor is grounded; and the second end of the fifth switch is connected with the second end of the sixth switch and then used as the output end of the loop filter to obtain an output signal out.
Further, as a preferable technical solution of the present invention, the first switch, the second switch, the third switch, the fourth switch and the fifth switch are controlled by a first control signal Φ 1 Control, the sixth switch and the seventh switch are controlled by a second control signal
Control and the first control signal phi 1 And a second control signal
Is a pair of opposing control signals.
Further, as a preferred technical solution of the present invention, the first control signal Φ 1 The control circuit works in an FLL state, and specifically comprises the following steps:
first control signal phi 1 Controlling a first switch, a second switch, a third switch, a fourth switch and a fifth switch S 5 The sixth switch and the seventh switch are turned off; a second-order filter circuit is formed by a first resistor, a first capacitor and a second capacitor; and copying the output potential of the second-order filter circuit by using the first operational amplifier, pre-charging the third capacitor and the fourth capacitor, and obtaining an output signal out through a fifth switch.
Further, as a preferred technical solution of the present invention, the second control signal
The control circuit works in a PLL state, and specifically comprises the following steps:
the first control signal phi 1 Switch to the second control signal
The first switch, the second switch, the third switch, the fourth switch and the fifth switch are turned off by the second control signal
Control the sixth switch and the seventh switch S 7 And when the second resistor, the first capacitor, the third resistor and the fourth capacitor are conducted, a third-order filter circuit is formed, and an output signal out is obtained through a sixth switch.
By adopting the technical scheme, the invention can produce the following technical effects:
the small-area low-power-consumption clock data recovery circuit is based on a double-ring structure, double rings work alternately and multiplex the clock data recovery circuit, and the occupied area is largeFirst capacitor C 1 And the power consumption is reduced, and the chip area is greatly reduced. In addition, a second-order filter is adopted in the frequency pull-in loop FLL and the loop bandwidth is relatively large, so that the loop locking speed is fast. In the phase alignment and data recovery process, namely a third-order filter takes effect in the PLL, the loop bandwidth is relatively small, and the noise performance is improved. In the clock data recovery process, it is the noise characteristics of the PLL that affect the quality of the signal that is ultimately recovered. Therefore, the small-area low-power-consumption clock data recovery circuit disclosed by the invention can reduce the area and simultaneously give consideration to the establishment speed and the noise performance.
Drawings
Fig. 1 is a schematic diagram of a small-area low-power consumption clock data recovery circuit according to the present invention.
Fig. 2 is a schematic diagram of the loop filter of the present invention operating in the FLL state.
Fig. 3 is a schematic diagram of the loop filter of the present invention operating in a PLL state.
Fig. 4 is a simulation result of the clock data recovery circuit setup process in the present invention.
Detailed Description
The following describes embodiments of the present invention with reference to the drawings.
As shown in fig. 1, the present invention provides a small-area low-power consumption clock data recovery circuit, which comprises a phase frequency detector, a frequency divider, a first charge pump, a second charge pump, a Bang-Bang phase detector, a loop filter, a voltage controlled oscillator, and a seventh switch S 7 . The first input end of the phase frequency detector is connected with an input signal Fref, the second input end of the phase frequency detector is connected with the output end of the frequency divider, and the input end of the frequency divider is connected with the first output end of the voltage-controlled oscillator; the input end of the voltage-controlled oscillator is connected with the output end of the loop filter, the second, third, fourth and fifth output ends of the voltage-controlled oscillator are respectively connected with the first, second, third and fourth input ends of the Bang-Bang phase detector to be connected with the Clk 0, clk 90, clk 180 and Clk270 signals, and the fifth and sixth input ends of the Bang-Bang phase detector are respectively connected with the positive and negative differential input signals Data +, dat and Data-, and the first, second, third and fourth output ends of the Bang-Bang phase detector are used as the output end of the whole circuit to output the restored data, and the fifth output end of the Bang-Bang phase detector is connected with the input end of the second charge pump; the second charge pump is connected to the power supply through a seventh switch S7, and the output end of the second charge pump is connected to the second input end of the loop filter; the input end of the first charge pump is connected with the output end of the phase frequency detector, and the output end of the first charge pump is connected to the first input end of the loop filter.
In the present invention, the structure of the loop filter is shown in fig. 1, which mainly includes a first switch S 1 A second switch S 2 And a third switch S 3 And a fourth switch S 4 The fifth switch S 5 And a sixth switch S 6 A first resistor R 1F A second resistor R 1P A third resistor R 2 A first capacitor C 1 A second capacitor C 2F A third capacitor C 2P A fourth capacitor C 3 A first operational amplifier A 1 (ii) a Wherein the first switch S 1 As a first input of the loop filter, with an input signal inf, a first switch S 1 Respectively with a second switch S 2 First terminal, first resistor R 1F Are connected with each other; the second switch S 2 Respectively with the first operational amplifier A 1 Positive input terminal of the first capacitor C 2F Are connected to each other, and a second capacitor C 2F The second terminal of (1) is grounded; the first operational amplifier A 1 Is connected to the first operational amplifier A 1 And a first operational amplifier A 1 Respectively with the third switch S 3 First terminal, fourth switch S 4 First terminal, fifth switch S 5 Are connected with each other; the third switch S 3 Second terminal, third resistor R 2 First terminal of (2), third capacitance C 2P First terminal and second resistor R 1P After being connected together, the first ends of the first and second loop filters are used as a second input end of the loop filter to be connected with an input signal inp; the third capacitor C 2P The second terminal of (1) is grounded; the first isResistance R 1F Second terminal, second resistor R 1P Respectively with the first capacitor C 1 Are connected to each other, and a first capacitor C 1 The second terminal of (1) is grounded; the third resistor R 2 Second terminal, fourth switch S 4 Second terminal of (2), sixth switch S 6 Respectively with a fourth capacitor C 3 Are connected to each other, and a fourth capacitor C 3 The second terminal of (1) is grounded; the fifth switch S 5 Second terminal and sixth switch S 6 And the second end of the second loop filter is connected to be used as the output end of the loop filter to obtain an output signal out.
The small-area low-power consumption clock data recovery circuit comprises an FLL loop and a PLL loop, wherein the FLL loop and the PLL loop work alternately; when the first control signal phi 1 Controlled first switch S 1 A second switch S 2 And a third switch S 3 And a fourth switch S 4 And a fifth switch S 5 When turned on, the sixth switch S 6 And a seventh switch S 7 The circuit is disconnected, and the circuit works in an FLL state; when the second control signal is applied
Controlled sixth switch S 6 And a seventh switch S 7 When turned off and on, the first switch S 1 A second switch S 2 And a third switch S 3 And a fourth switch S 4 And a fifth switch S 5 And the circuit is disconnected and works in a PLL state. The first control signal phi 1 And a second control signal
Is a pair of opposing control signals.
Fig. 2 is a schematic diagram illustrating the loop filter of the present invention operating in the FLL state. At this time, the first control signal phi 1 Control the first switch S 1 A second switch S 2 And a third switch S 3 And a fourth switch S 4 And a fifth switch S 5 Is turned on at this time 6 And a seventh switch S 7 And (5) disconnecting. A first resistor R 1F A first capacitor C 1 A second capacitor C 2F Forming a second order filter circuit. By operating a first operational amplifier A 1 Copying the output potential of the second-order filter circuit to the third capacitor C 2P And a fourth capacitance C 3 Is pre-charged and passes through a fifth switch S 5 Resulting in an output signal out. In addition, in the FLL state, the power supply of the second charge pump is cut off, and the potential of the output end of the second charge pump also follows the output of the second-order filter circuit, so that the influence of charge sharing on stability during circuit state switching is prevented. The pre-charge, follow, and final output are all at the first operational amplifier A 1 This is then to eliminate the first operational amplifier a 1 Causes disturbances when the circuit state switches.
Fig. 3 is a schematic diagram illustrating the loop filter of the present invention operating in the PLL state. First control signal phi 1 And a second control signal
The pair of opposite control signals is switched rapidly so that the first switch S is switched 1 A second switch S 2 And a third switch S 3 And a fourth switch S 4 And a fifth switch S 5 Off, second control signal
Control the sixth switch S 6 And a seventh switch S 7 And conducting. At the instant after switching, the first capacitor C 1 A third capacitor C 2P A fourth capacitor C 3 The upper plate potential and the potential of the node inp maintain the output result after FLL is stabilized. After entering the PLL state, the second resistor R 1P A first capacitor C 1 A third capacitor C 2P A third resistor R 2 And a fourth capacitance C 3 Form a third order filter circuit, and through a sixth switch S 6 Resulting in an output signal out.
In the design of loop filter, the first capacitor C 1 The capacity value of (a) is the largest, and the occupied area is also the largest, about 90%. The invention shares the first capacitor C 1 Is greatly reducedThe chip area is reduced. In addition, a second-order filter is adopted in the FLL, the loop bandwidth is relatively large, and although the noise performance is poor, the loop locking speed is high. And the effective filter of the third order in the PLL, the loop bandwidth is relatively smaller, and the noise performance is improved.
As shown in fig. 4, a simulation result of a setup process of a small-area low-power-consumption clock data recovery circuit is disclosed in the present invention. In the stage (1), the clock data recovery circuit works in an FLL state, and a loop is locked quickly; after 10 mus the circuit switches to the PLL state, i.e. enters phase (2), the circuit locks after undergoing a small perturbation to correct the phase. To fully verify the circuit, the FLL has a lock-in frequency that is 10MHz different from the code rate of the input data, so the final stable voltage is different for stage (1) and stage (2).
In summary, the small-area low-power-consumption clock data recovery circuit of the present invention affects the finally recovered signal quality in the clock data recovery process by the noise characteristics of the PLL. In addition, the double rings work alternately, and the power consumption is low. Therefore, the small-area low-power-consumption clock data recovery circuit disclosed by the invention can reduce the area and simultaneously give consideration to the establishment speed and the noise performance.
The embodiments of the present invention have been described in detail with reference to the drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the gist of the present invention.
Claims (4)
1. A small-area low-power consumption clock data recovery circuit is characterized in that: comprises a frequency and phase discriminator, a frequency divider, a first charge pump, a second charge pump, a Bang-Bang phase discriminator, a loop filter, a voltage-controlled oscillator and a seventh switch (S) 7 ) The first input end of the phase frequency detector is connected with an input signal Fref, the second input end of the phase frequency detector is connected with the output end of the frequency divider, and the input end of the frequency divider is connected with the first output end of the voltage-controlled oscillator; the input end of the voltage-controlled oscillator is connected with the output end of the loop filter, and the second, third, fourth and fifth input ends of the voltage-controlled oscillatorThe output end of the Bang-Bang phase discriminator is respectively connected with the first, second, third and fourth input ends of the Bang-Bang phase discriminator, the fifth and sixth input ends of the Bang-Bang phase discriminator are respectively connected with positive and negative differential input signals, the first, second, third and fourth output ends of the Bang-Bang phase discriminator are used as the output end of the whole circuit to output restored data, and the fifth output end of the Bang-Bang phase discriminator is connected with the input end of the second charge pump; the second charge pump is connected to the power supply through a seventh switch (S7), and the output end of the second charge pump is connected with the second input end of the loop filter; the input end of the first charge pump is connected with the output end of the phase frequency detector, and the output end of the first charge pump is connected with the first input end of the loop filter;
wherein the loop filter comprises a first switch (S) 1 ) A second switch (S) 2 ) And a third switch (S) 3 ) A fourth switch (S) 4 ) And a fifth switch (S) 5 ) And a sixth switch (S) 6 ) A first resistor (R) 1F ) A second resistor (R) 1P ) A third resistor (R) 2 ) A first capacitor (C) 1 ) A second capacitor (C) 2F ) A third capacitor (C) 2P ) A fourth capacitor (C) 3 ) A first operational amplifier (A) 1 ) (ii) a The first switch (S) 1 ) As a first input of the loop filter, with an input signal inf, a first switch (S) 1 ) Respectively with a second switch (S) 2 ) First terminal, first resistor (R) 1F ) Are connected with each other; the second switch (S) 2 ) Respectively with the first operational amplifier (A) 1 ) Positive input terminal of, a second capacitor (C) 2F ) Are connected to each other, and a second capacitor (C) 2F ) The second terminal of (1) is grounded; the first operational amplifier (A) 1 ) Is connected to the first operational amplifier (A) 1 ) And a first operational amplifier (A) 1 ) Respectively with the third switch (S) 3 ) First terminal, fourth switch (S) 4 ) First terminal, fifth switch (S) 5 ) Are connected with each other; the third switch (S) 3 ) Second terminal, third resistor (R) 2 ) First terminal, third capacitor (C) 2P ) First end ofAnd a second resistor (R) 1P ) After being connected together, the first ends of the first and second loop filters are used as a second input end of the loop filter to be connected with an input signal inp; the third capacitance (C) 2P ) The second terminal of (1) is grounded; the first resistor (R) 1F ) Second terminal, second resistor (R) 1P ) Respectively with the first capacitor (C) 1 ) Are connected to each other, and a first capacitor (C) 1 ) The second terminal of (1) is grounded; the third resistor (R) 2 ) Second terminal, fourth switch (S) 4 ) Second terminal, sixth switch (S) 6 ) Respectively with a fourth capacitor (C) 3 ) Are connected to each other, and a fourth capacitance (C) 3 ) The second terminal of (1) is grounded; the fifth switch (S) 5 ) And the second terminal of (S) and a sixth switch (S) 6 ) And the second end of the second loop filter is connected to be used as the output end of the loop filter to obtain an output signal out.
2. The small-area low-power clock-data recovery circuit of claim 1, wherein: the first switch (S) 1 ) A second switch (S) 2 ) And a third switch (S) 3 ) And a fourth switch (S) 4 ) And a fifth switch (S) 5 ) By a first control signal phi 1 Control, the sixth switch (S) 6 ) And a seventh switch (S) 7 ) By a second control signal
Control and the first control signal phi 1 And a second control signal
Is a pair of opposing control signals.
3. The small-area low-power clock-data recovery circuit of claim 2, wherein: the first control signal phi 1 The control circuit works in an FLL state, and specifically comprises the following steps:
first control signal phi 1 Controlling the first switch (S) 1 ) A second switch (S) 2 ) And a third switch (S) 3 ) The fourth partClosing (S) 4 ) And a fifth switch (S) 5 ) On, the sixth switch (S) 6 ) And a seventh switch (S) 7 ) Disconnecting; is composed of a first resistor (R) 1F ) A first capacitor (C) 1 ) A second capacitor (C) 2F ) Forming a second-order filter circuit; using a first operational amplifier (A) 1 ) Copying the output potential of the second-order filter circuit and applying it to a third capacitor (C) 2P ) And a fourth capacitance (C) 3 ) Pre-charged and passed through a fifth switch (S) 5 ) Resulting in an output signal out.
4. The small-area low-power clock-data recovery circuit of claim 2, wherein: the second control signal
The control circuit works in a PLL state, and specifically comprises the following steps:
the first control signal phi 1 Switching to the second control signal
The first switch (S1), the second switch (S2), the third switch (S3), the fourth switch (S4) and the fifth switch (S5) are turned off by a second control signal
Control the sixth switch (S) 6 ) And a seventh switch (S) 7 ) On, the second resistor (R) 1P ) A first capacitor (C) 1 ) A third capacitor (C) 2P ) A third resistor (R) 2 ) And a fourth capacitance (C) 3 ) Form a third-order filter circuit, and via a sixth switch (S) 6 ) Resulting in an output signal out.
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| CN105703767B (en) * | 2016-01-13 | 2018-10-12 | 中国科学技术大学先进技术研究院 | A kind of single loop clock data recovery circuit of high energy efficiency low jitter |
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