CN109884504A - A kind of quantum chip capacity detection method - Google Patents
A kind of quantum chip capacity detection method Download PDFInfo
- Publication number
- CN109884504A CN109884504A CN201910195191.4A CN201910195191A CN109884504A CN 109884504 A CN109884504 A CN 109884504A CN 201910195191 A CN201910195191 A CN 201910195191A CN 109884504 A CN109884504 A CN 109884504A
- Authority
- CN
- China
- Prior art keywords
- conductor wire
- quantum chip
- pole plate
- substrate
- wire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
The invention discloses a kind of quantum chip capacity detection methods, including providing substrate, quantum chip, bonding machine, metal wire and capacitance detecting device, on the surface of the substrate, area is placed in setting, and the first conductor wire and the second conductor wire is respectively set at the two edges for placing area；The quantum chip is fixed in the placement area of the substrate；The positive terminal of capacitance detecting device and negative terminal between first pole plate and first conductor wire of the quantum chip and between second pole plate and second conductor wire of the quantum chip, are separately connected by the port of first conductor wire on substrate and the port of second conductor wire using bonding machine by two metal lines difference bonding；The power supply of capacitance detecting device is connected, the capacitor of quantum chip is detected, using detection method, it enables to quantum chip capacity in test, and it is more stable with the connection of test device, improve testing efficiency.
Description
Technical field
The invention belongs to capacitance detecting field, especially a kind of quantum chip capacity detection method.
Background technique
Quantum chip is the basic Component units of quantum computer, is using the synergistic effect of quantum state as principle, with quantum
Bit is the processor of the carrier of information processing, and quantum chip mainly includes Superconducting Quantum chip, semiconductor quantum chip, quantum
Point chip, ion trap and NV (diamond) colour center etc..
Quantum chip needs to test its actual capacitance when leaving the factory, according to the design capacitance of actual capacitance and quantum chip it
Between error size judge whether quantum chip qualified.Currently, conventional way is two pole plates directly in quantum chip
Upper welding copper wire simultaneously connects capacitance bridge and is tested, but due to the small volume of quantum chip, directlys adopt copper wire welding
The mode of pole plate, welding difficulty is big, and it is bad to weld latter linked stability, and is easy to break, so that quantum chip capacity detects
Inefficiency.
Summary of the invention
The object of the present invention is to provide a kind of quantum chip capacity detection methods, to solve deficiency in the prior art, it
It enables to quantum chip capacity in test, more stable, raising testing efficiency is connect with test device.
The technical solution adopted by the invention is as follows:
A kind of quantum chip capacity detection method, comprising the following steps:
Substrate, quantum chip, bonding machine, metal wire and capacitance detecting device are provided, are arranged on the surface of the substrate
Area is placed, the first conductor wire and the second conductor wire is respectively set at the two edges for placing area, in which: the quantum chip
Including the first pole plate and the second pole plate being oppositely arranged；
The quantum chip is fixed in the placement area of the substrate；
Using bonding machine between first pole plate and first conductor wire piece metal wire of bonding,
So that first pole plate and first conductor wire conducting, between second pole plate and second conductor wire
Piece metal wire of bonding, so that second pole plate and second conductor wire conducting；
Described first that the positive terminal of the capacitance detecting device and negative terminal are separately connected on substrate is led
Electric wire and second conductor wire；
The power supply of capacitance detecting device is connected, the capacitor of quantum chip is detected.
It is further:
The metal wire uses metallic aluminium silk thread.
It is further:
25 μm of the diameter of the metallic aluminium silk thread, length 3mm.
It is further:
The capacitance detecting device is transformer ratio arm capacitance bridge.
It is further:
Area is placed in the setting on the surface of the substrate, and the first conduction is respectively set at the two edges for placing area
Line and the second conductor wire, specifically include:
The first conductor wire and the second conductor wire are respectively set at two opposite edges for placing area, described first is conductive
Line and second parallel conductive line setting；
Or the first conductor wire and the second conductor wire are respectively set at two neighboring edges in the security protection area, described first leads
Electric wire and second conductor wire are arranged in a crossed manner.
It is further:
By in the fixed placement area on the substrate of the quantum chip, specifically include:
The quantum chip is fixed on to the placement area of the substrate surface by way of stickup.
It is further:
It is described to use bonding machine piece gold of bonding between first pole plate and first conductor wire
Belonging to line is connected first pole plate and first conductor wire, between second pole plate and second conductor wire
Piece metal wire of bonding, so that second pole plate and second conductor wire conducting, specifically include:
Each metal wire is arranged to be respectively positioned on the extended line of first pole plate and the second pole plate line.
The utility model has the advantages that
Compared with prior art, the present invention is led by the way that two conductor wires, i.e. the first conductor wire and second are arranged on substrate
Electric wire, using bonding machine between first pole plate and first conductor wire piece metal wire of bonding, make
Obtain first pole plate and first conductor wire conducting, the bonding between second pole plate and second conductor wire
A piece metal wire, so that second pole plate and second conductor wire conducting, reuse capacitance detecting device detection limit
The capacitor of sub- chip, it is more stable due to connecting at this time, it is not easily to fall off, so that detection is more convenient efficiently, the amount of substantially increasing
The detection efficiency of sub- chip capacity.
Detailed description of the invention
Fig. 1 is the schematic diagram of substrate structure used in the first implementation of the present invention；
Fig. 2 is the schematic diagram of substrate structure used in another implementation of the invention.
Specific embodiment
The embodiments described below with reference to the accompanying drawings are exemplary, for explaining only the invention, and cannot be construed to
Limitation of the present invention.
Embodiment 1
Quantum chip is the basic Component units of quantum computer, is using the synergistic effect of quantum state as principle, with quantum
Bit is the processor of the carrier of information processing, and quantum chip mainly includes Superconducting Quantum chip, semiconductor quantum chip, quantum
Point chip, ion trap and NV (diamond) colour center etc..
Quantum chip needs to test its actual capacitance when leaving the factory, according to the design capacitance of actual capacitance and quantum chip it
Between error size judge whether quantum chip qualified.
In conjunction with attached drawing 1, the present invention provides a kind of quantum chip capacity detection methods, comprising the following steps:
Substrate 1, quantum chip 2, bonding machine (not shown), metal wire 3 and capacitance detecting device (not shown) are provided,
On the surface of the substrate 1, area 13 is placed in setting, and 11 He of the first conductor wire is respectively set at the two edges for placing area 13
Second conductor wire 12, in which: 2, the quantum core include the first pole plate 21 and the second pole plate 22 being oppositely arranged；
The quantum chip 2 is fixed in the placement area 13 of the substrate 1；
Using bonding machine between first pole plate 21 and first conductor wire 11 mono- wires of bonding
3, so that first pole plate 21 and first conductor wire 11 conducting, in second pole plate 22 and second conductor wire 12
Between mono- wires 3 of bonding so that second pole, 22 and second conductor wire 12 conducting.
First conductor wire positive terminal of capacitance detecting device and negative terminal being separately connected on substrate 1
11 and second conductor wire 12；
The power supply of capacitance detecting device is connected, the capacitor of quantum chip 2 is detected.
Compared with prior art, the present invention places area 13 by being arranged on the substrate 1, at the two edges in security protection area 13
Two conductor wires, i.e. the first conductor wire 11 and the second conductor wire 12 are set, using bonding machine by two metal conductive wires
3bonding is in 22 He of the first pole plate 21 and the first conductor wire 11 and the second pole plate for pasting quantum chip 2 on substrate 1
Between second conductor wire 12, the capacitor of capacitance detecting device detection quantum chip 2 is reused, it is more stable due to connecting at this time,
It is not easily to fall off, so that detection is more convenient efficiently, substantially increase the detection efficiency of 2 capacitor of quantum chip.
Embodiment 2
Specific: in conjunction with attached drawing 1, the present invention provides a kind of quantum chip capacity detection methods, comprising the following steps:
Step S1: substrate 1, quantum chip 2, bonding machine (not shown), metal wire 3 and capacitance detecting device (figure are provided
Do not show), area 13 is placed in setting on the substrate 1, and two conductor wires, respectively the are arranged at the two edges for placing area 13
One conductor wire 11 and the second conductor wire 12, in which: first conductor wire 11 and second conductor wire 12 are on the substrate 1
Between region formed the quantum chip 2 be place area 13, the quantum chip 2 include the first pole plate 21 and the second pole
Plate 21；
Wherein: two conductor wires being arranged on the substrate 1, respectively the first conductor wire 11 and the second conductor wire 12,
Specifically, first conductor wire 11 and second conductor wire can be respectively set at two opposite edges for placing area 13
12, and the first conductor wire 11 and second conductor wire 12 are disposed as straight line, and make first conductor wire 11 and second
The side by side parallel on the substrate 1 of conductor wire 12 is arranged, so set, simpler convenience, is easy to make, described first is conductive
Region is to place area 13 between line 11 and second conductor wire 12；
In conjunction with attached drawing 2, optional another way, the setting side of first conductor wire 11 and second conductor wire 12
Formula can also be the first conductor wire 11 and the second conductor wire 12 to be respectively set at 13 liang of neighboring edges in the security protection area, by institute
It states the first conductor wire 11 and second conductor wire 12 is disposed as straight line, and make first conductor wire 11 and described second
Conductor wire 12 is arranged in a crossed manner on the substrate 1, at this point, first conductor wire 11 and second conductor wire 12 are with crosspoint
Centered on, 4 placement areas 13 that can place the quantum chip 2 are formed, it can be in order to being examined to multiple quantum chips 2
It surveys, further, the shape of the substrate 1 may be alternatively provided as rectangular or round.
Wherein, the bonding machine refers to the machine that can be realized Wire-Bonding, Wire-Bonding (i.e. pressure welding,
Help fixed, bonding or wire bond) refer to using metal wire (such as gold thread), using hot pressing or the ultrasonic energy, complete in microelectronic component admittedly
The connection of state circuit intraconnection wiring, i.e. connection between chip and circuit or lead frame.
Wherein, the metal wire 3 can use metallic aluminium silk thread, using aluminum steel, can in steady operation under superconducting state,
According to the actual situation, the diameter of aluminum steel is set as 25 μm, and length is set as 3mm；
Wherein, the capacitance detecting device can use transformer ratio arm capacitance bridge, and 2700A can be used in concrete model
ULTRA PRECISION 50Hz-20KHz CAPACITANCE BRIDGE。
Step S2: the quantum chip 2 is fixed on the placement area 13.
Specifically, the quantum chip 2 is fixed on the mode in the placement area 13 of the substrate 1, it can direct institute
Gluing in the surface mount area 13 of substrate 1 is stated, then the quantum chip 2 is pasted onto and is placed in area 13, easy to operate, efficiency
It is high.
Step S3: using bonding machine bonding mono- between first pole plate 21 and first conductor wire 11
Metal wire 3, so that first pole plate 21 and first conductor wire 11 conducting, lead in second pole plate 21 with described second
Mono- wires 3 of bonding between electric wire 22, so that second pole plate 21 and second conductor wire 22 conducting.
Specifically, using bonding machine by two metal lines 3 difference bonding described the first of the quantum chip 2
Between pole plate 21 and first conductor wire 11 and second pole plate 22 of the quantum chip 2 and second conductor wire
Between 12, so that each metal line 3 is located on the extended line of first pole plate 21 and 22 line of the second pole plate, this
A possibility that sample can reduce the length of the metal wire 3 of bonding to the greatest extent, and metal wire 3 is shorter, generate inductance is smaller,
Influence to testing result is smaller.
Step S4: described positive terminal of capacitance detecting device and negative terminal are separately connected on substrate 1
One conductor wire 11 and second conductor wire 12.
Further, 1 edge of substrate can be located in first conductor wire 11 and second conductor wire 12
Endpoint at be arranged port, to facilitate the connection of the positive terminal and negative terminal of the capacitance detecting device.
Step S5: connecting the power supply of capacitance detecting device, detects the capacitor of quantum chip 2.
Specifically, needing to wait for a period of time after the power supply for connecting capacitance detecting device, wait after stablizing, then detect
The capacitor of quantum chip 2.
Specifically, transformer ratio arm capacitance bridge can be used in the capacitance detecting device, concrete model be can be used
2700A ULTRA PRECISION 50Hz-20KHz CAPACITANCE BRIDGE, after powering on, needs to wait
After 20min stablizes, then detected.
By using foregoing invention method, the connection of quantum chip and detection device is more stable, not easily to fall off, so that inspection
Survey it is more convenient efficiently, substantially increase the detection efficiency of quantum chip capacity
Structure, feature and effect of the invention, the above institute are described in detail based on the embodiments shown in the drawings
Only presently preferred embodiments of the present invention is stated, but the present invention does not limit the scope of implementation as shown in the drawings, it is all according to structure of the invention
Think made change or equivalent example modified to equivalent change, when not going beyond the spirit of the description and the drawings,
It should all be within the scope of the present invention.
Claims (7)
1. a kind of quantum chip capacity detection method, which comprises the following steps:
Substrate, quantum chip, bonding machine, metal wire and capacitance detecting device are provided, is arranged on the surface of the substrate and places
The first conductor wire and the second conductor wire is respectively set at the two edges for placing area, in which: the quantum chip includes in area
The first pole plate and the second pole plate being oppositely arranged；
The quantum chip is fixed in the placement area of the substrate；
Using bonding machine between first pole plate and first conductor wire mono- wires of bonding so that described
First pole plate and first conductor wire conducting, piece institute of bonding between second pole plate and second conductor wire
Metal wire is stated, so that second pole plate and second conductor wire conducting；
First conductor wire positive terminal of the capacitance detecting device and negative terminal being separately connected on substrate
With second conductor wire；
The power supply of capacitance detecting device is connected, the capacitor of quantum chip is detected.
2. quantum chip capacity detection method according to claim 1, it is characterised in that:
The metal wire uses metallic aluminium silk thread.
3. quantum chip capacity detection method according to claim 1, it is characterised in that:
25 μm of the diameter of the metallic aluminium silk thread, length 3mm.
4. quantum chip capacity detection method according to claim 1, it is characterised in that:
The capacitance detecting device is transformer ratio arm capacitance bridge.
5. quantum chip capacity detection method according to claim 1, it is characterised in that: the surface in the substrate
Area is placed in setting, and the first conductor wire and the second conductor wire is respectively set at the two edges for placing area, specifically includes:
Be respectively set the first conductor wire and the second conductor wire at two opposite edges for placing area, first conductor wire and
The second parallel conductive line setting；
Or the first conductor wire and the second conductor wire are respectively set at two neighboring edges in the security protection area, first conductor wire
It is arranged in a crossed manner with second conductor wire.
6. quantum chip capacity detection method according to claim 1, it is characterised in that: the quantum chip to be fixed on
In the placement area on the substrate, specifically include:
The quantum chip is fixed on to the placement area of the substrate surface by way of stickup.
7. -6 any quantum chip capacity detection method according to claim 1, which is characterized in that the use
Bonding machine piece metal wire of bonding between first pole plate and first conductor wire, so that described first
Pole plate and first conductor wire conducting, piece gold of bonding between second pole plate and second conductor wire
Belong to line, so that second pole plate and second conductor wire conducting, specifically include:
Each metal wire is arranged to be respectively positioned on the extended line of first pole plate and the second pole plate line.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910195191.4A CN109884504A (en) | 2019-03-14 | 2019-03-14 | A kind of quantum chip capacity detection method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910195191.4A CN109884504A (en) | 2019-03-14 | 2019-03-14 | A kind of quantum chip capacity detection method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109884504A true CN109884504A (en) | 2019-06-14 |
Family
ID=66932424
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910195191.4A Pending CN109884504A (en) | 2019-03-14 | 2019-03-14 | A kind of quantum chip capacity detection method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109884504A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112444713A (en) * | 2019-08-28 | 2021-03-05 | 合肥本源量子计算科技有限责任公司 | Quantum chip detection method |
Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN85202256U (en) * | 1985-06-12 | 1986-06-11 | 福建省计量科学技术研究所 | Direct reading transformer condenser bridge |
| CN101105504A (en) * | 2006-07-10 | 2008-01-16 | 中芯国际集成电路制造(上海)有限公司 | Probe card device |
| CN101285863A (en) * | 2007-04-10 | 2008-10-15 | 系新科技股份有限公司 | Circuit board measurement method and device |
| CN101384914A (en) * | 2006-02-23 | 2009-03-11 | 松下电器产业株式会社 | Semiconductor integrated circuit and method for inspecting same |
| CN103630824A (en) * | 2012-08-28 | 2014-03-12 | 上海华虹宏力半导体制造有限公司 | Chip concurrent test system |
| CN103969511A (en) * | 2014-05-27 | 2014-08-06 | 上海先进半导体制造股份有限公司 | Measuring method for capacity parameters of each chip on silicon chip |
| CN204758704U (en) * | 2015-06-22 | 2015-11-11 | 南通金泰科技有限公司 | Calculate passive RFID chip resonant capacitor's device |
| CN105388387A (en) * | 2015-11-25 | 2016-03-09 | 天津市捷威动力工业有限公司 | Device and method for detecting short circuit between flexible packaging lithium ion battery negative electrode and shell |
| CN205809182U (en) * | 2016-07-04 | 2016-12-14 | 中国振华集团云科电子有限公司 | Chip capacity temperature property test fixture |
| CN106783654A (en) * | 2016-11-28 | 2017-05-31 | 西安科锐盛创新科技有限公司 | The preparation method of bare chip test protection structure |
| CN207571216U (en) * | 2017-11-24 | 2018-07-03 | 长兴衡鑫仪表科技有限公司 | A kind of chip resistor test fixture |
| CN108445293A (en) * | 2018-05-29 | 2018-08-24 | 合肥本源量子计算科技有限责任公司 | A kind of quantum chip port impedance test device and measurement method |
| CN108761310A (en) * | 2018-05-25 | 2018-11-06 | 合肥本源量子计算科技有限责任公司 | A kind of test method of quantum chip |
-
2019
- 2019-03-14 CN CN201910195191.4A patent/CN109884504A/en active Pending
Patent Citations (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN85202256U (en) * | 1985-06-12 | 1986-06-11 | 福建省计量科学技术研究所 | Direct reading transformer condenser bridge |
| CN101384914A (en) * | 2006-02-23 | 2009-03-11 | 松下电器产业株式会社 | Semiconductor integrated circuit and method for inspecting same |
| CN101105504A (en) * | 2006-07-10 | 2008-01-16 | 中芯国际集成电路制造(上海)有限公司 | Probe card device |
| CN101285863A (en) * | 2007-04-10 | 2008-10-15 | 系新科技股份有限公司 | Circuit board measurement method and device |
| CN103630824A (en) * | 2012-08-28 | 2014-03-12 | 上海华虹宏力半导体制造有限公司 | Chip concurrent test system |
| CN103969511A (en) * | 2014-05-27 | 2014-08-06 | 上海先进半导体制造股份有限公司 | Measuring method for capacity parameters of each chip on silicon chip |
| CN204758704U (en) * | 2015-06-22 | 2015-11-11 | 南通金泰科技有限公司 | Calculate passive RFID chip resonant capacitor's device |
| CN105388387A (en) * | 2015-11-25 | 2016-03-09 | 天津市捷威动力工业有限公司 | Device and method for detecting short circuit between flexible packaging lithium ion battery negative electrode and shell |
| CN205809182U (en) * | 2016-07-04 | 2016-12-14 | 中国振华集团云科电子有限公司 | Chip capacity temperature property test fixture |
| CN106783654A (en) * | 2016-11-28 | 2017-05-31 | 西安科锐盛创新科技有限公司 | The preparation method of bare chip test protection structure |
| CN207571216U (en) * | 2017-11-24 | 2018-07-03 | 长兴衡鑫仪表科技有限公司 | A kind of chip resistor test fixture |
| CN108761310A (en) * | 2018-05-25 | 2018-11-06 | 合肥本源量子计算科技有限责任公司 | A kind of test method of quantum chip |
| CN108445293A (en) * | 2018-05-29 | 2018-08-24 | 合肥本源量子计算科技有限责任公司 | A kind of quantum chip port impedance test device and measurement method |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112444713A (en) * | 2019-08-28 | 2021-03-05 | 合肥本源量子计算科技有限责任公司 | Quantum chip detection method |
| CN112444713B (en) * | 2019-08-28 | 2021-10-08 | 合肥本源量子计算科技有限责任公司 | Quantum chip detection method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN218730911U (en) | Double-sided heat dissipation packaging structure with internal insulation | |
| CN102468122A (en) | Manufacturing method for semiconductor device failure analysis sample and analysis method | |
| CN205984975U (en) | Filtering transient state high -voltage pulse's ultra -thin rectifier bridge | |
| CN109817612B (en) | Encapsulation structure for improving electrothermal performance of welded silicon carbide power module | |
| CN103852707B (en) | A kind of power semiconductor chip test fixture | |
| CN109884504A (en) | A kind of quantum chip capacity detection method | |
| CN204706557U (en) | A kind of Intelligent Power Module | |
| CN106104290A (en) | High-sensitiivty magnetic sensor and preparation method thereof | |
| CN109031102A (en) | A kind of apparatus for testing chip | |
| CN105277864B (en) | Experimental rig, test method and the hookup of semiconductor chip | |
| CN212625492U (en) | LED chip detection device | |
| CN216411361U (en) | Test fixture for parallel testing IGBT (insulated Gate Bipolar transistor) chip and FRD (fast recovery diode) chip | |
| WO2024031819A1 (en) | Test method for integrated micro led | |
| WO2022156132A1 (en) | Chip test board and chip test method | |
| CN206671370U (en) | A kind of multi-functional clamp for chip capacitor electric performance test | |
| CN209543219U (en) | A kind of computer module based on 3 D stereo encapsulation | |
| CN108400131A (en) | Interior cascaded structure diode pipe heap | |
| CN207651047U (en) | A kind of patch chip experiment bread board | |
| CN203746841U (en) | Power semiconductor module | |
| CN213934111U (en) | Semiconductor laser chip aging device | |
| CN206179859U (en) | Packaging structure of series connection diode | |
| CN201716338U (en) | Test fixture used for impedance analyzer | |
| TW201307860A (en) | Method for bonding chips having double-sided electrical connections with an instant test | |
| CN211957650U (en) | Process improved diode | |
| CN205376474U (en) | Switching interface board with high bonding strength and multilayer structure |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20190614 |
|
| RJ01 | Rejection of invention patent application after publication |