CN109873036A - Mosfet结构及其制造方法 - Google Patents
Mosfet结构及其制造方法 Download PDFInfo
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Abstract
本发明涉及一种MOSFET结构及其制造方法。所述结构包括:衬底;第一导电类型阱区;第一沟槽,开设于第一导电类型阱区表面并向下延伸至第二导电类型阱区;源极,设于第二导电类型阱区内、第一沟槽下方;栅氧化层,设于第一沟槽的内表面;多晶硅栅,填充于第一沟槽底部的侧壁,位于栅氧化层上;导电栓塞,从第一沟槽的上方向下延伸,贯穿源极后与第二导电类型阱区接触;绝缘氧化层,填充于第一沟槽内、导电栓塞与多晶硅栅之间;漏极,设于第一沟槽外、源极的斜上方。本发明将传统集成工艺的高压器件由横向器件改为部分纵向的器件,将栅端以深沟槽工艺埋入器件内部,并形成垂直方向的沟道区,可以最大化降低高压器件所需要的横向尺寸。
Description
技术领域
本发明涉及半导体制造领域,特别是涉及一种MOSFET(金属氧化物半导体场效应管)结构,还涉及一种MOSFET结构的制造方法。
背景技术
传统集成工艺的高压横向器件,例如横向扩散金属氧化物半导体场效应管(LDMOSFET),是由改变漏端漂移区浓度与长度来实现调整耐压与降低导通电阻。对于漂移区长度占器件尺寸的绝大部分的高压横向器件,再进一步提高器件电压或者缩小器件尺寸皆无法实现,尤其在器件已经优化达到物理极限状态的时候再进一步缩小器件尺寸似乎不太现实。
发明内容
基于此,为了进一步缩小器件尺寸,有必要提供一种MOSFET结构及其制造方法。
一种MOSFET结构,包括:衬底;第一导电类型阱区,设于所述衬底上;第一沟槽,开设于所述第一导电类型阱区表面并向下延伸;第二导电类型阱区,所述第一沟槽是向下延伸至所述第二导电类型阱区;源极,具有第一导电类型,设于所述第二导电类型阱区内、所述第一沟槽下方;栅氧化层,设于所述第一沟槽的内表面;多晶硅栅,填充于所述第一沟槽底部的侧壁,位于所述栅氧化层上;导电栓塞,从所述第一沟槽的上方向下延伸,贯穿所述源极后与所述第二导电类型阱区接触;绝缘氧化层,填充于所述第一沟槽内、所述导电栓塞与多晶硅栅之间,覆盖所述多晶硅栅并将所述多晶硅栅与所述源极进行绝缘隔离;及漏极,具有第一导电类型,设于所述第一沟槽外、所述源极的斜上方;所述第一导电类型和第二导电类型为相反的导电类型。
在其中一个实施例中,所述漏极和所述第一沟槽之间还设有隔离结构。
在其中一个实施例中,还包括:第二沟槽;栅极引出结构,从所述第二沟槽底部向上堆积以致从所述第二沟槽露出;衬底引出,具有第二导电类型,所述衬底引出和所述第二沟槽之间设有隔离结构。
在其中一个实施例中,所述衬底具有第二导电类型,所述第二导电类型阱区设于所述第一导电类型阱区内,所述导电栓塞向下贯穿所述第二导电类型阱区后延伸至所述衬底。
在其中一个实施例中,所述导电栓塞的材质为金属,或所述导电栓塞的材质为合金,或所述导电栓塞的材质包括金属和金属氮化物。
在其中一个实施例中,所述第一导电类型是N型,所述第二导电类型是P型。
一种MOSFET结构的制造方法,包括:A,提供在衬底上形成有第一导电类型阱区的晶圆;步骤B,在所述第一导电类型阱区表面开设向下延伸的第一沟槽;步骤C,在所述第一沟槽的内表面形成栅氧化层;步骤D,向所述第一沟槽内填充多晶硅,将所述第一沟槽填满;步骤E,刻蚀所述多晶硅至预定厚度,在所述第一沟槽底部形成该预定厚度的多晶硅层;步骤F,在所述多晶硅层的表面和所述第一沟槽的侧壁形成第一绝缘氧化层;步骤G,向下刻蚀所述第一绝缘氧化层和多晶硅层,使所述第一沟槽的底部露出,所述侧壁的多晶硅层和第一绝缘氧化层被保留;步骤H,分别注入第二导电类型和第一导电类型的离子,在所述第一沟槽的下方形成第二导电类型阱区,在所述第二导电类型阱区内形成源极;步骤I,在所述第一沟槽内形成第二绝缘氧化层,将所述多晶硅层与所述源极进行绝缘隔离;及步骤J,在所述第一沟槽外、所述源极的斜上方注入第一导电类型的离子,形成漏极,并刻蚀所述第一沟槽底部的第二绝缘氧化层将所述第二导电类型阱区和源极露出,向所述第一沟槽内填入导电材料、形成贯穿所述源极与所述第二导电类型阱区接触的导电栓塞;所述第一导电类型和第二导电类型为相反的导电类型。
在其中一个实施例中,所述步骤A提供的晶圆还形成有隔离结构;所述步骤B是光刻后刻蚀部分所述隔离结构,将所述隔离结构刻穿后,以被所述光刻胶保护而未被刻蚀的隔离结构为硬掩膜,继续向下刻蚀所述第一导电类型阱区形成所述第一沟槽。
在其中一个实施例中,所述步骤B还包括同时开设第二沟槽;所述步骤C还包括同时在所述第二沟槽的内表面形成栅氧化层;所述步骤D还包括将所述第二沟槽也填满;所述步骤E是光刻后进行刻蚀,光刻形成的光刻胶将所述第二沟槽内的多晶硅至少部分遮挡从而在刻蚀后形成露出所述第二沟槽的栅极引出结构。
在其中一个实施例中,所述步骤G之后、所述在步骤I之前,还包括通过注入第二导电类型的离子,在所述第二导电类型阱区内、所述源极下方形成第二导电类型掺杂区的步骤。
在其中一个实施例中,所述步骤J具体包括:向所述第一沟槽内填入绝缘氧化材料;光刻并注入第一导电类型的离子,在所述第一沟槽外、所述源极的斜上方形成所述漏极;去胶后再次光刻,光刻胶在需要形成所述导电栓塞的位置露出刻蚀窗口;通过所述刻蚀窗口向下刻蚀至所述导电栓塞所需的深度;向所述第一沟槽内填入导电材料,形成所述导电栓塞。
在其中一个实施例中,所述去胶后再次光刻的步骤,是去胶后在所述漏极的表面形成第三绝缘氧化层,然后再次光刻;所述通过所述刻蚀窗口向下刻蚀至所述导电栓塞所需的深度的步骤,是采用第一刻蚀剂,通过所述刻蚀窗口向下刻蚀至所述第一沟槽底部,然后去胶,以所述第三绝缘氧化层为刻蚀掩膜、采用第二刻蚀剂继续刻蚀至所述导电栓塞所需的深度。
在其中一个实施例中,所述衬底具有第二导电类型;所述步骤H中,控制第二导电类型的离子的注入深度使得所述第二导电类型阱区形成于所述第一导电类型阱区内;所述步骤J中,所述导电栓塞向下贯穿所述第二导电类型阱区后延伸至所述衬底。
上述MOSFET结构,将传统集成工艺的高压器件由横向器件(例如LDMOSFET)改为部分纵向的器件,将栅端以深沟槽工艺埋入器件内部,并形成垂直方向的沟道区,可以最大化降低高压器件所需要的横向尺寸(pitch)。漂移区(Drift)的尺寸越大,节省的尺寸就越大。且该结构的漏端在上,相对于漏端在下的垂直结构器件(例如VDMOSFET),器件的栅、源、漏都可以从正面引出,引出更方便,且可以兼容传统横向器件的隔离结构工艺(例如STI)。
附图说明
图1是一实施例中MOSFET结构的剖面结构示意图;
图2是一实施例中集成了肖特基二极管的MOSFET结构的剖面结构示意图;
图3是一实施例中采用了MOSFET结构的高端高压管的剖面结构示意图;
图4是一实施例中采用了MOSFET结构的低端高压管的剖面结构示意图;
图5是一实施例中MOSFET结构的制造方法的流程图;
图6a~6f是一实施例中采用MOSFET结构的制造方法制造MOSFET结构的各个中间步骤完成后器件的剖面结构示意图;
图7一实施例中图5所示方法的步骤S210的子步骤的流程图。
具体实施方式
为了便于理解本发明,下面将参照相关附图对本发明进行更全面的描述。附图中给出了本发明的首选实施例。但是,本发明可以以许多不同的形式来实现,并不限于本文所描述的实施例。相反地,提供这些实施例的目的是使对本发明的公开内容更加透彻全面。
除非另有定义,本文所使用的所有的技术和科学术语与属于本发明的技术领域的技术人员通常理解的含义相同。本文中在本发明的说明书中所使用的术语只是为了描述具体的实施例的目的,不是旨在于限制本发明。本文所使用的术语“及/或”包括一个或多个相关的所列项目的任意的和所有的组合。
本说明书所使用的半导体领域词汇为本领域技术人员常用的技术词汇,例如对于P型和N型杂质,为区分掺杂浓度,简易的将P+型代表重掺杂浓度的P型,P型代表中掺杂浓度的P型,P-型代表轻掺杂浓度的P型,N+型代表重掺杂浓度的N型,N型代表中掺杂浓度的N型,N-型代表轻掺杂浓度的N型。
图1是一实施例中MOSFET结构的剖面结构示意图,包括衬底10、第一导电类型阱区20、第二导电类型阱区22、源极24、漏极26、多晶硅栅40、栅氧化层32、绝缘氧化层34以及导电栓塞50。在本实施例中,衬底10为硅衬底。
其中第一导电类型阱区20设于衬底10上。第一导电类型阱区20表面开设有向下延伸至第二导电类型阱区22的至少一个第一沟槽(图1中未标示)。栅氧化层32设于第一沟槽的内表面,第一沟槽底部靠近侧壁的区域填充有多晶硅栅40,在剖视图(图1)中表现为设于第一沟槽底部的两侧,且位于栅氧化层32上。源极24具有第一导电类型,设于第二导电类型阱区22内、第一沟槽位于多晶硅栅40之间的区域的下方。导电栓塞50从第一沟槽的上方向下延伸,贯穿源极24后与第二导电类型阱区22接触。绝缘氧化层34填充于第一沟槽内、导电栓塞50与多晶硅栅40之间,将第一沟槽内的剩余空间填满,覆盖多晶硅栅40并将多晶硅栅40与源极24进行绝缘隔离。
漏极26具有第一导电类型,设于第一沟槽外,源极24的斜上方,且在本实施例中设于第一导电类型阱区20。在本实施例中,第一导电类型为N型,第二导电类型为P型,相应地,第二导电类型阱区22为P阱,第一导电类型阱区20为高压N阱;在其他实施例中,也可以是第一导电类型为P型,第二导电类型为N型。
上述MOSFET结构,将传统集成工艺的高压器件由横向器件(例如LDMOSFET)改为部分纵向的器件,将栅端以深沟槽工艺埋入器件内部,并形成垂直方向的沟道区,可以最大化降低高压器件所需要的横向尺寸(pitch)。漂移区(Drift)的尺寸越大,节省的尺寸就越大。且该结构的漏端在上,相对于漏端在下的垂直结构器件(例如VDMOSFET),器件的栅、源、漏都可以从正面引出,引出更方便,且可以兼容传统横向器件的隔离结构工艺(例如STI)。
在一个实施例中,绝缘氧化层34的材质为氧化硅。
在一个实施例中,导电栓塞50的材质为金属。在另一个实施例中,导电栓塞50的材质为合金。在又一个实施例中,导电栓塞50的材质包括金属和金属氮化物。设置导电栓塞50,相当于手指状金属热片穿插进器件内部,这样散热的路径垂直深入器件内部,能够有效加大热能引出,大大的增加热能逸散,因此改善了器件的热击穿烧毁特性。
在图1所示实施例中,漏极26和第一沟槽之间还设有隔离结构36。隔离结构36用于在进行第一沟槽刻蚀时作为硬掩膜,具体是光刻后先用适合刻蚀隔离结构(氧化硅)的刻蚀剂刻蚀隔离结构至其底部,光刻得到的刻蚀窗口要比隔离结构36小,使得刻蚀得到的第一沟槽周围还留有部分隔离结构36;然后使用适合刻蚀硅的刻蚀剂、以残留的隔离结构36为硬掩膜刻蚀至所需的第一沟槽深度。可以理解的,晶圆中会形成有大量的隔离结构,作为第一沟槽刻蚀时的硬掩膜的隔离结构36只是其中的一部分。
在一个实施例中,隔离结构36为浅沟槽隔离结构(Shallow Trench Isolation,STI)。在另一个实施例中,隔离结构36为LOCOS形成的场氧。
在图1所示的实施例中,还设有钨塞60,导电栓塞50和漏极26通过钨塞60引出至金属互联层进行电连接。在其他实施例中,钨塞60也可以采用其他本领域习知的导电金属材质。
可以通过控制导电栓塞50和第一导电类型阱区20的深度,获得不同电位的器件。例如根据所需求高压管组合,调整导电栓塞50和第一导电类型阱区20的深度,形成低端(Low Side)高压管、隔离(Iso)高压管、高端(High Side)高压管、集成肖特基二极管的低端高压管等结构。上述MOSFET结构同样适用于VDMOSFET、IGBT等结构。
图2是一实施例中集成了肖特基二极管的MOSFET结构的剖面结构示意图。除了包括图1所示的结构之外,还包括第二沟槽(图2中未标示)、栅极引出结构42及衬底引出28。栅极引出结构42从第二沟槽底部向上延伸露出第二沟槽。衬底引出28具有第二导电类型,且衬底引出28和第二沟槽之间设有隔离结构36。对于导电栓塞50向下延伸至衬底10的实施例中,也可以不设置衬底引出,即不设置衬底引出28。
在其中一个实施例中,衬底10具有第二导电类型,第二导电类型阱区22设于第一导电类型阱区20内,导电栓塞50向下贯穿第二导电类型阱区22后延伸至衬底10,参见图1和图2。
在图2所示实施例中,导电栓塞50的材质包括金属和金属氮化物,从而形成纵向的金属半导体界面(也即形成垂直式的金属半导体界面,金属作为金属半导体界面的接触金属)。其中导电栓塞50作为肖特基二极管的阳极,第一导电类型阱区20介于第二导电类型阱区22和衬底10之间的部分作为肖特基二极管的阴极。
图3是一实施例中采用了MOSFET结构的高端高压管的剖面结构示意图。可以理解的,隔离高压管也可以采用图3所示的结构。由于图3大部分结构与图1相同,因此部分结构的标号予以省略。其与图1所示结构的主要区别在于,导电栓塞50的深度只到第二导电类型阱区22内,不继续向下贯穿出第二导电类型阱区22至衬底10。
在图3所示的实施例中,第二导电类型阱区22内、源极24下方还设有第二导电类型掺杂区29,第二导电类型掺杂区29与导电栓塞50的底部接触,作为衬底引出。
图4是一实施例中采用了MOSFET结构的低端高压管的剖面结构示意图,同样省略了部分标号。其与图3所示结构的主要区别在于,第一导电类型阱区20的阱深较浅,因此第二导电类型阱区22伸入衬底10内。
图5是一实施例中MOSFET结构的制造方法的流程图,包括下列步骤:
S110,提供在衬底上形成有第一导电类型阱区的晶圆。
在本实施例中,衬底为硅衬底,第一导电类型为N型,第二导电类型为P型。在其他实施例中,也可以是第一导电类型为P型,第二导电类型为N型。
S120,在第一导电类型阱区表面开设向下延伸的沟槽。
在本实施例中,步骤S110提供的晶圆还形成有隔离结构36,参见图6a。在一个实施例中,隔离结构36为浅沟槽隔离结构(Shallow Trench Isolation,STI)。在另一个实施例中,隔离结构36为LOCOS形成的场氧。在本实施例中,步骤S120是光刻后形成光刻胶图案11,根据需要第一沟槽的尺寸将隔离结构36相应的部分露出,其余部分遮挡掉,并以光刻胶图案11为掩膜,采用适合刻蚀氧化硅的刻蚀剂刻蚀隔离结构36。参见图6b,将隔离结构36刻穿后,以被光刻胶团11保护而未被刻蚀的隔离结构36为硬掩膜,继续向下刻蚀第一导电类型阱区20形成第一沟槽21。在一个实施例中,以隔离结构36为硬掩膜继续向下刻蚀之前,可以先进行去胶。
S130,在沟槽的内表面形成栅氧化层。
可以使用热氧化工艺形成栅氧化层32,第一沟槽21的内表面只会在硅(第一导电类型阱区20)的表面形成栅氧化层32,隔离结构36的表面不会形成栅氧化层32,参见图6c。
S140,向沟槽内填充多晶硅,将沟槽填满。
在一个实施例中,可以采用淀积工艺填充多晶硅,淀积的多晶硅层可以漫出沟槽。
S150,刻蚀多晶硅至预定厚度,在沟槽底部形成该预定厚度的多晶硅层。
在一个实施例中,步骤S120刻蚀出的沟槽包括第一沟槽21和第二沟槽23,其中第二沟槽23为环形沟槽,因此在剖视图图6d的两侧都能见到,第二沟槽23之间形成有多个第一沟槽21。同理,步骤S130也会在第二沟槽23的内表面形成栅氧化层32,步骤S140也会将第二沟槽23填满多晶硅,参见图6d。步骤S150刻蚀时先进行光刻,形成光刻胶图案13,第二沟槽23内的多晶硅至少部分被光刻胶图案13遮挡,从而在刻蚀后形成露出第二沟槽23的栅极引出结构42,刻蚀后将光刻胶图案13去除。同理,第一沟槽21底部同样会形成多晶硅栅40。
在一个实施例中,第一沟槽21和第二沟槽23的刻蚀可以同步进行,这样就只需一步光刻(刻蚀隔离结构36所需的光刻)。在其他实施例中,也可以将第一沟槽21和第二沟槽23进行分开刻蚀,即第一沟槽21和第二沟槽23的刻蚀可以各使用一块光刻版,这样第一沟槽21和第二沟槽23的可以刻蚀出不同的深度。
S160,在多晶硅层的表面和沟槽的侧壁形成第一绝缘氧化层。
在一个实施例中,可以采用淀积工艺形成第一绝缘氧化层342,参见图6e。在本实施例中,第一绝缘氧化层342的材质为氧化硅。可以理解的,对于需要形成第二沟槽23的实施例,也会在第二沟槽23的多晶硅层的表面形成第一绝缘氧化层。
S170,向下刻蚀第一绝缘氧化层和多晶硅层,露出沟槽底部。
在一个实施例中,首先进行第一绝缘氧化层342的回刻,第一沟槽侧壁的第一绝缘氧化层342在回刻后仍然保留,而位于中间的第一绝缘氧化层342被刻蚀掉,将多晶硅栅40露出,刻蚀采用适合刻蚀氧化硅的刻蚀剂,可以不使用光刻胶。然后进行多晶硅栅40的刻蚀,采用适合刻蚀多晶硅的刻蚀剂,以第一绝缘氧化层342为掩膜刻蚀多晶硅栅40,露出第一沟槽的底部。
S180,在第一沟槽下方形成第二导电类型阱区,在该阱区内形成第一导电类型的源极。
在本实施例中,是向第一沟槽内注入第二导电类型的离子,在第一沟槽的下方形成第二导电类型阱区22;然后注入第一导电类型的离子,在第二导电类型阱区22内形成源极24。在第一、第二导电类型的离子注入时第一沟槽侧壁的第一绝缘氧化层342会作为阻挡层。第二导电类型的离子之后还要进行推阱。为了保证多晶硅栅40与源极24之间更好的绝缘,在一个实施例中,上述推阱在离子注入形成源极24之前,这样因为第一绝缘氧化层342的阻挡作用,源极24在横向与多晶硅栅40基本不重合,参见图6f。
S190,在沟槽内形成第二绝缘氧化层,将多晶硅层与源极进行绝缘隔离。
可以采用淀积工艺向沟槽内填充第二绝缘氧化层。在一个实施例中,可以在淀积后再将第一沟槽底部的第二绝缘氧化层刻蚀开,为下一步形成导电栓塞预留位置。在一个实施例中,将第一沟槽底部的第二绝缘氧化层刻蚀开后,还可以再次进行第一导电类型的离子的注入,本次注入形成的掺杂区比步骤S180注入形成掺杂区浓度更高(步骤S180的注入可以采用轻掺杂漏极工艺),因此实际上本次注入形成的掺杂区才是真正的源极引出。
S210,在源极斜上方形成漏极,并向沟槽内填入导电材料形成导电栓塞。
在第一沟槽外、源极24的斜上方注入第一导电类型的离子,形成漏极26,并刻蚀第一沟槽底部的第二绝缘氧化层,将第二导电类型阱区和源极24露出,向第一沟槽内填入导电材料,形成贯穿源极24、与第二导电类型阱区22接触的导电栓塞50。步骤S210完成后的器件结构可以参见图4。
图7是一实施例中步骤S210的子步骤的流程图,具体包括:
S211,向第一沟槽内填入绝缘氧化材料。
由于接下来的步骤中需要进行光刻,因此用绝缘氧化材料将第一沟槽填满,避免光刻胶填入第一沟槽中导致去胶时难以除净。
S213,光刻并注入第一导电类型的离子,形成漏极。
涂胶并光刻将需要形成漏极的位置露出,注入第一导电类型的离子形成漏极。
S215,去胶后再次光刻,光刻胶在需要形成导电栓塞的位置露出刻蚀窗口。
在一个实施例中,去胶后在晶圆表面形成第三绝缘氧化层,将漏极覆盖,然后再次涂胶和光刻,在需要形成导电栓塞的位置露出刻蚀窗口。在一个实施例中,第三绝缘氧化层的材质是氧化硅。
S217,通过刻蚀窗口向下刻蚀至导电栓塞所需的深度。
在一个实施例中,是采用适合刻蚀氧化硅的刻蚀剂,通过刻蚀窗口向下刻蚀至第一沟槽底部。然后去胶,以第三绝缘氧化层为刻蚀掩膜、采用适合刻蚀硅的刻蚀剂继续刻蚀至导电栓塞所需的深度。漏极由于被第三绝缘氧化层保护,因此不会被刻蚀。
S219,向第一沟槽内填入导电材料,形成导电栓塞。
在一个实施例中,步骤S219之后还包括形成层间介质(ILD)层的步骤,光刻并刻蚀层间介质层形成接触孔的步骤,以及向接触孔内填充金属钨形成钨塞的步骤,以将导电栓塞和漏极引出,后续通过金属互联层进行电连接。
以上所述实施例仅表达了本发明的几种实施方式,其描述较为具体和详细,但并不能因此而理解为对发明专利范围的限制。应当指出的是,对于本领域的普通技术人员来说,在不脱离本发明构思的前提下,还可以做出若干变形和改进,这些都属于本发明的保护范围。因此,本发明专利的保护范围应以所附权利要求为准。
Claims (13)
1.一种MOSFET结构,其特征在于,包括:
衬底;
第一导电类型阱区,设于所述衬底上;
至少一个第一沟槽,开设于所述第一导电类型阱区表面并向下延伸;
第二导电类型阱区,所述第一沟槽是向下延伸至所述第二导电类型阱区;
栅氧化层,设于所述第一沟槽的内表面;
多晶硅栅,位于所述栅氧化层内侧,填充于所述第一沟槽底部及侧壁的部分区域;
源极,具有第一导电类型,设于所述第二导电类型阱区内、所述多晶硅栅之间的第一沟槽下部;
导电栓塞,从所述第一沟槽的上方向下延伸,贯穿所述源极后与所述第二导电类型阱区接触;
绝缘氧化层,填充于所述第一沟槽内、所述导电栓塞与多晶硅栅之间,覆盖所述多晶硅栅,并将所述多晶硅栅与所述源极进行绝缘隔离;及
漏极,具有第一导电类型,设于所述第一沟槽外、所述源极的斜上方;
所述第一导电类型和第二导电类型为相反的导电类型。
2.根据权利要求1所述的MOSFET结构,其特征在于,所述漏极和所述第一沟槽之间还设有隔离结构。
3.根据权利要求1所述的MOSFET结构,其特征在于,还包括:
第二沟槽;
栅极引出结构,从所述第二沟槽底部向上堆积并从所述第二沟槽露出;
衬底引出,具有第二导电类型,所述衬底引出和所述第二沟槽之间设有隔离结构。
4.根据权利要求1所述的MOSFET结构,其特征在于,所述衬底具有第二导电类型,所述第二导电类型阱区设于所述第一导电类型阱区内,所述导电栓塞向下贯穿所述第二导电类型阱区后延伸至所述衬底。
5.根据权利要求1所述的MOSFET结构,其特征在于,所述导电栓塞的材质为金属,或所述导电栓塞的材质为合金,或所述导电栓塞的材质包括金属和金属氮化物。
6.根据权利要求1-5中任一项所述的MOSFET结构,其特征在于,所述第一导电类型是N型,所述第二导电类型是P型。
7.一种MOSFET结构的制造方法,包括:
步骤A,提供在衬底上形成有第一导电类型阱区的晶圆;
步骤B,在所述第一导电类型阱区表面开设向下延伸的第一沟槽;
步骤C,在所述第一沟槽的内表面形成栅氧化层;
步骤D,向所述第一沟槽内填充多晶硅,将所述第一沟槽填满;
步骤E,刻蚀所述多晶硅至预定厚度,在所述第一沟槽底部形成该预定厚度的多晶硅层;
步骤F,在所述多晶硅层的表面和所述第一沟槽的侧壁形成第一绝缘氧化层;
步骤G,向下刻蚀所述第一绝缘氧化层和多晶硅层,使所述第一沟槽的底部露出,所述侧壁的多晶硅层和第一绝缘氧化层被保留;
步骤H,在所述第一沟槽的下方形成第二导电类型阱区,在所述第二导电类型阱区内形成第一导电类型的源极;
步骤I,在所述第一沟槽内形成第二绝缘氧化层,将所述多晶硅层与所述源极进行绝缘隔离;及
步骤J,在所述第一沟槽外、所述源极的斜上方注入第一导电类型的离子,形成漏极,并刻蚀所述第一沟槽底部的第二绝缘氧化层,将所述第二导电类型阱区和源极露出,向所述第一沟槽内填入导电材料、形成贯穿所述源极与所述第二导电类型阱区接触的导电栓塞;
所述第一导电类型和第二导电类型为相反的导电类型。
8.根据权利要求7所述的制造方法,其特征在于,所述步骤A提供的晶圆还形成有隔离结构;所述步骤B是光刻后刻蚀部分所述隔离结构,将所述隔离结构刻穿后,以被所述光刻胶保护而未被刻蚀的隔离结构为硬掩膜,继续向下刻蚀所述第一导电类型阱区形成所述第一沟槽。
9.根据权利要求7所述的制造方法,其特征在于,
所述步骤B还包括同时开设第二沟槽;
所述步骤C还包括同时在所述第二沟槽的内表面形成栅氧化层;
所述步骤D还包括将所述第二沟槽也填满多晶硅;
所述步骤E是光刻后进行刻蚀,光刻形成的光刻胶至少部分遮挡所述第二沟槽内的多晶硅,从而在刻蚀后形成露出所述第二沟槽的栅极引出结构。
10.根据权利要求7所述的制造方法,其特征在于,所述步骤G之后、所述在步骤I之前,还包括通过注入第二导电类型的离子,在所述第二导电类型阱区内、所述源极下方形成第二导电类型掺杂区的步骤。
11.根据权利要求7所述的制造方法,其特征在于,所述步骤J具体包括:
向所述第一沟槽内填入绝缘氧化材料;
光刻并注入第一导电类型的离子,在所述第一沟槽外、所述源极的斜上方形成所述漏极;
去胶后再次光刻,光刻胶在需要形成所述导电栓塞的位置露出刻蚀窗口;
通过所述刻蚀窗口向下刻蚀至所述导电栓塞所需的深度;
向所述第一沟槽内填入导电材料,形成所述导电栓塞。
12.根据权利要求11所述的制造方法,其特征在于,
所述去胶后再次光刻的步骤,是去胶后在所述漏极的表面形成第三绝缘氧化层,然后再次光刻;
所述通过所述刻蚀窗口向下刻蚀至所述导电栓塞所需的深度的步骤,是采用第一刻蚀剂,通过所述刻蚀窗口向下刻蚀至所述第一沟槽底部,然后去胶,以所述第三绝缘氧化层为刻蚀掩膜、采用第二刻蚀剂继续刻蚀至所述导电栓塞所需的深度。
13.根据权利要求7所述的制造方法,其特征在于,所述衬底具有第二导电类型;所述步骤H中,控制第二导电类型的离子的注入深度使得所述第二导电类型阱区形成于所述第一导电类型阱区内;所述步骤J中,所述导电栓塞向下贯穿所述第二导电类型阱区后延伸至所述衬底。
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WO2021238197A1 (zh) * | 2020-05-29 | 2021-12-02 | 无锡华润上华科技有限公司 | 具有引出结构的沟槽侧壁栅极及其制造方法 |
WO2023092947A1 (zh) * | 2021-11-25 | 2023-06-01 | 无锡华润上华科技有限公司 | 自对准孔的制备方法及半导体器件 |
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