CN109815625A - A kind of method of high precision computation phaselocked loop in-band phase noise - Google Patents
A kind of method of high precision computation phaselocked loop in-band phase noise Download PDFInfo
- Publication number
- CN109815625A CN109815625A CN201910129688.6A CN201910129688A CN109815625A CN 109815625 A CN109815625 A CN 109815625A CN 201910129688 A CN201910129688 A CN 201910129688A CN 109815625 A CN109815625 A CN 109815625A
- Authority
- CN
- China
- Prior art keywords
- phaselocked loop
- output
- phase
- phase noise
- noise
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
Abstract
The invention discloses a kind of method of high precision computation phaselocked loop in-band phase noise comprising steps of S1, emulating to phase frequency detector and charge pump circuit, the current noise P of circuit is obtainedNOUT；The output amplitude virtual value V of S2, simulated oscillator coreRMS；S3, the current noise P according to acquisitionNOUTWith output amplitude virtual value VRMSCalculate phase frequency detector and the equivalent phase noise PN to phaselocked loop output of charge pumpCP；S4, the equivalent phase noise PN to phaselocked loop output of reference clock is calculatedREF；S5, the in-band phase noise PN for calculating phaselocked loop entiretyTotal.The calculating phase noise method that the present invention uses is easily operated, can be fitted the in-band phase noise of phaselocked loop with high precision, provides whole simulation result for the design of phaselocked loop, is conducive to the iteration and optimization of Design of PLL.
Description
Technical field
The invention belongs to phases in radio-frequency system phaselocked loop field more particularly to a kind of high precision computation phase-locked loop
The method of noise.
Background technique
It is also more and more specific to the phase noise requirements of frequency synthesizer recently as the development of transceiver communication technology
Change.Phaselocked loop is made of as one kind important in frequency synthesizer, phase noise the noise of multiple modules.Grasp each mould
The phase noise calculation method of block, synthesizes the phase noise of entire phaselocked loop, this design and transceiver for phaselocked loop
The whole design of index is crucial.Since the module of phaselocked loop is more, and the phase noise of each module is different
Different noise results can be obtained under simulated environment, therefore, be badly in need of a kind of method of high precision computation phaselocked loop phase noise.
Summary of the invention
It is an object of that present invention to provide a kind of methods of high precision computation phaselocked loop in-band phase noise, solve traditional imitate
True calculation method has ignored the lower problem of the phase noise of important module, precision.
A kind of method of high precision computation phaselocked loop in-band phase noise, specific steps are as follows:
S1, phase frequency detector and charge pump circuit are emulated, obtains the current noise P of circuitNOUT；
The output amplitude virtual value V of S2, simulated oscillator coreRMS；
S3, the current noise P according to acquisitionNOUTWith output amplitude virtual value VRMSCalculate phase frequency detector and charge pump etc.
Imitate the phase noise PN of phaselocked loop outputCP；
S4, the equivalent phase noise PN to phaselocked loop output of reference clock is calculatedREF；
S5, the in-band phase noise PN for calculating phaselocked loop entiretyTotal。
Further, it in step S1, emulates phase frequency detector and charge pump circuit includes: phase frequency detector PFD, charge pump
CP, input signal source, feedback signal source and output voltage source.
Further, what the input signal source and the feedback signal source exported is all square-wave signal, and two signals are the same as frequency
Same phase, the output signal of the PFD are connected with the input signal of the CP, and the output of CP connects output voltage source, the output
Voltage source is an ideal voltage source.
Further, the current noise PNOUTFrom in the simulation result of the phase frequency detector and charge pump artificial circuit
It reads and obtains.
Further, oscillator core artificial circuit figure includes oscillator core VCO in the step S2, exports buffer stage
BUF。
Further, the difference output of the VCO is connected to the Differential Input of BUF.
Further, the output amplitude of the VCO is detected at the Differential Input of the BUF, and it is effective to calculate output amplitude
Value VRMS。
Further, phase frequency detector and the equivalent phase noise to phaselocked loop output of charge pump are calculated in the step S3
PNCPFormula are as follows:Wherein N is the frequency dividing ratio of phaselocked loop, and I is the charging and discharging currents of charge pump.
Further, the equivalent phase noise PN to phaselocked loop output of reference clock is calculated in the step S4REFIt uses
Formula are as follows: PNREF=N*PNref, wherein N is the frequency dividing ratio of phaselocked loop, PNrefFor the phase noise of reference clock.
Further, the in-band phase noise PN of phaselocked loop entirety is calculated in the step S5TotalThe formula of use are as follows:
PNTotal=PNCP+PNREF。
The calculating phase noise method that the present invention uses error compared with test result is small, easily operated, can be with high precision
It is fitted the in-band phase noise of phaselocked loop, provides whole simulation result for the design of phaselocked loop, is conducive to changing for Design of PLL
Generation and optimization.
Detailed description of the invention
The flow chart of the method for Fig. 1 high precision computation phaselocked loop in-band phase noise of the present invention；
Fig. 2 embodiment of the present invention phase frequency detector and charge pump artificial circuit schematic diagram；
Fig. 3 embodiment of the present invention phase frequency detector and charge pump current noise Simulation result；
Fig. 4 oscillator core artificial circuit schematic diagram of the embodiment of the present invention.
Specific embodiment
Technical solution of the present invention is clearly and completely described below in conjunction with attached drawing, it is clear that described implementation
Example is a part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, ordinary skill
Personnel's every other embodiment obtained without making creative work, shall fall within the protection scope of the present invention.
A kind of method of high precision computation phaselocked loop in-band phase noise of the present invention, as shown in Figure 1, specifically including step:
S1, phase frequency detector and charge pump circuit are emulated, obtains the current noise PN of circuitOUT。
It emulates phase frequency detector and charge pump circuit schematic diagram is as shown in Figure 2, comprising: phase frequency detector PFD, charge pump
CP, input signal source, feedback signal source and output voltage source.
What the input signal source and the feedback signal source exported is all square-wave signal, and two signals are described with the same phase of frequency
The output signal of PFD is connected with the input signal of the CP, and the output of CP connects output voltage source, and the output voltage source is one
Ideal voltage source.
The current noise PNOUTIt is obtained from being read in the simulation result of the phase frequency detector and charge pump artificial circuit.
The simulation result of phase frequency detector and charge pump current noise Simulation circuit is directly analyzed by circuit diagram and carries out noise analysis
Available, output noise curve is related with deviation frequency, and the frequency point data of needs is directly read in figure, such as Fig. 3 institute
Show, the electric current output noise at 10KHz is -210.3dB.
The output amplitude virtual value V of S2, simulated oscillator coreRMS。
Oscillator core artificial circuit figure is as shown in figure 4, include oscillator core VCO, output buffer stage BUF.The difference of VCO
The Differential Input for dividing output to be connected to BUF, detects the output amplitude of the VCO, i.e., in Fig. 4 at the Differential Input of the BUF
Middle Poutl point detects VCO output amplitude, rather than in Pout2 point.Finally calculate output amplitude virtual value VRMS。
S3, the current noise P according to acquisitionNOUTWith output amplitude virtual value VRMSCalculate phase frequency detector and charge pump etc.
Imitate the phase noise PN of phaselocked loop outputCP。
On the basis of first two steps, following formula is utilized:
Phase frequency detector and the equivalent phase noise PN to phaselocked loop output of charge pump can be obtainedCP, wherein N is locking phase
The frequency dividing ratio of ring, I are the charging and discharging currents of charge pump.
S4, the equivalent phase noise PN to phaselocked loop output of reference clock is calculatedREF。
The equivalent phase noise PN to phaselocked loop output of reference clockREFIt is calculated by following formula: PNREF=N*PNref,
Wherein, N is the frequency dividing ratio of phaselocked loop, PNrefFor the phase noise of reference clock, value by searching for crystal oscillator databook or
Person is tested available with frequency spectrograph.
S5, the in-band phase noise PN for calculating phaselocked loop entiretyTotal。
Total phase noise PNTotalIt is obtained by following formula: PNTotal=PNCP+PNREF。
Obviously, the above embodiments are merely examples for clarifying the description, rather than the restriction to embodiment.For
For person of an ordinary skill in the technical field, other various forms of variations can also be made on the basis of the above description
Or it changes.There is no necessity and possibility to exhaust all the enbodiments.And obvious variation extended from this
Or it changes and still falls among the protection scope of the invention.
Claims (10)
1. a kind of method of high precision computation phaselocked loop in-band phase noise, which is characterized in that comprising steps of
S1, phase frequency detector and charge pump circuit are emulated, obtains the current noise P of circuitNOUT；
The output amplitude virtual value V of S2, simulated oscillator coreRMS；
S3, the current noise P according to acquisitionNOUTWith output amplitude virtual value VRMSIt calculates phase frequency detector and charge pump is equivalent to lock
The phase noise PN of phase ring outputCP；
S4, the equivalent phase noise PN to phaselocked loop output of reference clock is calculatedREF；
S5, the in-band phase noise PN for calculating phaselocked loop entiretyTotal。
2. the method as described in claim 1, which is characterized in that in the step S1, emulate phase frequency detector and charge pump electricity
Road includes: phase frequency detector PFD, charge pump CP, input signal source, feedback signal source and output voltage source.
3. method according to claim 2, which is characterized in that the input signal source and feedback signal source output are all
It is square-wave signal, two signals are connected with the same phase of frequency, the output signal of the PFD with the input signal of the CP, and the output of CP connects
Output voltage source is connect, the output voltage source is an ideal voltage source.
4. method as claimed in claim 3, which is characterized in that the current noise PNOUTFrom the phase frequency detector and charge
It pumps to read in the simulation result of artificial circuit and obtain.
5. the method as described in claim 1, which is characterized in that oscillator core artificial circuit figure includes vibration in the step S2
Device core VCO is swung, buffer stage BUF is exported.
6. method as claimed in claim 5, which is characterized in that the difference output of the VCO is connected to the Differential Input of BUF.
7. method as claimed in claim 6, which is characterized in that detect the output of the VCO at the Differential Input of the BUF
Amplitude calculates output amplitude virtual value VRMS。
8. the method as described in claim 1, which is characterized in that calculate phase frequency detector in the step S3 and charge pump is equivalent
The phase noise PN exported to phaselocked loopCPFormula are as follows:
Wherein N is the frequency dividing ratio of phaselocked loop, and I is the charging and discharging currents of charge pump.
9. the method as described in claim 1, which is characterized in that it is equivalent defeated to phaselocked loop to calculate reference clock in the step S4
Phase noise PN outREFThe formula of use are as follows:
PNREF=N*PNref, wherein N is the frequency dividing ratio of phaselocked loop, PNrefFor the phase noise of reference clock.
10. the method as described in claim 1, which is characterized in that calculate making an uproar with interior phase for phaselocked loop entirety in the step S5
Sound PNTotalThe formula of use are as follows:
PNTotal=PNCP+PNREF。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910129688.6A CN109815625B (en) | 2019-02-21 | 2019-02-21 | Method for calculating phase noise in phase-locked loop band with high precision |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201910129688.6A CN109815625B (en) | 2019-02-21 | 2019-02-21 | Method for calculating phase noise in phase-locked loop band with high precision |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109815625A true CN109815625A (en) | 2019-05-28 |
| CN109815625B CN109815625B (en) | 2022-11-22 |
Family
ID=66607138
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201910129688.6A Active CN109815625B (en) | 2019-02-21 | 2019-02-21 | Method for calculating phase noise in phase-locked loop band with high precision |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109815625B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113644932A (en) * | 2021-08-17 | 2021-11-12 | 江苏星宇芯联电子科技有限公司 | Big dipper No. three RDSS system transmission link filter bandwidth automatic switching circuit |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102263554A (en) * | 2010-05-26 | 2011-11-30 | 中国科学院微电子研究所 | Phase-locked loop frequency synthesizer structure for improving in-band phase noise performance |
| US8102196B1 (en) * | 2008-06-27 | 2012-01-24 | National Semiconductor Corporation | Programmable dual phase-locked loop clock signal generator and conditioner |
| CN102684686A (en) * | 2012-05-09 | 2012-09-19 | 上海宏力半导体制造有限公司 | Phase-locked loop with reduced in-band phase noise and corresponding working method thereof |
| CN105871372A (en) * | 2016-03-24 | 2016-08-17 | 中国电子科技集团公司第二十四研究所 | Downsampling phase locked loop for preventing in-band noise from being amplified to square times of frequency dividing ratio |
| CN107110902A (en) * | 2014-12-31 | 2017-08-29 | 德克萨斯仪器股份有限公司 | Frequency synthesizer noise it is spuious or it is phase noise dynamic measurement |
-
2019
- 2019-02-21 CN CN201910129688.6A patent/CN109815625B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8102196B1 (en) * | 2008-06-27 | 2012-01-24 | National Semiconductor Corporation | Programmable dual phase-locked loop clock signal generator and conditioner |
| CN102263554A (en) * | 2010-05-26 | 2011-11-30 | 中国科学院微电子研究所 | Phase-locked loop frequency synthesizer structure for improving in-band phase noise performance |
| CN102684686A (en) * | 2012-05-09 | 2012-09-19 | 上海宏力半导体制造有限公司 | Phase-locked loop with reduced in-band phase noise and corresponding working method thereof |
| CN107110902A (en) * | 2014-12-31 | 2017-08-29 | 德克萨斯仪器股份有限公司 | Frequency synthesizer noise it is spuious or it is phase noise dynamic measurement |
| CN105871372A (en) * | 2016-03-24 | 2016-08-17 | 中国电子科技集团公司第二十四研究所 | Downsampling phase locked loop for preventing in-band noise from being amplified to square times of frequency dividing ratio |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113644932A (en) * | 2021-08-17 | 2021-11-12 | 江苏星宇芯联电子科技有限公司 | Big dipper No. three RDSS system transmission link filter bandwidth automatic switching circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109815625B (en) | 2022-11-22 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Jaalam et al. | A comprehensive review of synchronization methods for grid-connected converters of renewable energy source | |
| Xiong et al. | A novel PLL for grid synchronization of power electronic converters in unbalanced and variable-frequency environment | |
| CN203014748U (en) | Micromechanical gyroscope closed-loop driving automatic gain control circuit | |
| CN107707253B (en) | Self-detection common time base circuit, system and method based on arbitrary variable reference source | |
| CN103338041B (en) | Synchronized sampling clock generating method and power quality analyzer | |
| CN101714875B (en) | Phase-locked loop circuit | |
| CN104267244A (en) | Integral proportion circuit and impedance measurement method based on integral proportion circuit | |
| CN109815625A (en) | A kind of method of high precision computation phaselocked loop in-band phase noise | |
| Nothaft et al. | Pragma-based floating-to-fixed point conversion for the emulation of analog behavioral models | |
| CN110768666B (en) | Kalman filter-based phase-locked loop system and method for decoupling double synchronous coordinate systems | |
| CN106911144A (en) | Photovoltaic inverter control system and method based on modelling exploitation | |
| CN109918735A (en) | A kind of searching method of circuit-level single particle effect Path-sensitive | |
| CN110470291A (en) | A kind of MEMS resonant formula gyroscope interface circuit and TT&C system | |
| CN104569786A (en) | Embedded test method of phase-locked loop circuits | |
| CN201251611Y (en) | High-frequency parameter measuring equipment of high-precision electric wave trapper | |
| Wang et al. | Event driven analog modeling for the verification of PLL frequency synthesizers | |
| CN110266036A (en) | A kind of dimension reduction method of current transformer multidimensional frequency domain impedance | |
| CN105044465A (en) | Automatic balance bridge based on synchronous clock DDS and method for measuring impedance of DUT (Device Under Test) | |
| CN103425810A (en) | Behavioral modeling methods for clock and data recovery circuit and analog circuits | |
| CN106873352B (en) | Pulse integration ball atomic clock system | |
| CN202285032U (en) | Electronic transformer harmonic influence testing device | |
| CN112487753B (en) | Clock tree modeling method oriented to software development | |
| CN210198392U (en) | Novel MEMS resonant gyroscope measurement and control device | |
| Chen et al. | Z-domain model procedure for heterodyne digital optical phase-locked loop | |
| Tan et al. | Model linearization analysis for three-phase unbalanced phase-locked loop techniques |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |