CN109815625B - Method for calculating phase noise in phase-locked loop band with high precision - Google Patents
Method for calculating phase noise in phase-locked loop band with high precision Download PDFInfo
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Abstract
The invention discloses a high-precisionThe method for calculating the phase noise in the phase-locked loop zone comprises the following steps: s1, simulating a phase frequency detector and a charge pump circuit to obtain current noise P of the circuit NOUT (ii) a S2, the effective value V of the output amplitude of the core of the simulation oscillator RMS (ii) a S3, according to the obtained current noise P NOUT And the effective value V of the output amplitude RMS Calculating phase noise PN from phase frequency detector and charge pump equivalent to phase-locked loop output CP (ii) a S4, calculating phase noise PN equivalent to phase-locked loop output by reference clock REF (ii) a S5, calculating the integral in-band phase noise PN of the phase-locked loop Total . The method for calculating the phase noise is easy to operate, can fit the in-band phase noise of the phase-locked loop with high precision, provides an integral simulation result for the design of the phase-locked loop, and is favorable for iteration and optimization of the design of the phase-locked loop.
Description
Technical Field
The invention belongs to the field of phase-locked loops of radio frequency transceiving systems, and particularly relates to a method for calculating phase noise in a phase-locked loop with high precision.
Background
In recent years, with the development of communication transceiving technology, the phase noise requirement of the frequency synthesizer is more and more embodied. A phase locked loop, whose phase noise is composed of noise of a plurality of blocks, is an important one in a frequency synthesizer. The phase noise calculation method of each module is mastered, and the phase noise of the whole phase-locked loop is synthesized, which is very important for the design of the phase-locked loop and the whole design of the index of the transceiver. Because the number of modules of the phase-locked loop is large, and the phase noise of each module can obtain different noise results under different simulation environments, a method for calculating the phase noise of the phase-locked loop with high precision is urgently needed.
Disclosure of Invention
The invention aims to provide a method for calculating phase noise in a phase-locked loop with high precision, and solves the problems that the phase noise of an important module is neglected and the precision is low in the traditional simulation calculation method.
A method for calculating phase noise in a phase-locked loop with high precision comprises the following specific steps:
s1, simulating a phase frequency detector and a charge pump circuit to obtain current noise P of the circuit NOUT ；
S2, the effective value V of the output amplitude of the core of the simulation oscillator RMS ；
S3, according to the obtained current noise P NOUT And the effective value V of the output amplitude RMS Calculating phase noise PN from phase frequency detector and charge pump equivalent to phase-locked loop output CP ；
S4, calculating phase noise PN equivalent to phase-locked loop output by reference clock REF ；
S5, calculating the integral in-band phase noise PN of the phase-locked loop Total 。
Further, in step S1, the simulated phase frequency detector and the charge pump circuit include: the phase frequency detector PFD, the charge pump CP, the input signal source, the feedback signal source and the output voltage source.
Further, the output of the input signal source and the output of the feedback signal source are both square wave signals, the two signals have the same frequency and phase, the output signal of the PFD is connected with the input signal of the CP, the output of the CP is connected with an output voltage source, and the output voltage source is an ideal voltage source.
Further, the current noise P NOUT And reading the simulation result of the phase frequency detector and the charge pump simulation circuit.
Further, the oscillator core simulation circuit diagram in the step S2 includes an oscillator core VCO and an output buffer stage BUF.
Further, the differential output of the VCO is connected to the differential input of the BUF.
Further, the output amplitude of the VCO is detected at the differential input of the BUF, and an output amplitude effective value V is calculated RMS 。
Further, the phase noise PN from the phase frequency detector and the charge pump equivalent to the output of the phase-locked loop is calculated in the step S3 CP The formula of (1) is:
n is the frequency dividing ratio of the phase-locked loop, and I is the charge and discharge current of the charge pump.
Further, the phase noise PN equivalent to the phase-locked loop output of the reference clock is calculated in the step S4 REF The formula adopted is as follows: PN (pseudo-noise) REF ＝N*PN ref Where N is the frequency division ratio of the phase-locked loop, PN ref Is the phase noise of the reference clock.
Further, the in-band phase noise PN of the whole phase-locked loop is calculated in the step S5 Total The formula adopted is as follows: PN (pseudo-noise) Total ＝PN CP +PN REF 。
Compared with a test result, the method for calculating the phase noise has small error and easy operation, can fit the in-band phase noise of the phase-locked loop with high precision, provides an integral simulation result for the design of the phase-locked loop, and is favorable for iteration and optimization of the design of the phase-locked loop.
Drawings
FIG. 1 is a flow chart of a method of the present invention for calculating phase noise in a phase locked loop with high accuracy;
FIG. 2 is a schematic diagram of a phase frequency detector and charge pump simulation circuit according to an embodiment of the present invention;
FIG. 3 shows simulation results of current noise of the phase frequency detector and the charge pump according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of an oscillator core simulation circuit according to an embodiment of the present invention.
Detailed Description
The technical solutions of the present invention will be described clearly and completely with reference to the accompanying drawings, and it should be understood that the described embodiments are some, but not all embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention discloses a method for calculating phase noise in a phase-locked loop with high precision, which specifically comprises the following steps as shown in figure 1:
s1, simulating a phase frequency detector and a charge pump circuit to obtain the current of the circuitNoise PN OUT 。
The schematic diagram of the simulated phase frequency detector and the charge pump circuit is shown in fig. 2, and includes: the phase frequency detector PFD, the charge pump CP, the input signal source, the feedback signal source and the output voltage source.
The output of the input signal source and the output of the feedback signal source are both square wave signals, the two signals have the same frequency and phase, the output signal of the PFD is connected with the input signal of the CP, the output of the CP is connected with an output voltage source, and the output voltage source is an ideal voltage source.
The current noise P NOUT And reading the simulation result of the phase frequency detector and the charge pump simulation circuit. The simulation results of the phase frequency detector and the charge pump current noise simulation circuit can be obtained by directly analyzing and carrying out noise analysis on the circuit schematic diagram, the output noise curve is related to the offset frequency, the required frequency point data can be directly read in the diagram, as shown in figure 3, the current output noise at 10KHz is-210.3 dB.
S2, the effective value V of the output amplitude of the core of the simulation oscillator RMS 。
The simulation circuit diagram of the oscillator core is shown in fig. 4 and comprises an oscillator core VCO and an output buffer stage BUF. The differential output of the VCO is connected to the differential input of the BUF, where the output amplitude of the VCO is detected, i.e. the VCO output amplitude is detected at point Poutl in fig. 4, instead of at point Pout 2. Finally calculating the effective value V of the output amplitude RMS 。
S3, according to the obtained current noise P NOUT And outputting the effective value V of the amplitude RMS Calculating phase noise PN from phase frequency detector and charge pump equivalent to phase-locked loop output CP 。
On the basis of the first two steps, the following formula is utilized:
the phase noise PN equivalent to the phase-locked loop output by the phase frequency detector and the charge pump can be obtained CP Wherein N is a fraction of the phase-locked loopAnd the frequency ratio I is the charge and discharge current of the charge pump.
S4, calculating phase noise PN equivalent to phase-locked loop output by reference clock REF 。
Phase noise PN equivalent to phase-locked loop output by reference clock REF Calculated by the following formula: PN (pseudo-noise) REF ＝N*PN ref Where N is the frequency dividing ratio of the phase-locked loop, PN ref The phase noise of the reference clock is obtained by looking up a data book of the crystal oscillator or by testing with a spectrometer.
S5, calculating the integral in-band phase noise PN of the phase-locked loop Total 。
Total phase noise PN Total The following formula is obtained: PN (pseudo-noise) Total ＝PN CP +PN REF 。
It is to be understood that the above examples are illustrative only for the purpose of clarity of description and are not intended to limit the embodiments. Other variations and modifications will be apparent to persons skilled in the art upon reference to the above description. And are neither required nor exhaustive of all embodiments. And obvious variations or modifications therefrom are intended to be within the scope of the invention.
Claims (1)
1. A method for calculating phase noise in a phase-locked loop with high precision, comprising the steps of:
s1, simulating a phase frequency detector and a charge pump circuit to obtain current noise P of the circuit NOUT ；
S2, the effective value V of the output amplitude of the core of the simulation oscillator RMS ；
S3, according to the obtained current noise P NOUT And outputting the effective value V of the amplitude RMS Calculating phase noise PN from phase frequency detector and charge pump equivalent to phase-locked loop output CP ；
S4, calculating phase noise PN equivalent to phase-locked loop output by reference clock REF ；
S5, calculating the integral in-band phase noise PN of the phase-locked loop Total ；
In step S1, the simulation phase frequency detector and the charge pump circuit include: the phase frequency detector PFD, the charge pump CP, the input signal source, the feedback signal source and the output voltage source;
the output of the input signal source and the output of the feedback signal source are both square wave signals, the two signals have the same frequency and phase, the output signal of the PFD is connected with the input signal of the CP, the output of the CP is connected with an output voltage source, and the output voltage source is an ideal voltage source;
the current noise P NOUT Reading the simulation result of the phase frequency detector and the charge pump simulation circuit;
the oscillator core simulation circuit diagram in the step S2 comprises an oscillator core VCO and an output buffer stage BUF;
the differential output of the VCO is connected to the differential input of the BUF;
detecting the output amplitude of the VCO at the differential input of the BUF, calculating an output amplitude effective value V RMS ；
And in the step S3, phase noise PN equivalent to the output of the phase-locked loop from the phase frequency detector and the charge pump is calculated CP The formula of (1) is as follows:
calculating phase noise PN equivalent to phase-locked loop output by the reference clock in the step S4 REF The formula adopted is as follows:
PN REF ＝N*PN ref wherein, PN ref Phase noise of a reference clock;
calculating the integral in-band phase noise PN of the phase-locked loop in the step S5 Total The formula adopted is as follows:
PN Total ＝PN CP +PN REF 。
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| CN102263554A (en) * | 2010-05-26 | 2011-11-30 | 中国科学院微电子研究所 | Phase-locked loop frequency synthesizer structure for improving in-band phase noise performance |
| US8102196B1 (en) * | 2008-06-27 | 2012-01-24 | National Semiconductor Corporation | Programmable dual phase-locked loop clock signal generator and conditioner |
| CN102684686A (en) * | 2012-05-09 | 2012-09-19 | 上海宏力半导体制造有限公司 | Phase-locked loop with reduced in-band phase noise and corresponding working method thereof |
| CN105871372A (en) * | 2016-03-24 | 2016-08-17 | 中国电子科技集团公司第二十四研究所 | Downsampling phase locked loop for preventing in-band noise from being amplified to square times of frequency dividing ratio |
| CN107110902A (en) * | 2014-12-31 | 2017-08-29 | 德克萨斯仪器股份有限公司 | Frequency synthesizer noise it is spuious or it is phase noise dynamic measurement |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US8102196B1 (en) * | 2008-06-27 | 2012-01-24 | National Semiconductor Corporation | Programmable dual phase-locked loop clock signal generator and conditioner |
| CN102263554A (en) * | 2010-05-26 | 2011-11-30 | 中国科学院微电子研究所 | Phase-locked loop frequency synthesizer structure for improving in-band phase noise performance |
| CN102684686A (en) * | 2012-05-09 | 2012-09-19 | 上海宏力半导体制造有限公司 | Phase-locked loop with reduced in-band phase noise and corresponding working method thereof |
| CN107110902A (en) * | 2014-12-31 | 2017-08-29 | 德克萨斯仪器股份有限公司 | Frequency synthesizer noise it is spuious or it is phase noise dynamic measurement |
| CN105871372A (en) * | 2016-03-24 | 2016-08-17 | 中国电子科技集团公司第二十四研究所 | Downsampling phase locked loop for preventing in-band noise from being amplified to square times of frequency dividing ratio |
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