CN109782573B - Electronic clock generating device and chip - Google Patents
Electronic clock generating device and chip Download PDFInfo
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- CN109782573B CN109782573B CN201711117817.7A CN201711117817A CN109782573B CN 109782573 B CN109782573 B CN 109782573B CN 201711117817 A CN201711117817 A CN 201711117817A CN 109782573 B CN109782573 B CN 109782573B
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Abstract
The invention provides an electronic clock generating device and a chip, wherein the electronic clock generating device comprises: the voltage reference source is used for charging the first energy storage element in a first period; the voltage stabilizing element is used for acquiring the electric energy in the first energy storage element in a second time interval and supplying power to the first resistor at a preset voltage in the first time interval and the second time interval; the current output circuit is configured to output a first current to the second resistor such that: the voltage of the first end of the second resistor is the preset voltage; and outputting a second current to the second energy storage element; the clock output circuit is used for comparing the voltage of the second energy storage element with the reference voltage of the voltage reference source; and outputting a first level signal and a second level signal, wherein the first level signal and the second level signal form a clock signal. The invention reduces the influence of the production process and the working environment on the output clock signal.
Description
Technical Field
The invention relates to the field of electronic clock design, in particular to an electronic clock generating device and a chip.
Background
In the art, circuits in electronic systems require clocks for timing operations, such as digital timing circuits, digital/analog hybrids, and the like. The required clock frequencies in different circuits often differ, and for synchronous operation, these different clocks are required to be provided by the same clock source.
In the related art, clock signals with different clock frequencies can be obtained by increasing or decreasing the frequency of the same clock source and then used by each circuit module, or a high-precision clock generator can be used to generate clock signals with the clock frequencies required by each circuit module. For example, the patent name clock generation circuit of application No. 201110251385.5 includes a voltage controlled oscillator, an integer divider, and a phase detector. The clock generated by the voltage-controlled oscillator is compared with a reference clock by using a phase discriminator after passing through a frequency divider, the compared difference value is sent to the voltage-controlled oscillator, and the voltage-controlled oscillator adjusts the clock output according to the difference value until the difference value is zero; however, the scheme is a phase-locked loop scheme, has high hardware overhead, cannot realize non-integer frequency division, and can change along with the change of a production process and a working environment. For another example, in application No. 2012103672745.3, the patent name "variable synchronous clock frequency dividing circuit" performs an operation of adding 1 to a timer at each rising edge of a clock reference source, and when an accumulated value of the timer reaches a set value N, an output clock is inverted to achieve a frequency dividing function, and a frequency dividing ratio is 2N; however, this scheme can only implement integer frequency division, but cannot implement non-integer frequency division, and if a larger frequency division ratio is to be implemented, the number of frequency dividers needs to be increased to increase hardware overhead, and frequency multiplication cannot be implemented. However, clock sources are susceptible to manufacturing processes and/or operating environments. For example, as the process batch, temperature, voltage, etc. environment changes, the clock source generated may change. Although integer division of the time base can be realized by a counter, the hardware overhead of this approach increases proportionally with increasing division ratio; in some systems, non-integer frequency division needs to be carried out on a clock, although the non-integer frequency division can be completed in a feedback loop through a phase-locked loop at present, the hardware overhead of the phase-locked loop is large and the phase-locked loop is easily influenced by a non-ideal environment; the same problems of hardware overhead and irrational environmental impact are faced if the oscillator is used directly to generate a required clock. If the frequency raising is to be realized, a phase-locked loop is usually required to realize the frequency raising, but the technical defects that the hardware cost is large and the influence of non-ideal environment is easily caused are caused.
Disclosure of Invention
The invention provides an electronic clock generating device and a chip, which aim to solve the problem that a generated clock source is easily influenced by a production process and/or a working environment.
According to a first aspect of the present invention, there is provided an electronic clock generating apparatus for obtaining a clock signal from a clock reference source, comprising: the voltage stabilizing circuit comprises a voltage reference source, a first energy storage element, a second energy storage element, a first resistor, a second resistor, a voltage stabilizing element, a current output circuit, a clock output circuit, a first switch, a second switch, a third switch and a fourth switch; wherein the first switch and the second switch are on or off simultaneously, and the third switch and the fourth switch are on or off simultaneously;
the voltage reference source is connected with the clock output circuit, the first end of the second resistor and the first end of the second energy storage element are both connected with the current output circuit, and the clock output circuit is also connected with the first end of the second energy storage element;
the first end of the first switch is connected with the first end of the first energy storage element, and the second end of the first switch is respectively connected with the first end of the first resistor and the first end of the voltage stabilizing element; the first end of the second switch is connected with the second end of the first energy storage element, and the second end of the second switch is connected with the first end of the second resistor; the first end of the third switch is connected with the first end of the first energy storage element, and the second end of the third switch is connected with the voltage reference source; the first end of the fourth switch is connected with the second end of the first energy storage element, and the second end of the fourth switch is connected with the ground; the first switch, the second switch, the third switch and the fourth switch are all connected with the clock reference source;
the clock reference source is used for controlling the first switch and the second switch to be closed and the third switch and the fourth switch to be opened in a first period; controlling the first switch and the second switch to be open and the third switch and the fourth switch to be closed in a second period; wherein the first time interval and the second time interval are two adjacent time intervals, and one first time interval and one adjacent second time interval form one reference cycle of the clock reference source;
the voltage reference source is used for charging the first energy storage element in the first period;
the voltage stabilizing element is used for acquiring the electric energy in the first energy storage element in the second time interval and supplying power to the first resistor at a preset voltage in the first time interval and the second time interval;
the current output circuit is configured to output a first current to the second resistor such that: the voltage of the first end of the second resistor is the preset voltage; and outputting a second current to the second energy storage element; wherein the first current is proportional to the second current;
the clock output circuit is used for comparing the voltage of the second energy storage element with the reference voltage output by the voltage reference source; when the voltage of the second energy storage element is greater than the reference voltage, outputting a first level signal and controlling the second energy storage element to discharge; when the voltage of the second energy storage element is smaller than the reference voltage, outputting a second level signal and controlling the second energy storage element to be charged through the second current; wherein the first level signal and the second level signal constitute the clock signal.
Optionally, the current output circuit includes an operational amplifier and an output sub-circuit, a first input terminal of the operational amplifier is connected to the first terminal of the voltage stabilizing element, a second input terminal of the operational amplifier is connected to the first terminal of the second resistor, and an output terminal of the operational amplifier is connected to the output sub-circuit; the output sub-circuit is respectively connected with the first end of the second resistor and the first end of the second energy storage element;
the operational amplifier is used for controlling the output sub-circuit to output the first current to the second resistor and controlling the output sub-circuit to output the second current to the second energy storage element.
Optionally, the output sub-circuit includes a first MOS transistor and a second MOS transistor, the first MOS transistor and the gate of the second MOS transistor are both connected to the output end of the operational amplifier, the drain of the first MOS transistor is connected to the first end of the second resistor, the drain of the second MOS transistor is connected to the first end of the second energy storage element, and the source of the first MOS transistor and the source of the second MOS transistor are both connected to the power supply.
Optionally, the first MOS transistor and the second MOS transistor are both PMOS transistors.
Optionally, the clock output circuit includes a comparator and a charge-discharge electronic circuit, a first input end of the comparator is connected to the first end of the second energy storage element, a second input end of the comparator is connected to the voltage reference source, an output end of the comparator is connected to the charge-discharge electronic circuit, and the charge-discharge electronic circuit is further connected to the first end of the second energy storage element;
the comparator is used for comparing the voltage of the second energy storage element with the reference voltage of the voltage reference source; when the voltage of the second energy storage element is greater than the reference voltage, outputting the first level signal; when the voltage of the second energy storage element is smaller than the reference voltage, outputting the second level signal;
the charge-discharge electronic circuit is used for acquiring a signal of an output end of the comparator, controlling the second energy storage element to discharge when the comparator outputs the first level signal, and controlling the second energy storage element to charge through the second current when the comparator outputs the second level signal.
Optionally, the charge-discharge electronic circuit includes a charge-discharge switch, and the charge-discharge switch is disposed between the first end of the second energy storage element and a low potential point; and the control end of the charge and discharge switch is connected with the output end of the comparator.
Optionally, the second end of the second resistor and the second end of the second energy storage element have the same potential as the low potential point.
Optionally, the apparatus further includes: the flip-flop is connected with the clock output circuit;
the flip-flop is used for adjusting at least one of the frequency, the phase and the duty ratio of the clock signal.
Optionally, the voltage reference source includes a first reference source and a second reference source, the first reference source is connected to the second end of the third switch, and the second reference source is connected to the clock output circuit;
the first reference source is used for charging the first energy storage element in the first period;
the second reference source is used for outputting the reference voltage to the clock output circuit.
According to a second aspect of the invention, there is provided a chip comprising: an electronic clock generating apparatus according to the first aspect of the present invention and its alternatives.
The electronic clock generating device and the chip provided by the invention charge the first energy storage element in a first time interval through the voltage reference source, the voltage stabilizing element acquires the electric energy in the first energy storage element in a second time interval, and supplies power to the first resistor at a preset voltage in the first time interval and the second time interval, and the current output circuit outputs a first current to the second resistor, so that: the voltage of the first end of the second resistor is the preset voltage, so that the electric energy consumed by the first resistor can be equivalent to the electric energy charged by the first energy storage element; a second current is also output to the second energy storage element through a current output circuit; the first current is proportional to the second current, and the clock output circuit compares the voltage of the second energy storage element with the reference voltage of the voltage reference source and outputs a first level signal and a second level signal, so that the output of the clock signal is realized. The invention can make the first resistor, the second resistor, the first energy storage element and the second energy storage element mutually offset by the influence of the production process and the working environment, thereby reducing the influence of the production process and the working environment on the output clock signal.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a first schematic circuit diagram of an electronic clock generating device according to the present invention;
FIG. 2 is a second schematic circuit diagram of an electronic clock generating device according to the present invention;
FIG. 3 is a third schematic circuit diagram of an electronic clock generating device according to the present invention;
FIG. 4 is a fourth schematic circuit diagram of an electronic clock generating device according to the present invention;
FIG. 5 is a fifth schematic circuit diagram of an electronic clock generating device according to the present invention;
FIG. 6 is a sixth schematic circuit diagram of an electronic clock generating device according to the present invention;
FIG. 7 is a seventh schematic circuit diagram of an electronic clock generating device according to the present invention;
FIG. 8 is a circuit diagram eight of an electronic clock generating device according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The terms "first," "second," "third," "fourth," and the like in the description and in the claims, as well as in the drawings, if any, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used is interchangeable under appropriate circumstances such that the embodiments of the invention described herein are, for example, capable of operation in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed, but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.
The technical solution of the present invention will be described in detail below with specific examples. The following several specific embodiments may be combined with each other, and details of the same or similar concepts or processes may not be repeated in some embodiments.
FIG. 1 is a first schematic circuit diagram of an electronic clock generating device according to the present invention.
With reference to FIG. 1, the apparatus described, for use with a self-clocking reference source U4Obtaining a clock signal, comprising: voltage reference source U1A first energy storage element C1A second energy storage element C2A first resistor R1A second resistor R2Voltage stabilizing element CPCurrent output circuit U2Clock output circuit U3A first switch S1A second switch S2And a third switch S3And a fourth switch S4(ii) a Wherein the first switch S1And said second switch S2The same opening or the same closing, the third switch S3And said fourth switch S4Open simultaneously or close simultaneously.
The voltage reference source U1Is connected with the clock output circuit U3Said second resistance R2First terminal of, the second energy storage element C2The first ends of the two ends are connected with the current output circuit U2The clock output circuit U3Is also connected with the second energy storage element C2A first end of (a);
the first switch S1Is connected with the first energy storage element C1A second end of the first resistor R is respectively connected with the first end of the first resistor R1And the voltage stabilizing element CPA first end of (a); the second switch S2Is connected with the first energy storage element C1A second terminal connected to the second resistor R2The first end of (a).
The third switch S3Is connected with the first energy storage element C1A second terminal connected to the voltage reference source U1(ii) a The fourth switch S4Is connected with the first energy storage element C1A second end of (a), the second end being connected to ground; the first switch S1The second switch S2The third switch S3And a fourth switch S4Are all connected with the clock reference source U4。
The clock reference source U4For controlling the first switch S during a first period1And said second switch S2Is closed, and the third switch S3And said fourth switch S4Disconnecting; controlling the first switch S for a second period of time1And said second switch S2Is open, and the third switch S3And said fourth switch S4Closing; wherein the first time interval and the second time interval are two adjacent time intervals, and one first time interval and one adjacent second time interval constitute the clock reference source U4One reference period of time.
Wherein, the clock reference source U4Can be used to output a signal to the first switch S respectively1And a second switch S2Outputting another signal to the third switch S3And a fourth switch S4So that: first switch S1And a second switch S2When closed, the third switch S3And a fourth switch S4Disconnecting; first switch S1And a second switch S2When turned off, the third switch S3And a fourth switch S4And (5) closing. Clock reference source U4Is the reference period TrThe corresponding frequency is the reference frequency fr。
Clock reference source U4The output signals may be a general RC clock, a Phase Locked Loop (PLL) clock, or a crystal oscillator clock, which may output two signals with the same amplitude, the same frequency, and the opposite phases, that is, the two signals are output to the first switch S1And a second switch S2A signal and output to the third switch S3And a fourth switch S4The other signal of (1).
Through the first switch S1A second switch S2And a third switch S3And a fourth switch S4Can realize the first energy storage element C1Charge and discharge control of (2), thereby makingObtaining: first energy storage element C1Voltage stabilizing element C during chargingPAnd a first resistor R1Without consuming the charged energy, the voltage-stabilizing element CPObtaining a first energy storage element C1When the electric energy is in, the first energy storage element C1Only discharged, not charged, thereby due to the voltage-stabilizing element CPVoltage holding preset voltage V0The first resistor R can be ensured unchanged1The consumed electric energy can be regarded as the first energy storage element C1The charged energy is equal.
The voltage reference source U1For supplying power to the first energy storage element C during the first period1Charging; and can also be used for outputting a circuit U to a clock3And outputting the reference voltage.
The voltage stabilizing element CPFor obtaining the first energy storage element C during the second period1And at a preset voltage V during the first and second periods0To the first resistor R1And (5) supplying power.
The current output circuit U2For applying a voltage to the second resistor R2Outputs a first current I1So that: the second resistor R2The voltage of the first terminal of (1) is the preset voltage V0(ii) a And to the second energy storage element C2Output a second current I2(ii) a Wherein the first current I1And the second current I2In proportion.
The clock output circuit U3For comparing the second energy storage element C2Voltage of and the voltage reference source U1The output reference voltage; in the second energy storage element C2When the voltage of the second energy storage element is greater than the reference voltage, outputting a first level signal and controlling the second energy storage element to discharge; in the second energy storage element C2Is less than the reference voltage, outputs a second level signal and controls the second energy storage element C2Passing the second current I2Charging; wherein the first level signal and the second level signal constitute the clock signal.
The clock signal generated by the electronic clock generating device is composed of a first level signal and a second level signal which are alternately generated, wherein the first level signal can be a high level signal, and the second level signal can be a low level signal.
First energy storage element C1A first capacitor and a second energy storage element C can be adopted2A second capacitor may be used, and in alternative embodiments, other elements that can store charge may be used. Voltage stabilizing element CPA voltage stabilizing capacitor may be used, and in alternative embodiments, the voltage stabilizing element CPOther devices that can produce a voltage stabilization effect, such as filters, may also be selected. If the voltage stabilizing element CPFor voltage stabilizing capacitor, then because voltage stabilizing capacitor's capacitance value is big enough, voltage stabilizing capacitor's voltage variation is minimum, and its both ends voltage can be regarded as stable voltage, promptly: so that the first resistance R1The electric charge is consumed at the stable voltage. In addition, a voltage stabilizing element CPSecond terminal and first resistor R1May be grounded, or other similar low potential.
Since the voltage stabilizing element CPFirst terminal and first resistor R1Is always a first resistor R1Providing a predetermined voltage V0Can enable the first energy storage element C to be powered in the first period of time1The received charging electric energy and the first resistor R in the first time interval and the second time interval1The consumed electric energy is equal, and the reference frequency f can be further setrA first energy storage element C1Capacitance value of (1), preset voltage V0And a first resistor R1A quantitative relationship is established between the resistance values.
Specifically, the electrical energy can be characterized by an amount of charge, then:
first energy storage element C1Amount of charge Q of charging+Can be characterized as:
Q+＝VR1·C1；
wherein, VR1As a voltage reference source U1To the first energy storage element C1The charging voltage of the charge.
Since the voltage stabilizing element CPAt a voltage ofA first resistor R1The charged voltage remains unchanged.
A first resistor R1Amount of charge Q consumed-Can be characterized as:
due to the first energy storage element C1The charging electric energy is equal to the first resistor R1The consumed electric energy comprises the following components:
Q+＝Q-；
thus, it is possible to obtain:
wherein, TrIs a clock reference source U4The reference period of (a); f. ofrIs a clock reference source U4Due to fr＝1/TrThen, there are:
V0＝VR1·C1·R1·fr。
due to the second resistance R2The voltage of the first terminal of (1) is the preset voltage V0To the second energy storage element C2Output a second current I2The first current I1And the second current I2In proportion, and the clock output circuit U3Comparing the second energy storage element C2Voltage of and the voltage reference source U1The reference voltage of (a) outputs a clock signal; can be arranged at the first energy storage element C1Capacitance value of (1), second energy storage element C2A first resistance R1And a second resistor R2A quantitative relationship is established between the resistance values.
Specifically, the first current I1Can be characterized as:
according to the second energy storage element C2The charging principle of (2) may be:
I2·T0＝VR2·C2；
wherein, VR2As a voltage reference source U1To clock output circuit U3The output reference voltage.
If the first current I1And a second current I2The ratio of the current values is a, i.e.: i is2＝a·I1；
Due to f0＝1/T0Then, there are:
wherein f is0For clock output circuit U3Frequency of the output signal, T0For clock output circuit U3The period of the output signal may be a clock frequency and a clock period of the output clock signal.
If it is
Greater than 1, clock frequency f can be realized0Relative to a reference frequency frUp-converting; if it is
Less than 1, clock frequency f can be realized0Relative to a reference frequency frAnd (4) reducing the frequency. Therefore, the embodiment realizes arbitrary frequency increasing and frequency reducing output, namely the clock reference source U can be used4Obtaining a clock signal of an arbitrary division ratio, in an integrated circuit, of
All the steps can be independent of the production process and the working environment, so the frequency increasing and the frequency reducing can be independent of the production process and the working environment.
It can also be understood as a frequency dividing ratio, when it is greater than 1, it can implement frequency up, and when it is less than 1, it can implement frequency down. In addition, the frequency dividing ratio can include integer frequency up-conversion and frequency down-conversion, and non-integer frequency up-conversion and frequency down-conversion, and the embodiment has universality for various frequency up-conversion and frequency down-conversion requirements.
It can be seen that the first energy storage element C can be made based on the quantization relation established by the above circuit1And a second energy storage element C2And a first resistor R1And a second resistor R2The influence of the production process and the working environment is mutually offset, and the influence of the production process and the working environment on the output clock signal is reduced.
FIG. 2 is a second schematic circuit diagram of an electronic clock generating device according to the present invention.
Referring to fig. 2, the current output circuit U2Comprises an operational amplifier A1And output sub-circuit U21The operational amplifier A1And the voltage stabilizing element CPIs connected to the first terminal of the operational amplifier A1And the second input end of the second resistor R2Is connected to the first terminal of the operational amplifier A1Is connected with the output sub-circuit U21(ii) a The output sub-circuit U21Respectively connected with the second resistors R2And the second energy storage element C2Is connected to the first end of the first housing.
The operational amplifier A1For controlling said output sub-circuit U21To the second resistor R2Outputting the first current I1And controls the output sub-circuit U21To the second energy storage element C2Outputting the second current I2。
Due to the operational amplifier A1The first input end of the voltage stabilizing element is connected with a voltage stabilizing element CPThe input voltage of the first terminal of (1) is a preset voltage V0The second input end is connected with a second resistor R2The first terminal of (1) is also at a predetermined voltage V0Due to operational amplificationAmplifier A1The voltages of the first input end and the second input end are always kept consistent, and the operational amplifier A1The output signal of (1) is kept unchanged, and the output sub-circuit U can be always controlled21Outputs a first current I1And a second current I2。
FIG. 3 is a third schematic circuit diagram of an electronic clock generating device according to the present invention.
Referring to fig. 3, the output sub-circuit U21Comprises a first MOS transistor Q1And a second MOS transistor Q2The first MOS transistor Q1And the second MOS transistor Q2Are all connected with the operational amplifier A1The output end of the first MOS transistor Q1Is connected to the second resistor R2The first end of the second MOS transistor Q2Is connected with the second energy storage element C2The first MOS transistor Q1And a second MOS transistor Q2The source electrodes are all connected with a power supply U5。
First MOS transistor Q1And a second MOS transistor Q2The Semiconductor device may be a PMOS tube (positive channel Metal Oxide Semiconductor). First MOS transistor Q1And a second MOS transistor Q2May be of the same size so that the first current I1And a second current I2Equal, i.e. a may be 1; first MOS transistor Q1And a second MOS transistor Q2Different sizes are also possible, so that a takes on other values.
The a can be very accurate and does not change along with the environmental changes of process batch, temperature, voltage and the like, so that the influence of the environmental changes of the process batch, the temperature, the voltage and the like on the clock signal is reduced.
Wherein the first MOS transistor Q1And a second MOS transistor Q2MOS tubes in a cascade mode can be replaced. Output sub-circuit U21The first current I can be any other current I capable of being output1And a second current I2The circuit structure of (1) may be exemplified as a current mirror so that the first current I1And a second current I2Are equal.
If the first current I1And a second current I2Equal, then there are:
FIG. 4 is a fourth schematic circuit diagram of an electronic clock generating device according to the present invention.
Referring to fig. 4, the clock output circuit U3Comprises a comparator CMP and a charge-discharge electronic circuit U31The first input end of the comparator CMP is connected with the second energy storage element C2A second input terminal of the comparator CMP and the voltage reference source U1Connected, the output end of the comparator CMP is connected with the charge-discharge electronic circuit U31Connected to the charge-discharge electronic circuit U31Is also connected with the second energy storage element C2The first end of (a).
The comparator CMP for comparing the second energy storage element C2Voltage of and the voltage reference source U1A reference voltage of (d); in the second energy storage element C2When the voltage of the first voltage is greater than the reference voltage, outputting a first level signal; in the second energy storage element C2Is less than the reference voltage, a second level signal is output.
The charge-discharge electronic circuit U31For obtaining the signal at the output terminal of the comparator CMP, and controlling the second energy storage element C when the comparator CMP outputs the first level signal2Discharging, and controlling the second energy storage element C when the comparator CMP outputs the second level signal2Passing the second current I2And (6) charging.
Since the comparator CMP compares the second energy storage element C2With reference voltage, the output signal of the comparator CMP can be understood as being dependent on the second energy storage element C2The required clock signal can be obtained by this embodiment. At the same time, the second energy storage element C is controlled2The comparator CMP is also used for charging and discharging, and the circuit design can effectively simplify the device.
FIG. 5 is a fifth schematic circuit diagram of an electronic clock generating device according to the present invention.
Referring to fig. 5, the charge and discharge electronic circuit U31Comprises a charge-discharge switch SRThe charge and discharge switch SRIs arranged on the second energy storage element C2Between the first end of the first transistor and a low potential point; the charge and discharge switch SRIs connected to the output of said comparator CMP.
When the comparator CMP outputs the first level signal, the charge-discharge switch S is controlledRWhen closed, the second energy storage element C2The first end of the second energy storage element C is connected with a low potential to realize the second energy storage element C2When discharging, the second energy storage element C is enabled2After the voltage of the Comparator (CMP) is lower than the reference voltage, the output signal of the Comparator (CMP) is changed into a second level signal to control a charge-discharge switch (S)ROff, the second energy storage element C2Is not connected with a low potential, a current output circuit U2Can be used for the second energy storage element C2Charging, when the voltage is higher than the reference voltage, the output signal of the comparator CMP is changed into a first level signal to control the charge-discharge switch SRClosing, again effecting the second energy storage element C2Is discharged.
In one embodiment, the second resistor R2And the second end of the second energy storage element C2The second terminal is equal to the low potential point. I.e. the second energy storage element C2Second terminal, second resistor R2The second terminals of the first and second terminals are connected to a low potential, which may be ground.
FIG. 6 is a sixth schematic circuit diagram of an electronic clock generating device according to the present invention.
Referring to fig. 6, the apparatus further includes: a flip-flop TR, the flip-flop TR and the clock output circuit U3Connecting; the flip-flop TR is configured to adjust at least one of a frequency, a phase, and a duty cycle of the clock signal.
In this embodiment, the flip-flop TR is coupled to the clock output circuit U3The output clock signal is adjusted to output an adjusted clock signal. For example, if a duty cycle is requiredIs 50% of the clock signal, the circuit U can be clocked out by means of the flip-flop TR3Halving the output frequency of the output clock signal; at this time, the flip-flop TR may be a T flip-flop.
FIG. 7 is a seventh schematic circuit diagram of an electronic clock generating device according to the present invention.
Referring to FIG. 7, the voltage reference source U1May include a first reference source U11And a second reference source U12It may be a voltage source, the first reference source and the third switch S3Is available for a first period of time to the first energy storage element C1Providing a charging voltage VR1To realize the first energy storage element C1Charging of (1); the second reference source U12Is connected with the clock output circuit U3For outputting a signal to the clock output circuit U3Outputting the reference voltage VR2。
First reference source U11And a second reference source U12The reference sources may be different reference sources or the same reference source, and if the reference sources are the same reference source, it can be understood that the voltage reference source U is1May comprise only one reference source, respectively connected to the third switch S3Second terminal and clock output circuit U3And (4) connecting.
If the same reference source is adopted, the following are available:
if a is 1, then:
FIG. 8 is a circuit diagram eight of an electronic clock generating device according to the present invention.
Please refer to fig. 8, which is a circuit obtained by combining the embodiments illustrated in fig. 1 to 7; wherein the first energy storage element C1Using a first capacitor and a second energy-storing element C2Using a second capacitor, a voltage-stabilizing element CPAnd a voltage stabilizing capacitor is adopted. A first resistor R1The second end of the first capacitor is grounded, the second end of the second capacitor is grounded, and the second resistor R is connected with the first resistor R2Second terminal and charge-discharge switch SRAre all grounded.
The present embodiment further provides a chip, including: any one of the embodiments and alternatives thereof described above relates to an electronic clock generating device.
Finally, it should be noted that: the above embodiments are only used to illustrate the technical solution of the present invention, and not to limit the same; while the invention has been described in detail and with reference to the foregoing embodiments, it will be understood by those skilled in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some or all of the technical features may be equivalently replaced; and the modifications or the substitutions do not make the essence of the corresponding technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (10)
1. An electronic clock generating apparatus for deriving a clock signal from a clock reference source, comprising: the voltage stabilizing circuit comprises a voltage reference source, a first energy storage element, a second energy storage element, a first resistor, a second resistor, a voltage stabilizing element, a current output circuit, a clock output circuit, a first switch, a second switch, a third switch and a fourth switch; wherein the first switch and the second switch are on or off simultaneously, and the third switch and the fourth switch are on or off simultaneously;
the voltage reference source is connected with the clock output circuit, the first end of the second resistor and the first end of the second energy storage element are both connected with the current output circuit, and the clock output circuit is also connected with the first end of the second energy storage element;
the first end of the first switch is connected with the first end of the first energy storage element, and the second end of the first switch is respectively connected with the first end of the first resistor and the first end of the voltage stabilizing element; the first end of the second switch is connected with the second end of the first energy storage element, and the second end of the second switch is connected with the first end of the second resistor; the first end of the third switch is connected with the first end of the first energy storage element, and the second end of the third switch is connected with the voltage reference source; the first end of the fourth switch is connected with the second end of the first energy storage element, and the second end of the fourth switch is connected with the ground; the first switch, the second switch, the third switch and the fourth switch are all connected with the clock reference source;
the clock reference source is used for controlling the first switch and the second switch to be closed and the third switch and the fourth switch to be opened in a first period; controlling the first switch and the second switch to be open and the third switch and the fourth switch to be closed in a second period; wherein the first time interval and the second time interval are two adjacent time intervals, and one first time interval and one adjacent second time interval form one reference cycle of the clock reference source;
the voltage reference source is used for charging the first energy storage element in the first period;
the voltage stabilizing element is used for acquiring the electric energy in the first energy storage element in the second time interval and supplying power to the first resistor at a preset voltage in the first time interval and the second time interval;
the current output circuit is configured to output a first current to the second resistor such that: the voltage of the first end of the second resistor is the preset voltage; and outputting a second current to the second energy storage element; wherein the first current is proportional to the second current;
the clock output circuit is used for comparing the voltage of the second energy storage element with the reference voltage output by the voltage reference source; when the voltage of the second energy storage element is greater than the reference voltage, outputting a first level signal and controlling the second energy storage element to discharge; when the voltage of the second energy storage element is smaller than the reference voltage, outputting a second level signal and controlling the second energy storage element to be charged through the second current; wherein the first level signal and the second level signal constitute the clock signal.
2. The apparatus according to claim 1, wherein the current output circuit comprises an operational amplifier and an output sub-circuit, a first input terminal of the operational amplifier is connected to a first terminal of the voltage stabilizing element, a second input terminal of the operational amplifier is connected to a first terminal of the second resistor, and an output terminal of the operational amplifier is connected to the output sub-circuit; the output sub-circuit is respectively connected with the first end of the second resistor and the first end of the second energy storage element;
the operational amplifier is used for controlling the output sub-circuit to output the first current to the second resistor and controlling the output sub-circuit to output the second current to the second energy storage element.
3. The apparatus of claim 2, wherein the output sub-circuit comprises a first MOS transistor and a second MOS transistor, gates of the first MOS transistor and the second MOS transistor are both connected to the output terminal of the operational amplifier, a drain of the first MOS transistor is connected to the first terminal of the second resistor, a drain of the second MOS transistor is connected to the first terminal of the second energy storage element, and sources of the first MOS transistor and the second MOS transistor are both connected to a power supply.
4. The apparatus of claim 3, wherein the first MOS transistor and the second MOS transistor are both PMOS transistors.
5. The device of claim 1, wherein the clock output circuit comprises a comparator and a charge-discharge electronic circuit, a first input terminal of the comparator is connected to the first terminal of the second energy storage element, a second input terminal of the comparator is connected to the voltage reference source, an output terminal of the comparator is connected to the charge-discharge electronic circuit, and the charge-discharge electronic circuit is further connected to the first terminal of the second energy storage element;
the comparator is used for comparing the voltage of the second energy storage element with the reference voltage of the voltage reference source; when the voltage of the second energy storage element is greater than the reference voltage, outputting the first level signal; when the voltage of the second energy storage element is smaller than the reference voltage, outputting the second level signal;
the charge-discharge electronic circuit is used for acquiring a signal of an output end of the comparator, controlling the second energy storage element to discharge when the comparator outputs the first level signal, and controlling the second energy storage element to charge through the second current when the comparator outputs the second level signal.
6. The apparatus of claim 5, wherein the charge-discharge electronic circuit comprises a charge-discharge switch disposed between the first end of the second energy storage device and a low potential point; and the control end of the charge and discharge switch is connected with the output end of the comparator.
7. The apparatus of claim 6, wherein the second terminal of the second resistor and the second terminal of the second energy storage element are at the same potential as the low potential point.
8. The apparatus of any one of claims 1 to 7, further comprising: the flip-flop is connected with the clock output circuit;
the flip-flop is used for adjusting at least one of the frequency, the phase and the duty ratio of the clock signal.
9. The apparatus of any of claims 1 to 7, wherein the voltage reference source comprises a first reference source and a second reference source, the first reference source is connected to the second terminal of the third switch, and the second reference source is connected to the clock output circuit;
the first reference source is used for charging the first energy storage element in the first period;
the second reference source is used for outputting the reference voltage to the clock output circuit.
10. A chip, comprising: an electronic clock generating apparatus as claimed in any one of claims 1 to 9.
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| CN201711117817.7A CN109782573B (en) | 2017-11-13 | 2017-11-13 | Electronic clock generating device and chip |
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| CN201711117817.7A CN109782573B (en) | 2017-11-13 | 2017-11-13 | Electronic clock generating device and chip |
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| JP2017044649A (en) * | 2015-08-28 | 2017-03-02 | セイコーインスツル株式会社 | Electronic timepiece |
| CN206149153U (en) * | 2016-09-21 | 2017-05-03 | 国网山东省电力公司青岛供电公司 | Clock circuit |
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| US4879505A (en) * | 1986-12-23 | 1989-11-07 | Analog Devices, Inc. | Temperature and power supply compensation circuit for integrated circuits |
| CN2074471U (en) * | 1990-05-02 | 1991-04-03 | 林土胜 | Intelligent programable timing controller |
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