CN109768136A - A kind of LED epitaxial slice and its growing method - Google Patents

A kind of LED epitaxial slice and its growing method Download PDF

Info

Publication number
CN109768136A
CN109768136A CN201811503410.2A CN201811503410A CN109768136A CN 109768136 A CN109768136 A CN 109768136A CN 201811503410 A CN201811503410 A CN 201811503410A CN 109768136 A CN109768136 A CN 109768136A
Authority
CN
China
Prior art keywords
layer
insert
type
insert layer
type semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
CN201811503410.2A
Other languages
Chinese (zh)
Inventor
洪威威
王倩
程丁
董彬忠
周飚
胡加辉
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HC Semitek Zhejiang Co Ltd
Original Assignee
HC Semitek Zhejiang Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by HC Semitek Zhejiang Co Ltd filed Critical HC Semitek Zhejiang Co Ltd
Priority to CN201811503410.2A priority Critical patent/CN109768136A/en
Publication of CN109768136A publication Critical patent/CN109768136A/en
Withdrawn legal-status Critical Current

Links

Abstract

The invention discloses a kind of LED epitaxial slice and its growing methods, belong to technical field of semiconductors.The LED epitaxial slice includes substrate, n type semiconductor layer, active layer, low temperature P-type layer, electronic barrier layer and p type semiconductor layer, and the n type semiconductor layer, the active layer, the low temperature P-type layer, the electronic barrier layer and the p type semiconductor layer stack gradually over the substrate；The LED epitaxial slice further includes the first insert layer and the second insert layer stacked gradually, and first insert layer and second insert layer are arranged between the active layer and the low temperature P-type layer；The material of first insert layer uses undoped aluminium nitride, and the material of second insert layer uses the InGaN of p-type doping.The present invention between active layer and low temperature P-type layer by setting gradually the gallium indium nitride layer of undoped aln layer and p-type doping, the final luminous efficiency and light efficiency for improving light emitting diode.

Description

A kind of LED epitaxial slice and its growing method
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of LED epitaxial slice and its growing method.
Background technique
Light emitting diode (English: Light Emitting Diode, referred to as: LED) it is a kind of semi-conductor electricity that can be luminous Subcomponent.Gallium nitride (GaN) sill has good thermal conductivity, while it is excellent to have high temperature resistant, acid and alkali-resistance, high rigidity etc. Characteristic is widely used in the light emitting diode of various wave bands.
The core component of light emitting diode is chip, and chip includes epitaxial wafer and the electrode on epitaxial wafer.It is existing GaN base light emitting epitaxial wafer includes substrate, n type semiconductor layer, active layer and p type semiconductor layer, and active layer includes alternating Multiple Quantum Well of stacking and multiple quantum are built.Quantum is built for electrons and holes to be limited in Quantum Well, and Quantum Well is used for The recombination luminescence of electrons and holes is carried out, n type semiconductor layer is used to provide the electronics for carrying out recombination luminescence, and p type semiconductor layer is used In providing the hole for carrying out recombination luminescence, substrate is used to provide growing surface for epitaxial material.
The electron amount that N-type semiconductor provides is much larger than the number of cavities that p type semiconductor layer provides, in addition the volume of electronics Much smaller than the volume in hole, cause the electron amount injected in active layer much larger than number of cavities.In order to avoid n type semiconductor layer The electron transfer of offer carries out non-radiative recombination with hole into p type semiconductor layer, it will usually in active layer and p type semiconductor layer Between electronic barrier layer is set, stop electronics to transit to p type semiconductor layer from active layer.
The material of electronic barrier layer generally selects aluminium gallium nitride alloy (AlGaN), since aluminium gallium nitride alloy is needed in higher growth At a temperature of generate, therefore the growth temperature of electronic barrier layer is usually higher.And the material of Quantum Well generally selects InGaN (InGaN), high temperature will cause phosphide atom and parse from InGaN.So if electronic barrier layer is set up directly on active layer On, then the higher growth temperature of electronic barrier layer will cause the parsing of the phosphide atom in Quantum Well, and then influence electronics in Quantum Well With the combined efficiency in hole, the internal quantum efficiency of epitaxial wafer is reduced, the final luminous efficiency for reducing light emitting diode.In order to reduce Low temperature P can be also arranged in influence of the higher growth temperature of electronic barrier layer to Quantum Well between active layer and electronic barrier layer The growth temperature of type layer, low temperature P-type layer is lower, can protect to Quantum Well, avoids the higher growth temperature of electronic barrier layer Degree influences active layer.
In the implementation of the present invention, the inventor finds that the existing technology has at least the following problems:
The hole injection active layer institute that the setting of low temperature P-type layer and electronic barrier layer can all cause p type semiconductor layer to provide The distance of process is elongated.Since the transfer ability in hole is poor, movement get up to need higher energy, therefore low temperature P-type layer and Being affected for the hole injection active layer that the setting of electronic barrier layer provides p type semiconductor layer, can reduce p type semiconductor layer The number of cavities of active layer is injected, the combined efficiency of electrons and holes in Quantum Well is reduced, is raising simultaneously light emitting diode just To operating voltage.
Summary of the invention
The embodiment of the invention provides a kind of LED epitaxial slice and its growing methods, are able to solve prior art drop Low electronics and combined efficiency with hole, the problem of increasing the positive operating voltage of light emitting diode.The technical solution is as follows:
On the one hand, the embodiment of the invention provides a kind of LED epitaxial slice, the LED epitaxial slice packets Include substrate, n type semiconductor layer, active layer, low temperature P-type layer, electronic barrier layer and p type semiconductor layer, the n type semiconductor layer, The active layer, the low temperature P-type layer, the electronic barrier layer and the p type semiconductor layer stack gradually over the substrate； The LED epitaxial slice further includes the first insert layer and the second insert layer stacked gradually, first insert layer and institute The second insert layer is stated to be arranged between the active layer and the low temperature P-type layer；The material of first insert layer, which uses, not to be mixed Miscellaneous aluminium nitride, the material of second insert layer use the InGaN of p-type doping.
Optionally, the active layer includes the multiple composite constructions stacked gradually, and each composite construction includes successively The Quantum Well and quantum of stacking are built；The material of the Quantum Well uses undoped InGaN, indium in second insert layer The content of component is less than the content of indium component in the Quantum Well.
Preferably, the material of second insert layer is using the In for mixing MgxGa1-xN, 0.2 < x < 0.3.
Further, second insert layer with a thickness of 4nm~8nm.
Further, the 1/3~2/3 of the thickness with a thickness of second insert layer of first insert layer.
Optionally, the doping concentration of P-type dopant is 5*10 in second insert layer19/cm3~8*1019/cm3。
On the other hand, the embodiment of the invention provides a kind of growing method of LED epitaxial slice, the growth sides Method includes:
One substrate is provided；
N type semiconductor layer, active layer, the first insert layer, the second insert layer, low temperature p-type are successively grown over the substrate Layer, electronic barrier layer and p type semiconductor layer；
Wherein, the material of first insert layer uses undoped aluminium nitride, and the material of second insert layer uses P The InGaN of type doping.
Optionally, the active layer includes the multiple composite constructions stacked gradually, and each composite construction includes successively The Quantum Well and quantum of stacking are built；The growth temperature of second insert layer is higher than the growth temperature of the Quantum Well.
Preferably, the growth temperature of second insert layer is 10 DEG C~20 DEG C higher than the growth temperature of the Quantum Well.
Optionally, first insert layer is formed using physical gas phase deposition technology.
Technical solution provided in an embodiment of the present invention has the benefit that
By setting gradually the first insert layer and the second insert layer, the first insert layer between active layer and low temperature P-type layer Material use undoped aluminium nitride, potential barrier is very high, at the same the material of the second insert layer use p-type doping InGaN, Potential barrier is very low.First insert layer and the second insert layer are arranged in pairs or groups, using potential barrier difference between the two, " aerohydrous can be formed Library " temporarily stores extra hole, continuously inputs for active layer and send hole, shortens the transmission range in hole, promotes empty Longitudinal transmission in cave, improves the low problem of hole mobility, increases injected holes quantity in active layer, improve electrons and holes Combined efficiency, reduce the positive operating voltage of light emitting diode.And second in insert layer and low temperature P-type layer doped with P Type dopant can easily be that " hole reservoir " provides hole, effectively increase the quantity in hole, be conducive to improve luminous two The internal quantum efficiency of pole pipe, the final luminous efficiency and light efficiency for improving light emitting diode.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other Attached drawing.
Fig. 1 is a kind of structural schematic diagram of LED epitaxial slice provided in an embodiment of the present invention；
Fig. 2 is the structural schematic diagram of active layer provided in an embodiment of the present invention；
Fig. 3 is the schematic diagram of layering barrier height in the middle part of LED epitaxial slice provided in an embodiment of the present invention；
Fig. 4 is a kind of flow chart of the growing method of LED epitaxial slice provided in an embodiment of the present invention.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with attached drawing to embodiment party of the present invention Formula is described in further detail.
The embodiment of the invention provides a kind of LED epitaxial slices.Fig. 1 is a kind of hair provided in an embodiment of the present invention The structural schematic diagram of optical diode epitaxial wafer.Referring to Fig. 1, which includes substrate 10, n type semiconductor layer 20, active layer 30, the first insert layer 40, the second insert layer 50, low temperature P-type layer 60, electronic barrier layer 70 and p type semiconductor layer 80, n type semiconductor layer 20, active layer 30, the first insert layer 40, the second insert layer 50, low temperature P-type layer 60, electronic barrier layer 70 It is sequentially laminated on substrate 10 with p type semiconductor layer 80.
In the present embodiment, the material of the first insert layer 40 uses undoped aluminium nitride, the material of the second insert layer 50 The InGaN adulterated using p-type.
The embodiment of the present invention between active layer and low temperature P-type layer by setting gradually the first insert layer and the second insertion The material of layer, the first insert layer uses undoped aluminium nitride, and potential barrier is very high, while the material of the second insert layer is mixed using p-type Miscellaneous InGaN, potential barrier are very low.First insert layer and the second insert layer are arranged in pairs or groups, it, can using potential barrier difference between the two With formation " hole reservoir ", extra hole is temporarily stored, is continuously inputted for active layer and send hole, shorten the biography in hole Defeated distance promotes longitudinal transmission in hole, improves the low problem of hole mobility, increase injected holes quantity in active layer, The combined efficiency for improving electrons and holes, reduces the positive operating voltage of light emitting diode.And second insert layer and low temperature p-type Doped with P-type dopant in layer, it can easily be that " hole reservoir " provides hole, effectively increase the quantity in hole, have Conducive to the internal quantum efficiency for improving light emitting diode, the final luminous efficiency and light efficiency for improving light emitting diode.
Fig. 2 is the structural schematic diagram of active layer provided in an embodiment of the present invention.Referring to fig. 2, active layer 30 may include according to Multiple composite constructions 31 of secondary stacking, each composite construction 31 include that the Quantum Well 32 stacked gradually and quantum build 33.Wherein, it measures The material of sub- trap 32 can use undoped InGaN, and the material that quantum builds 33 can use undoped gallium nitride.Have Quantum is built in active layer is arranged close to the first insert layer, can cooperate with the first insert layer, stop electron transition to the second insert layer In with hole carry out it is compound, avoid electronics overflow.
Optionally, the content of indium component can be less than the content of indium component in Quantum Well 32 in the second insert layer 50.By The content of indium component is limited in lesser range in two insert layers, promotes to carry out compound hair with electronics in the sub- trap of hole injection fluence Light.
Fig. 3 is the schematic diagram of layering barrier height in the middle part of LED epitaxial slice provided in an embodiment of the present invention.Referring to The potential barrier of Fig. 3, the first insert layer 40 are higher than active layer 30 and the second insert layer 50, and the first insert layer 40 and the second insert layer 50 are matched Conjunction can be formed " hole reservoir ", while the potential barrier of the second insert layer 50 is higher than the Quantum Well 32 in active layer 30, is conducive to electricity Son and hole recombination luminescence in Quantum Well 32.
Preferably, the material of the second insert layer 50 can be using the In for mixing MgxGa1-xN, 0.2 < x < 0.3, such as x= 0.25.The content of indium component within this range, preferably can cooperatively form " aerohydrous with the first insert layer in second insert layer Library " also can effectively promote in the sub- trap of hole injection fluence.
Correspondingly, the material of Quantum Well 32 can use undoped InyGa1-yN, 0.5 < y < 0.8, such as y=0.6, with Realize the recombination luminescence of electrons and holes.
Further, the thickness of the second insert layer 50 can be 4nm~8nm, such as 6nm.The thickness of second insert layer is herein In range, the content of indium component in the second insert layer can be cooperated, effectively accumulate extra hole, while reducing setting as far as possible Adverse effect caused by second insert layer such as reduces whole crystal quality.
Further, the thickness of the first insert layer 40 can be the thickness 1/3~2/3 of the second insert layer 50.First inserts Enter layer and the second insert layer using this ratio setting thickness, " the hole reservoir " of formation is preferable to the accumulation effect in hole, also not It will cause the waste of material.
Specifically, the thickness of the first insert layer 40 can be 2nm~5nm.With the thickness matching of the second insert layer, effect is realized Fruit is good.
Optionally, the doping concentration of P-type dopant can be 5*10 in the second insert layer 5019/cm3~8*1019/cm3, such as 6.5*1019/cm3.The doping concentration of P-type dopant can easily be " aerohydrous within this range in second insert layer Library " provides hole, the quantity in hole is effectively increased, instead of the effect of part p type semiconductor layer, so that the thickness of p type semiconductor layer Degree is reduced, and reduces the light that p type semiconductor layer absorbs, the final luminous efficiency for improving light emitting diode.
Preferably, the thickness of p type semiconductor layer 80 can be 50nm~100nm, such as 80nm.The thickness of p type semiconductor layer Reduce, the absorption of light is accordingly reduced, can be further improved the luminous efficiency of light emitting diode.
Specifically, the material of substrate 10 can use sapphire (main material is aluminum oxide), such as graphical blue precious Stone lining bottom (English: Patterned Sapphire Substrate, referred to as: PSS).The material of n type semiconductor layer 20 can be adopted With the gallium nitride of n-type doping (such as silicon).The material of low temperature P-type layer 60 can be using the gallium nitride of p-type doping (such as magnesium).Electronics resistance The material of barrier 70 can be using the aluminium gallium nitride alloy of p-type doping (such as magnesium), such as AlzGa1-zN, 0.1 < z < 0.5.P-type semiconductor The material of layer 80 can be using the gallium nitride of p-type doping (such as magnesium).
Further, the thickness of n type semiconductor layer 20 can be 1 μm~5 μm, preferably 3 μm；N in n type semiconductor layer 20 The doping concentration of type dopant can be 1018cm-3~1019cm-3, preferably 5*1018cm-3.The thickness of Quantum Well 32 can be 2nm~5nm, preferably 3nm；The thickness that quantum builds 33 can be 9nm~20nm, preferably 15nm；The quantity of composite construction 31 It can be 5~11, preferably 8.The thickness of low temperature P-type layer 60 can be 50nm~200nm, preferably 100nm；Low temperature The doping concentration of P-type dopant can be 10 in P-type layer 6018/cm3~1020/cm3, preferably 1019/cm3.Electronic barrier layer 70 Thickness can be 50nm~100nm, preferably 80nm；The doping concentration of P-type dopant can be in electronic barrier layer 70 1018/cm3~1020/cm3, preferably 1019/cm3.The doping concentration of P-type dopant can be 10 in p type semiconductor layer 8018/ cm3~1020/cm3, preferably 1019/cm3。
Preferably, in electronic barrier layer 70 aluminium component content can along the LED epitaxial slice stacking direction by It is decrescence small, so that the hole of p type semiconductor layer is accumulated in " the hole reservoir " that the first insert layer and the second insert layer are formed, together When can also effectively avoid electronics overflow.
Optionally, as shown in Figure 1, the LED epitaxial slice can also include buffer layer 91, the setting of buffer layer 91 exists Between substrate 10 and n type semiconductor layer 20, to alleviate the stress and defect that lattice mismatch generates between substrate material and gallium nitride, And nuclearing centre is provided for gallium nitride material epitaxial growth.
Specifically, the material of buffer layer 91 can use undoped gallium nitride.
Further, the thickness of buffer layer 91 can be 15nm~35nm, preferably 25nm.
Preferably, as shown in Figure 1, the LED epitaxial slice can also include high temperature buffer layer 92, high temperature buffer layer 92 are arranged between buffer layer 91 and n type semiconductor layer 20, further to alleviate lattice mismatch between substrate material and gallium nitride The stress and defect of generation provide crystal quality preferable growing surface for epitaxial wafer main structure.
In specific implementation, buffer layer is the gallium nitride of the layer of low-temperature epitaxy first in patterned substrate, because This is also referred to as low temperature buffer layer.The longitudinal growth for carrying out gallium nitride in low temperature buffer layer again, will form multiple mutually independent three Island structure is tieed up, referred to as three-dimensional nucleating layer；Then it is carried out between each three-dimensional island structure on all three-dimensional island structures The cross growth of gallium nitride forms two-dimension plane structure, referred to as two-dimentional retrieving layer；The finally high growth temperature one on two-dimensional growth layer The thicker gallium nitride of layer, referred to as intrinsic gallium nitride layer.By three-dimensional nucleating layer, two-dimentional retrieving layer and intrinsic gallium nitride in the present embodiment Layer is referred to as high temperature buffer layer.
Further, the thickness of high temperature buffer layer 92 can be 1 μm~3 μm, preferably 2 μm.
Optionally, as shown in Figure 1, the LED epitaxial slice can also include stress release layer 93, stress release layer 93 are arranged between n type semiconductor layer 20 and active layer 30, with the stress generated to lattice mismatch between sapphire and gallium nitride It is discharged, improves the crystal quality of active layer, be conducive to electrons and holes and shine in active layer progress radiation recombination, improve The internal quantum efficiency of LED, and then improve the luminous efficiency of LED.
Specifically, the material of stress release layer 93 can use gallium indium aluminum nitrogen (AlInGaN), can be released effectively sapphire The stress generated with gallium nitride crystal lattice mismatch, improves the crystal quality of epitaxial wafer, improves the luminous efficiency of LED.
Preferably, the molar content of aluminium component can be less than or equal to 0.2, in stress release layer 93 in stress release layer 93 The molar content of indium component can be less than or equal to 0.05, to avoid adverse effect is caused.
Further, the thickness of stress release layer 93 can be 50nm~500nm, preferably 300nm.
Optionally, as shown in Figure 1, the LED epitaxial slice can also include contact layer 94, contact layer 94 is arranged in P In type semiconductor layer 80, to form Ohmic contact between the electrode or transparent conductive film that are formed in chip fabrication technique.
Specifically, the material of contact layer 94 can be using the InGaN or gallium nitride of p-type doping.
Further, the thickness of contact layer 94 can be 50nm~100nm, preferably 80nm；P-type is adulterated in contact layer 94 The doping concentration of agent can be 1021/cm3~1022/cm3, preferably 5*1021/cm3。
The embodiment of the invention provides a kind of growing method of LED epitaxial slice, it is suitable for growing shown in FIG. 1 LED epitaxial slice.Fig. 4 is a kind of process of the growing method of LED epitaxial slice provided in an embodiment of the present invention Figure.Referring to fig. 4, which includes:
Step 201: a substrate is provided.
Optionally, which may include:
Controlled at 1000 DEG C~1200 DEG C (preferably 1100 DEG C), in hydrogen atmosphere to substrate carry out 1 minute~ It makes annealing treatment within 10 minutes (preferably 5 minutes)；
Nitrogen treatment is carried out to substrate.
The surface for cleaning substrate through the above steps avoids being conducive to the life for improving epitaxial wafer in impurity incorporation epitaxial wafer Long quality.
Step 202: successively growing n type semiconductor layer, active layer, the first insert layer, the second insert layer, low temperature on substrate P-type layer, electronic barrier layer and p type semiconductor layer.
In the present embodiment, the material of the first insert layer uses undoped aluminium nitride, and the material of the second insert layer uses P The InGaN of type doping.
Optionally, active layer may include the multiple composite constructions stacked gradually, and each composite construction includes stacking gradually Quantum Well and quantum build；The growth temperature of second insert layer is higher than the growth temperature of Quantum Well.The case where guaranteeing indium doping Under, the crystal quality of the second insert layer is improved as far as possible.
Preferably, the growth temperature of the second insert layer can be 10 DEG C~20 DEG C higher than the growth temperature of Quantum Well, can keep away Exempt from indium to parse at high temperature.
Specifically, the growth temperature of the second insert layer can be 730 DEG C~850 DEG C, such as 780 DEG C.
Further, the growth pressure of the second insert layer can be 100torr~300torr, such as 200torr；Second inserts The revolving speed of epitaxial wafer can be 400 revs/min~600 revs/min when entering layer growth, such as 500 turns.By the growth of the second insert layer The revolving speed of epitaxial wafer and the growth temperature of the second insert layer cooperate when pressure, growth, improve the crystal quality of the second insert layer.
Correspondingly, the growth temperature of Quantum Well can be 720 DEG C~829 DEG C, such as 760 DEG C；The growth pressure of Quantum Well can Think 100torr~500torr, such as 300torr.The growth temperature that quantum is built can be 850 DEG C~959 DEG C, such as 900 DEG C；Amount The growth pressure that son is built can be 100torr~500torr, such as 300torr.
Optionally, the first insert layer can using physical vapour deposition (PVD) (English: Physical Vapor Deposition, Referred to as: PVD) technology is formed, and such as magnetron sputtering technique, is reduced the formation temperature of the first insert layer, is avoided high temperature that indium is caused to parse.
Preferably, the formation temperature of the first insert layer can be 550 DEG C~650 DEG C, such as 600 DEG C.
In practical applications, the first insert layer can also using metallo-organic compound chemical gaseous phase deposition (English: Metal organic chemical vapor deposition, referred to as: MOCVD) technology formed, it is realized, is avoided with facilitating Epitaxial wafer is shifted when forming the process of the first insert layer.
Specifically, the growth temperature of the first insert layer can be 800 DEG C~850 DEG C, such as 825 DEG C；The life of first insert layer Long pressure can be 100torr~200torr, such as 150torr.
Specifically, which may include:
The first step, controlled at 1000 DEG C~1200 DEG C (preferably 1100 DEG C), pressure is 100torr~500torr (preferably 300torr), grows n type semiconductor layer on substrate；
Second step grows active layer on n type semiconductor layer；
Third step sequentially forms the first insert layer and the second insert layer on active layer；
4th step, controlled at 600 DEG C~750 DEG C (preferably 675 DEG C), pressure is that 100torr~300torr is (excellent It is selected as 200torr), the growing low temperature P-type layer in the second insert layer；
5th step, controlled at 200 DEG C~1000 DEG C (preferably 600 DEG C), pressure is that 50torr~500torr is (excellent It is selected as 250torr), electronic barrier layer is grown in low temperature P-type layer；
6th step, controlled at 600 DEG C~1000 DEG C (preferably 800 DEG C), pressure is that 100torr~300torr is (excellent It is selected as 200torr), the growing P-type semiconductor layer on electronic barrier layer.
Optionally, before the first step, which can also include:
Grown buffer layer on substrate.
Correspondingly, n type semiconductor layer is grown on the buffer layer.
Specifically, grown buffer layer on substrate may include:
Using PVD technique grown buffer layer on substrate.
Specifically, the formation condition of buffer layer can be identical as the first insert layer, and this will not be detailed here.
Preferably, on substrate after grown buffer layer, which can also include:
High temperature buffer layer is grown on the buffer layer.
Correspondingly, n type semiconductor layer is grown on high temperature buffer layer.
Specifically, high temperature buffer layer is grown on the buffer layer, may include:
Controlled at 1000 DEG C~1200 DEG C (preferably 1100 DEG C), pressure be 100torr~500torr (preferably 300torr), high temperature buffer layer is grown on the buffer layer.
Optionally, before second step, which can also include:
The growth stress releasing layer on n type semiconductor layer.
Correspondingly, active layer is grown on stress release layer.
Specifically, the growth stress releasing layer on n type semiconductor layer may include:
Controlled at 800 DEG C~1100 DEG C (preferably 950 DEG C), pressure be 100torr~500torr (preferably 300torr), the growth stress releasing layer on n type semiconductor layer.
Optionally, after the 6th step, which can also include:
Contact layer is grown on p type semiconductor layer.
Specifically, contact layer is grown on p type semiconductor layer, may include:
Controlled at 850 DEG C~1050 DEG C (preferably 950 DEG C), pressure be 100torr~300torr (preferably 200torr), contact layer is grown on p type semiconductor layer.
It should be noted that after above-mentioned epitaxial growth terminates, can first by temperature be reduced to 650 DEG C~850 DEG C (preferably It is 750 DEG C), the annealing of 5 minutes~15 minutes (preferably 10 minutes) is carried out to epitaxial wafer in nitrogen atmosphere, then again The temperature of epitaxial wafer is reduced to room temperature.
Control temperature, pressure each mean temperature, pressure in the reaction chamber of control growth epitaxial wafer, and specially MOCVD is set Standby reaction chamber.Using trimethyl gallium or triethyl-gallium as gallium source when realization, high-purity ammonia is as nitrogen source, and trimethyl indium is as indium Source, for trimethyl aluminium as silicon source, silicon source selects silane, and two luxuriant magnesium are selected in magnesium source.
The foregoing is merely presently preferred embodiments of the present invention, is not intended to limit the invention, it is all in spirit of the invention and Within principle, any modification, equivalent replacement, improvement and so on be should all be included in the protection scope of the present invention.

Claims (10)

1. a kind of LED epitaxial slice, the LED epitaxial slice includes substrate, n type semiconductor layer, active layer, low Warm P-type layer, electronic barrier layer and p type semiconductor layer, it is the n type semiconductor layer, the active layer, the low temperature P-type layer, described Electronic barrier layer and the p type semiconductor layer stack gradually over the substrate；It is characterized in that, the LED epitaxial Piece further includes the first insert layer and the second insert layer stacked gradually, and first insert layer and second insert layer setting exist Between the active layer and the low temperature P-type layer；The material of first insert layer use undoped aluminium nitride, described second The material of insert layer uses the InGaN of p-type doping.
2. LED epitaxial slice according to claim 1, which is characterized in that the active layer includes stacking gradually Multiple composite constructions, each composite construction include that the Quantum Well stacked gradually and quantum are built；The material of the Quantum Well is adopted With undoped InGaN, the content of indium component is less than the content of indium component in the Quantum Well in second insert layer.
3. LED epitaxial slice according to claim 2, which is characterized in that the material of second insert layer uses Mix the In of MgxGa1-xN, 0.2 < x < 0.3.
4. LED epitaxial slice according to claim 3, which is characterized in that second insert layer with a thickness of 4nm~8nm.
5. LED epitaxial slice according to claim 4, which is characterized in that first insert layer with a thickness of institute State the 1/3~2/3 of the thickness of the second insert layer.
6. described in any item LED epitaxial slices according to claim 1~5, which is characterized in that second insert layer The doping concentration of middle P-type dopant is 5*1019/cm3~8*1019/cm3。
7. a kind of growing method of LED epitaxial slice, which is characterized in that the growing method includes:
One substrate is provided；
N type semiconductor layer, active layer, the first insert layer, the second insert layer, low temperature P-type layer, electricity are successively grown over the substrate Sub- barrier layer and p type semiconductor layer；
Wherein, the material of first insert layer uses undoped aluminium nitride, and the material of second insert layer is mixed using p-type Miscellaneous InGaN.
8. growing method according to claim 7, which is characterized in that the active layer include stack gradually it is multiple compound Structure, each composite construction include that the Quantum Well stacked gradually and quantum are built；The growth temperature of second insert layer is high In the growth temperature of the Quantum Well.
9. growing method according to claim 8, which is characterized in that the growth temperature of second insert layer is than the amount The growth temperature of sub- trap is 10 DEG C high~and 20 DEG C.
10. according to the described in any item growing methods of claim 7~9, which is characterized in that first insert layer uses physics Gas phase deposition technology is formed.
CN201811503410.2A 2018-12-10 2018-12-10 A kind of LED epitaxial slice and its growing method Withdrawn CN109768136A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201811503410.2A CN109768136A (en) 2018-12-10 2018-12-10 A kind of LED epitaxial slice and its growing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201811503410.2A CN109768136A (en) 2018-12-10 2018-12-10 A kind of LED epitaxial slice and its growing method

Publications (1)

Publication Number Publication Date
CN109768136A true CN109768136A (en) 2019-05-17

Family

ID=66451401

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201811503410.2A Withdrawn CN109768136A (en) 2018-12-10 2018-12-10 A kind of LED epitaxial slice and its growing method

Country Status (1)

Country Link
CN (1) CN109768136A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113764556A (en) * 2021-09-10 2021-12-07 圆融光电科技股份有限公司 Compound N type barrier layer of gallium nitride-based light emitting diode epitaxial wafer and gallium nitride-based light emitting diode epitaxial wafer
CN117476834A (en) * 2023-12-28 2024-01-30 江西兆驰半导体有限公司 Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113764556A (en) * 2021-09-10 2021-12-07 圆融光电科技股份有限公司 Compound N type barrier layer of gallium nitride-based light emitting diode epitaxial wafer and gallium nitride-based light emitting diode epitaxial wafer
CN117476834A (en) * 2023-12-28 2024-01-30 江西兆驰半导体有限公司 Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode
CN117476834B (en) * 2023-12-28 2024-03-22 江西兆驰半导体有限公司 Light-emitting diode epitaxial wafer, preparation method thereof and light-emitting diode

Similar Documents

Publication Publication Date Title
CN108550675B (en) A kind of LED epitaxial slice and preparation method thereof
CN109786529A (en) A kind of gallium nitride based LED epitaxial slice and preparation method thereof
CN109192831A (en) A kind of gallium nitride based LED epitaxial slice and preparation method thereof
CN109346576A (en) A kind of LED epitaxial slice and preparation method thereof
CN109860358A (en) A kind of gallium nitride based LED epitaxial slice and preparation method thereof
CN109216514A (en) A kind of gallium nitride based LED epitaxial slice and preparation method thereof
CN109860359A (en) A kind of gallium nitride based LED epitaxial slice and preparation method thereof
CN109256445A (en) A kind of gallium nitride based LED epitaxial slice and preparation method thereof
CN109346583A (en) A kind of LED epitaxial slice and preparation method thereof
CN109786530A (en) A kind of GaN base light emitting epitaxial wafer and preparation method thereof
CN109473516A (en) A kind of gallium nitride based LED epitaxial slice and its growing method
CN108987544B (en) Light emitting diode epitaxial wafer and manufacturing method thereof
CN109671817A (en) A kind of LED epitaxial slice and preparation method thereof
CN110364598A (en) LED epitaxial slice and preparation method thereof
CN109346568A (en) A kind of LED epitaxial slice and preparation method thereof
CN109473514A (en) A kind of gallium nitride based LED epitaxial slice and its manufacturing method
CN109768136A (en) A kind of LED epitaxial slice and its growing method
CN109103312A (en) A kind of gallium nitride based LED epitaxial slice and preparation method thereof
CN109309150A (en) A kind of gallium nitride based LED epitaxial slice and preparation method thereof
CN109192826B (en) A kind of LED epitaxial slice and preparation method thereof
CN109473521A (en) A kind of LED epitaxial slice and preparation method thereof
CN109686823A (en) A kind of gallium nitride based LED epitaxial slice and preparation method thereof
CN109087977A (en) A kind of gallium nitride based LED epitaxial slice and preparation method thereof
CN109830582A (en) LED epitaxial slice and its growing method
CN109346577A (en) A kind of gallium nitride based LED epitaxial slice and preparation method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
WW01 Invention patent application withdrawn after publication
WW01 Invention patent application withdrawn after publication

Application publication date: 20190517