CN109671817A - A kind of LED epitaxial slice and preparation method thereof - Google Patents
A kind of LED epitaxial slice and preparation method thereof Download PDFInfo
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- CN109671817A CN109671817A CN201811412842.2A CN201811412842A CN109671817A CN 109671817 A CN109671817 A CN 109671817A CN 201811412842 A CN201811412842 A CN 201811412842A CN 109671817 A CN109671817 A CN 109671817A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/12—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0075—Processes for devices with an active region comprising only III-V compounds comprising nitride compounds
Abstract
The invention discloses a kind of LED epitaxial slices and preparation method thereof, belong to technical field of semiconductors.Epitaxial wafer includes substrate, n type semiconductor layer, active layer and p type semiconductor layer, and active layer includes multiple composite constructions, and composite construction includes well layer and barrier layer；Several well layer near p type semiconductor layer are the first well layer, and the first well layer includes the first sublayer, the second sublayer and third sublayer；Well layer in addition to the first well layer is the second well layer, and the second well layer includes the 4th sublayer, the 5th sublayer and the 6th sublayer；The material of second sublayer and the material of the 5th sublayer are all made of InxGa1‑xN, the material of the first sublayer and the material of third sublayer are all made of AlaInbGa1‑a‑bN, the material of the 4th sublayer and the material of the 6th sublayer are all made of AlcIndGa1‑c‑dN, x, a, b, c, d are the positive number less than 1, (a/b) < (c/d).The luminous efficiency of epitaxial wafer can be improved in the present invention.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of LED epitaxial slice and preparation method thereof.
Background technique
Light emitting diode (English: Light Emitting Diode, referred to as: LED) it is a kind of semi-conductor electricity that can be luminous
Subcomponent.LED has many advantages, such as that high-efficient, the service life is long, small in size, low in energy consumption, can be applied to indoor and outdoor white-light illuminating, screen
The fields such as display, backlight.In the development of LED industry, gallium nitride (GaN) sill is V-III compound semiconductor
Typical Representative, the photoelectric properties for improving GaN base LED have become the key of semiconductor lighting industry.
Epitaxial wafer is the primary finished product in LED preparation process.Existing GaN base LED epitaxial wafer includes that substrate, N-type are partly led
Body layer, active layer and p type semiconductor layer, n type semiconductor layer, active layer and p type semiconductor layer stack gradually on substrate.Substrate
For providing growing surface for epitaxial material, n type semiconductor layer is used to provide the electronics for carrying out recombination luminescence, p type semiconductor layer
For providing the hole for carrying out recombination luminescence, the radiation recombination that active layer is used to carry out electrons and holes shines.
In the implementation of the present invention, the inventor finds that the existing technology has at least the following problems:
Active layer includes multiple well layer and multiple barrier layer, and multiple well layer and the alternately laminated setting of multiple barrier layer, barrier layer will be infused
The electrons and holes for entering active layer, which are limited in well layer, carries out recombination luminescence.The material of usual well layer uses the nitridation of high indium component
The material of indium gallium (InGaN), barrier layer uses gallium nitride (GaN).Since the lattice constant of gallium nitride is 3.181, the crystalline substance of indium nitride
Lattice constant is 3.538, therefore there are biggish lattice mismatch between well layer and barrier layer, the stress that lattice mismatch generates will affect electricity
Son and hole cause the luminous efficiency of LED lower in the combined efficiency in space.
Summary of the invention
The embodiment of the invention provides a kind of LED epitaxial slices and preparation method thereof, are able to solve prior art trap
There is a problem of that biggish lattice mismatch causes the luminous efficiency of LED lower between layer and barrier layer.The technical solution is as follows:
On the one hand, the embodiment of the invention provides a kind of LED epitaxial slice, the LED epitaxial slice packets
Include substrate, n type semiconductor layer, active layer and p type semiconductor layer, the n type semiconductor layer, the active layer and the p-type half
Conductor layer stacks gradually over the substrate；The active layer includes the multiple composite constructions stacked gradually, each described compound
Structure includes well layer and the barrier layer that is layered in the well layer；Near the several of the p type semiconductor layer in the active layer
Well layer is the first well layer, and first well layer includes the first sublayer, the second sublayer and third sublayer stacked gradually；It is described active
Well layer in addition to first well layer is the second well layer in layer, and second well layer includes the 4th sublayer stacked gradually, the
Five sublayers and the 6th sublayer；The material of second sublayer and the material of the 5th sublayer are all made of InxGa1-xN, described
The material of one sublayer and the material of the third sublayer are all made of AlaInbGa1-a-bN, the material of the 4th sublayer and described
The material of six sublayers is all made of AlcIndGa1-c-dN, x, a, b, c, d are the positive number less than 1, (a/b) < (c/d).
Optionally, (a/b) > (4/9).
Optionally, the thickness of first sublayer is less than the thickness of second sublayer, and the thickness of second sublayer is big
In the thickness of the third sublayer；The thickness of 4th sublayer is less than the thickness of the 5th sublayer, the 5th sublayer
Thickness is greater than the thickness of the 6th sublayer.
Preferably, 5 times~10 times of the thickness with a thickness of first sublayer of second sublayer, second sublayer
5 times~10 times of the thickness with a thickness of the third sublayer；The thickness with a thickness of the 4th sublayer of 5th sublayer
5 times~10 times, 5 times~10 times of the thickness with a thickness of the 6th sublayer of the 5th sublayer.
It is highly preferred that the thickness of second sublayer is greater than the thickness of the 5th sublayer；The thickness of first sublayer,
The thickness of the thickness of the third sublayer, the thickness of the 4th sublayer and the 6th sublayer is equal.
Optionally, the quantity of first well layer is 1/5~1/2 of well layer sum in the active layer.
Preferably, the quantity of first well layer is 1~5.
It is highly preferred that the quantity of second well layer is 4~8.
On the other hand, the embodiment of the invention provides a kind of preparation method of LED epitaxial slice, the preparation sides
Method includes:
One substrate is provided；
N type semiconductor layer, active layer and p type semiconductor layer are successively grown over the substrate；
Wherein, the active layer includes the multiple composite constructions stacked gradually, each composite construction include well layer and
The barrier layer being layered in the well layer；In the active layer near several well layer of the p type semiconductor layer be the first well layer,
First well layer includes the first sublayer, the second sublayer and third sublayer stacked gradually；Described first is removed in the active layer
Well layer except well layer is the second well layer, and second well layer includes the 4th sublayer stacked gradually, the 5th sublayer and the 6th son
Layer；The material of second sublayer and the material of the 5th sublayer are all made of InxGa1-xN, the material of first sublayer and
The material of the third sublayer is all made of AlaInbGa1-a-bN, the material of the 4th sublayer and the material of the 6th sublayer are equal
Using AlcIndGa1-c-dN, x, a, b, c, d are the positive number less than 1, (a/b) < (c/d).
Optionally, the growth temperature of the growth temperature of second sublayer and the 5th sublayer is T1, first son
The growth temperature of layer and the growth temperature of the third sublayer are T2, the growth temperature and the 6th sublayer of the 4th sublayer
Growth temperature be T3, the growth temperature of the barrier layer is T4, T1≤T2=T3 < T4.
Technical solution provided in an embodiment of the present invention has the benefit that
By being arranged AlInGaN layers in the two sides of InGaN layer, AlInGaN layers be can be used as between InGaN layer and barrier layer
Buffer layer can effectively adjust the band gap between InGaN layer and barrier layer by adjusting the content of Al component and the content of In component
Width and lattice match alleviate the lattice mismatch between well layer and barrier layer, reduce polarity mismatch, improve the spoke of electrons and holes
Combined efficiency is penetrated, the final luminous efficiency for improving LED.AlInGaN layer of energy band height is higher than InGaN layer simultaneously, can will be electric
Son and hole, which are preferably limited in InGaN layer, carries out radiation recombination, further increases the radiation recombination efficiency of electrons and holes,
The final luminous efficiency for improving LED.And the content of Al component is higher than close to p-type in the AlInGaN layer of n type semiconductor layer
On the one hand the counterguard effect to electronics can be improved in the content of Al component in the AlInGaN layer of semiconductor layer, reduce electronics and overflow
Stream；On the other hand electrons and holes can be allowed to concentrate on carrying out radiation recombination in several well layer of P-type semiconductor, thus
Improve the internal quantum efficiency of epitaxial wafer.
Detailed description of the invention
To describe the technical solutions in the embodiments of the present invention more clearly, make required in being described below to embodiment
Attached drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the invention, for
For those of ordinary skill in the art, without creative efforts, it can also be obtained according to these attached drawings other
Attached drawing.
Fig. 1 is a kind of structural schematic diagram of LED epitaxial slice provided in an embodiment of the present invention；
Fig. 2 is the structural schematic diagram of active layer provided in an embodiment of the present invention；
Fig. 3 is the structural schematic diagram of the first well layer provided in an embodiment of the present invention；
Fig. 4 is the structural schematic diagram of the second well layer provided in an embodiment of the present invention；
Fig. 5 is a kind of flow chart of the preparation method of LED epitaxial slice provided in an embodiment of the present invention.
Specific embodiment
To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with attached drawing to embodiment party of the present invention
Formula is described in further detail.
The embodiment of the invention provides a kind of LED epitaxial slices.Fig. 1 is a kind of hair provided in an embodiment of the present invention
The structural schematic diagram of optical diode epitaxial wafer.Referring to Fig. 1, which includes substrate 10, n type semiconductor layer
20, active layer 30 and p type semiconductor layer 40, n type semiconductor layer 20, active layer 30 and p type semiconductor layer 40 are sequentially laminated on lining
On bottom 10.
Fig. 2 is the structural schematic diagram of active layer provided in an embodiment of the present invention.Referring to fig. 2, in the present embodiment, active layer
30 include the multiple composite constructions 31 stacked gradually, and each composite construction 31 includes well layer 32 and the barrier layer being layered in well layer 32
33.In active layer 30 near several well layer 32 of p type semiconductor layer be the first well layer.For example, partly being led in Fig. 2 near p-type
Two well layer 32 of body layer are the first well layer, and three well layer near n type semiconductor layer are not the first well layer (using different
The first well layer of graphical representation and non-first well layer).
Fig. 3 is the structural schematic diagram of the first well layer provided in an embodiment of the present invention.Referring to Fig. 3, the first well layer includes successively
The first sublayer 32a, the second sublayer 32b and the third sublayer 32c of stacking.Well layer 32 in active layer in addition to the first well layer is the
Two well layer.Fig. 4 is the structural schematic diagram of the second well layer provided in an embodiment of the present invention.Referring to fig. 4, the second well layer 32 includes successively
The 4th sublayer 32d, the 5th sublayer 32e and the 6th sublayer 32f of stacking.The material of second sublayer 32b and the material of the 5th sublayer 32e
Material is all made of InxGa1-xThe material of N, the first sublayer 32a and the material of third sublayer 32c are all made of AlaInbGa1-a-bN, the 4th son
The material of layer 32d and the material of the 6th sublayer 32f are all made of AlcIndGa1-c-dN, x, a, b, c, d are the positive number less than 1, (a/
B) < (c/d).
For the embodiment of the present invention by being arranged AlInGaN layers in the two sides of InGaN layer, AlInGaN layers can be used as InGaN layer
Buffer layer between barrier layer can effectively adjust InGaN layer and base by adjusting the content of Al component and the content of In component
Band gap width and lattice match between layer alleviate the lattice mismatch between well layer and barrier layer, reduce polarity mismatch, improve electricity
The radiation recombination efficiency of son and hole, the final luminous efficiency for improving LED.AlInGaN layers of energy band height is higher than InGaN simultaneously
Layer, electrons and holes can be preferably limited in InGaN layer and carry out radiation recombination, further increase the spoke of electrons and holes
Combined efficiency is penetrated, the final luminous efficiency for improving LED.And close to n type semiconductor layer AlInGaN layer in Al component content
Higher than the content of the Al component in the AlInGaN layer of p type semiconductor layer, the counterguard effect to electronics on the one hand can be improved,
Reduce electronics overflow；On the other hand electrons and holes can be allowed to concentrate on carrying out spoke in several well layer of P-type semiconductor
Penetrate it is compound, to improve the internal quantum efficiency of epitaxial wafer.
Optionally, 0.02≤x≤0.06, such as x=0.03.InGaN layer and barrier layer can effectively be adjusted due to AlInGaN layers
Between lattice match, therefore the content of In component can be improved in InGaN layer, to improve the radiation recombination effect of carrier
Rate, and then promote the photoelectric properties of epitaxial wafer.
Optionally, (a/b) > (4/9), such as (a/b)=0.6, (c/d)=0.7.AlInGaN layers of potential barrier is higher than barrier layer
Potential barrier, is conducive to be limited to electrons and holes in InGaN layer and carries out recombination luminescence.
Optionally, the thickness of the first sublayer 32a can be less than the thickness of the second sublayer 32b, and the thickness of the second sublayer 32b can
To be greater than the thickness of third sublayer 32c；The thickness of 4th sublayer 32d can be less than the thickness of the 5th sublayer 32e, the 5th sublayer
The thickness of 32e can be greater than the thickness of the 6th sublayer 32f.InGaN layer is most thick, and the radiation recombination for being conducive to improve carrier is general
Rate, and then promote the photoelectric properties of epitaxial wafer.
Preferably, the thickness of the second sublayer 32b can be 5 times~10 times of the thickness of the first sublayer 32a, such as 30 times；The
The thickness of two sublayer 32b can be 5 times~10 times of the thickness of third sublayer 32c, such as 8 times.The thickness of 5th sublayer 32e can be with
It is 5 times~10 times of the thickness of the 4th sublayer 32d, such as 8 times；The thickness of 5th sublayer 32e can be the thickness of the 6th sublayer 32f
5 times~10 times, such as 8 times.The radiation recombination efficiency that InGaN layer improves carrier is efficiently used, while reducing InGaN as far as possible
Lattice mismatch between layer and barrier layer.
It is highly preferred that the thickness of the second sublayer 32b can be greater than the thickness of the 5th sublayer 32e, the thickness of the first sublayer 32a
The thickness of degree, the thickness of third sublayer 32c, the thickness of the 4th sublayer 32d and the 6th sublayer 32f can be equal.It is partly led close to p-type
The InGaN layer of body layer is thicker, and more holes and electron concentration can be allowed in several well layer progress near p type semiconductor layer
Radiation recombination improves the radiation recombination efficiency of active layer entirety, and then improves the internal quantum efficiency of epitaxial wafer, finally improves LED
Luminous efficiency.
Specifically, the thickness of the first sublayer 32a can be 0.3nm~0.5nm, such as 0.4nm；The thickness of second sublayer 32b
It can be 3nm~4nm, such as 3.5nm；The thickness of third sublayer 32c can be 0.3nm~0.5nm, such as 0.4nm.4th sublayer
The thickness of 32d can be 0.3nm~0.5nm, such as 0.4nm；The thickness of 5th sublayer 32e can be 2.5nm~3.5nm, such as
3nm；The thickness of 6th sublayer 32f can be 0.3nm~0.5nm, such as 0.4nm.
Optionally, the quantity of the first well layer can be 1/5~1/2 of well layer sum in active layer, such as 1/4, be conducive to carry
Stream concentrates on several well layer radiation recombinations near p type semiconductor layer, improves the radiation recombination efficiency of active layer entirety.
Preferably, the quantity of the first well layer can be 1~5, such as 4, and practical application effect is good.
Preferably, the quantity of the second well layer can be 4~8, such as 5, and practical application effect is good.
Optionally, the material of barrier layer 33 can use undoped gallium nitride, can also using n-type doping (such as silicon or
Germanium) gallium nitride.When the material of barrier layer uses the gallium nitride of n-type doping, is conducive to the migration of electronics, improves the spoke of active layer
Penetrate combined efficiency.
Preferably, the material of the adjacent barrier layer 33 of the first well layer can use undoped gallium nitride, and the second well layer is adjacent
Barrier layer 33 material can use n-type doping gallium nitride, be conducive to electrons and holes and concentrate near p type semiconductor layer
Several well layer radiation recombinations, improve active layer entirety radiation recombination efficiency.
Further, when the material of barrier layer 33 uses the gallium nitride of n-type doping, the doping of N type dopant in barrier layer 33
Concentration can be 1017/cm3~1017/cm3, such as 1018/cm3.Both the mobility of electronics can be improved, will not influence active
The crystal structure of layer.
Specifically, the quantity of composite construction 31 can be 5~13, can satisfy the compound needs of carrier.
Specifically, the material of substrate 10 can use sapphire (main material is aluminum oxide), silicon or silicon carbide.
The material of n type semiconductor layer 20 can use the gallium nitride of n-type doping (such as silicon or germanium).The material of p type semiconductor layer 40 can be with
Using the gallium nitride of p-type doping (such as magnesium).
Further, the thickness of n type semiconductor layer 20 can be 1 μm~5 μm, preferably 3 μm；N in n type semiconductor layer 20
The doping concentration of type dopant can be 1018cm-3~9*1019cm-3, preferably 1019cm-3.The thickness of p type semiconductor layer 40 can
Think 100nm~300nm, preferably 200nm；The doping concentration of P-type dopant can be 10 in p type semiconductor layer 4018/cm3
~1020/cm3, preferably 1019/cm3。
Optionally, as shown in Figure 1, the LED epitaxial slice can also include buffer layer 51, the setting of buffer layer 51 exists
Between substrate 10 and n type semiconductor layer 20, to alleviate the stress and defect that lattice mismatch generates between substrate material and gallium nitride,
And nuclearing centre is provided for gallium nitride material epitaxial growth.
Specifically, the material of buffer layer 51 can use gallium nitride or aluminium nitride.
Further, the thickness of buffer layer 51 can be 15nm~35nm, preferably 25nm.
Preferably, undoped as shown in Figure 1, the LED epitaxial slice can also include undoped gallium nitride layer 52
Gallium nitride layer 52 is arranged between buffer layer 51 and n type semiconductor layer 20, further to alleviate between substrate material and gallium nitride
The stress and defect that lattice mismatch generates, provide crystal quality preferable growing surface for epitaxial wafer main structure.
In specific implementation, buffer layer is the gallium nitride of the layer of low-temperature epitaxy first in patterned substrate, because
This is also referred to as low temperature buffer layer.The longitudinal growth for carrying out gallium nitride in low temperature buffer layer again, will form multiple mutually independent three
Island structure is tieed up, referred to as three-dimensional nucleating layer；Then it is carried out between each three-dimensional island structure on all three-dimensional island structures
The cross growth of gallium nitride forms two-dimension plane structure, referred to as two-dimentional retrieving layer；The finally high growth temperature one on two-dimensional growth layer
The thicker gallium nitride of layer, referred to as intrinsic gallium nitride layer.By three-dimensional nucleating layer, two-dimentional retrieving layer and intrinsic gallium nitride in the present embodiment
Layer is referred to as undoped gallium nitride layer.
Further, the thickness of undoped gallium nitride layer 52 can be 1 μm~3 μm, preferably 2 μm.
Optionally, as shown in Figure 1, the LED epitaxial slice can also include stress release layer 60, stress release layer
60 are arranged between n type semiconductor layer 20 and active layer 30, with the stress generated to lattice mismatch between sapphire and gallium nitride
It is discharged, improves the crystal quality of active layer, be conducive to electrons and holes and shine in active layer progress radiation recombination, improve
The internal quantum efficiency of LED, and then improve the luminous efficiency of LED.
Specifically, stress release layer 60 can be gallium indium aluminum nitrogen (AlInGaN) layer, can be released effectively sapphire and nitridation
The stress that gallium lattice mismatch generates, improves the crystal quality of epitaxial wafer, improves the luminous efficiency of LED.
Further, the thickness of stress release layer 60 can be 50nm~500nm, preferably 300nm.
Optionally, as shown in Figure 1, the gallium nitride based LED epitaxial slice can also include electronic barrier layer 71, electricity
Sub- barrier layer 71 is arranged between active layer 30 and p type semiconductor layer 40, to avoid electron transition into p type semiconductor layer with sky
Cave carries out non-radiative recombination, reduces the luminous efficiency of LED.
Specifically, the material of electronic barrier layer 71 can be using the aluminium gallium nitride alloy of p-type doping, such as AlyGa1-yN, 0.1 < y
< 0.5.
Further, the thickness of electronic barrier layer 71 can be 50nm~150nm, preferably 100nm.
Preferably, as shown in Figure 1, the gallium nitride based LED epitaxial slice can also include low temperature P-type layer 72, low temperature
P-type layer 72 is arranged between active layer 30 and electronic barrier layer 71, has caused to avoid the higher growth temperature of electronic barrier layer
Phosphide atom in active layer is precipitated, and influences the luminous efficiency of light emitting diode.
Specifically, the material of low temperature P-type layer 72 can be identical as the material of p type semiconductor layer 40.In the present embodiment,
The material of low temperature P-type layer 72 can be the gallium nitride of p-type doping.
Further, the thickness of low temperature P-type layer 72 can be 10nm~50nm, preferably 30nm；P in low temperature P-type layer 72
The doping concentration of type dopant can be 1018/cm3~1020/cm3, preferably 1019/cm3。
Optionally, as shown in Figure 1, the LED epitaxial slice can also include contact layer 80, contact layer 80 is arranged in P
In type semiconductor layer 40, to form Ohmic contact between the electrode or transparent conductive film that are formed in chip fabrication technique.
Specifically, the material of contact layer 80 can be using the InGaN or gallium nitride of p-type doping.
Further, the thickness of contact layer 80 can be 5nm~300nm, preferably 100nm；P-type is adulterated in contact layer 80
The doping concentration of agent can be 1021/cm3~1022/cm3, preferably 5*1021/cm3。
The embodiment of the invention provides a kind of preparation method of LED epitaxial slice, it is suitable for preparing shown in FIG. 1
LED epitaxial slice.Fig. 5 is a kind of process of the preparation method of LED epitaxial slice provided in an embodiment of the present invention
Figure.Referring to Fig. 5, which includes:
Step 201: a substrate is provided.
Optionally, which may include:
Clean the surface of substrate.
Specifically, the surface for cleaning substrate may include:
Controlled at 1110 DEG C, 8~10 minutes annealings are carried out to substrate in hydrogen atmosphere.
Step 202: successively growing n type semiconductor layer, active layer and p type semiconductor layer on substrate.
In the present embodiment, active layer includes the multiple composite constructions stacked gradually, each composite construction include well layer and
The barrier layer being layered in well layer；It near several well layer of p type semiconductor layer is the first well layer in active layer, the first well layer includes
The first sublayer, the second sublayer and the third sublayer stacked gradually；Well layer in active layer in addition to the first well layer is the second well layer,
Second well layer includes the 4th sublayer, the 5th sublayer and the 6th sublayer stacked gradually；The material of second sublayer and the 5th sublayer
Material is all made of InxGa1-xN, the material of the first sublayer and the material of third sublayer are all made of AlaInbGa1-a-bN, the 4th sublayer
Material and the material of the 6th sublayer are all made of AlcIndGa1-c-dN, x, a, b, c, d are the positive number less than 1, (a/b) < (c/d).
Optionally, the growth temperature of the growth temperature of the second sublayer and the 5th sublayer is T1, the growth temperature of the first sublayer
Growth temperature with third sublayer is T2, and the growth temperature of the 4th sublayer and the growth temperature of the 6th sublayer are T3, the life of barrier layer
Long temperature is T4, T1≤T2=T3 < T4.The growth temperature of InGaN layer is minimum, it is possible to prevente effectively from In is parsed at high temperature, protects
The content for demonstrate,proving In component avoids the emission wavelength for influencing epitaxial wafer；The growth temperature highest of barrier layer, it is ensured that barrier layer is preferable
Crystal quality；AlInGaN layers of growth temperature both can guarantee AlInGaN layers of crystal matter between barrier layer and InGaN layer
Amount, the In parsing being also avoided that in InGaN layer.
Specifically, 780 DEG C≤T1≤820 DEG C, such as T1=800 DEG C；820 DEG C≤T2≤840 DEG C, such as T2=820 DEG C；820
DEG C≤T3≤840 DEG C, such as T3=820 DEG C；845 DEG C≤T4≤875 DEG C, such as T4=860 DEG C, realize that effect is preferable.
Specifically, which may include:
The first step, controlled at 1050 DEG C~1100 DEG C (preferably 1080 DEG C), pressure is 100torr~500torr
(preferably 300torr), grows n type semiconductor layer on substrate；
Second step, control pressure are 100torr~500torr (preferably 300torr), are grown on n type semiconductor layer
Active layer；
Third step, controlled at 850 DEG C~1080 DEG C (preferably 960 DEG C), pressure is that 100torr~300torr is (excellent
It is selected as 200torr), the growing P-type semiconductor layer on active layer.
Optionally, before the first step, which can also include:
Buffer layer is formed on the substrate.
Correspondingly, n type semiconductor layer is grown on the buffer layer.
Specifically, buffer layer is formed on the substrate, may include:
Using physical vapour deposition (PVD) (English: Physical Vapor Deposition, abbreviation: PVD), technology is on substrate
Form buffer layer.
Preferably, on substrate after grown buffer layer, which can also include:
Undoped gallium nitride layer is grown on the buffer layer.
Correspondingly, n type semiconductor layer is grown on undoped gallium nitride layer.
Specifically, undoped gallium nitride layer is grown on the buffer layer, may include:
Controlled at 1000 DEG C~1200 DEG C (preferably 1100 DEG C), pressure be 100torr~500torr (preferably
300torr), undoped gallium nitride layer is grown on the buffer layer.
Optionally, before second step, which can also include:
The growth stress releasing layer on n type semiconductor layer.
Correspondingly, active layer is grown on stress release layer.
Specifically, the growth stress releasing layer on n type semiconductor layer may include:
Controlled at 800 DEG C~1100 DEG C (preferably 950 DEG C), pressure be 100torr~500torr (preferably
300torr), the growth stress releasing layer on n type semiconductor layer.
Optionally, before third step, which can also include:
Electronic barrier layer is grown on active layer.
Correspondingly, p type semiconductor layer is grown on electronic barrier layer.
Specifically, electronic barrier layer is grown on active layer, may include:
Controlled at 850 DEG C~1080 DEG C (preferably 960 DEG C), pressure be 200torr~500torr (preferably
350torr), electronic barrier layer is grown on active layer.
Preferably, before growing electronic barrier layer on active layer, which can also include:
The growing low temperature P-type layer on active layer.
Correspondingly, electronic barrier layer is grown in low temperature P-type layer.
Specifically, the growing low temperature P-type layer on active layer may include:
Controlled at 600 DEG C~850 DEG C (preferably 750 DEG C), pressure be 100torr~600torr (preferably
300torr), the growing low temperature P-type layer on active layer.
Optionally, after third step, which can also include:
Contact layer is grown on p type semiconductor layer.
Specifically, contact layer is grown on p type semiconductor layer, may include:
Controlled at 850 DEG C~1050 DEG C (preferably 950 DEG C), pressure be 100torr~300torr (preferably
200torr), contact layer is grown on p type semiconductor layer.
It should be noted that after above-mentioned epitaxial growth terminates, can first by temperature be reduced to 650 DEG C~850 DEG C (preferably
It is 750 DEG C), the annealing of 5 minutes~15 minutes (preferably 10 minutes) is carried out to epitaxial wafer in nitrogen atmosphere, then again
The temperature of epitaxial wafer is reduced to room temperature.
Control temperature, pressure each mean temperature, pressure in the reaction chamber of control growth epitaxial wafer, and specially metal is organic
Compound chemical gaseous phase deposition (English: Metal-organic Chemical Vapor Deposition, referred to as: MOCVD) set
Standby reaction chamber.High-purity H can be used when realization2Or N2As carrier gas, be respectively adopted TEGa or TMGa, TMAl, TMIn and
NH3Respectively as the source Ga, the source Al, the source In and the source N, and SiH can be respectively adopted4And Cp2Mg is as N-type and P-type dopant, also
TeESi (silicon tetraethyl) and Si can be used2H6As the source Si.
The foregoing is merely presently preferred embodiments of the present invention, is not intended to limit the invention, it is all in spirit of the invention and
Within principle, any modification, equivalent replacement, improvement and so on be should all be included in the protection scope of the present invention.
Claims (10)
1. a kind of LED epitaxial slice, the LED epitaxial slice includes substrate, n type semiconductor layer, active layer and P
Type semiconductor layer, the n type semiconductor layer, the active layer and the p type semiconductor layer stack gradually over the substrate；Institute
Stating active layer includes the multiple composite constructions stacked gradually, and each composite construction includes well layer and is layered in the well layer
Barrier layer；It is characterized in that, in the active layer near several well layer of the p type semiconductor layer be the first well layer, it is described
First well layer includes the first sublayer, the second sublayer and third sublayer stacked gradually；First well layer is removed in the active layer
Except well layer be the second well layer, second well layer includes the 4th sublayer, the 5th sublayer and the 6th sublayer stacked gradually；Institute
The material of the material and the 5th sublayer of stating the second sublayer is all made of InxGa1-xN, the material of first sublayer and described
The material of three sublayers is all made of AlaInbGa1-a-bN, the material of the 4th sublayer and the material of the 6th sublayer are all made of
AlcIndGa1-c-dN, x, a, b, c, d are the positive number less than 1, (a/b) < (c/d).
2. LED epitaxial slice according to claim 1, which is characterized in that (a/b) > (4/9).
3. LED epitaxial slice according to claim 1 or 2, which is characterized in that the thickness of first sublayer is small
In the thickness of second sublayer, the thickness of second sublayer is greater than the thickness of the third sublayer；4th sublayer
Thickness is less than the thickness of the 5th sublayer, and the thickness of the 5th sublayer is greater than the thickness of the 6th sublayer.
4. LED epitaxial slice according to claim 3, which is characterized in that second sublayer with a thickness of described
5 times of the thickness of first sublayer~10 times, 5 times~10 times of the thickness with a thickness of the third sublayer of second sublayer；
5 times~10 times of the thickness with a thickness of the 4th sublayer of 5th sublayer, the 5th sublayer with a thickness of described
5 times of the thickness of six sublayers~10 times.
5. LED epitaxial slice according to claim 4, which is characterized in that the thickness of second sublayer is greater than institute
State the thickness of the 5th sublayer；The thickness of first sublayer, the thickness of the third sublayer, the thickness of the 4th sublayer and institute
The thickness for stating the 6th sublayer is equal.
6. LED epitaxial slice according to claim 1 or 2, which is characterized in that the quantity of first well layer is
The 1/5~1/2 of well layer sum in the active layer.
7. LED epitaxial slice according to claim 6, which is characterized in that the quantity of first well layer is 1
~5.
8. LED epitaxial slice according to claim 7, which is characterized in that the quantity of second well layer is 4
~8.
9. a kind of preparation method of LED epitaxial slice, which is characterized in that the preparation method includes:
One substrate is provided；
N type semiconductor layer, active layer and p type semiconductor layer are successively grown over the substrate；
Wherein, the active layer includes the multiple composite constructions stacked gradually, and each composite construction includes well layer and stacking
Barrier layer in the well layer；In the active layer near several well layer of the p type semiconductor layer be the first well layer, it is described
First well layer includes the first sublayer, the second sublayer and third sublayer stacked gradually；First well layer is removed in the active layer
Except well layer be the second well layer, second well layer includes the 4th sublayer, the 5th sublayer and the 6th sublayer stacked gradually；Institute
The material of the material and the 5th sublayer of stating the second sublayer is all made of InxGa1-xN, the material of first sublayer and described
The material of three sublayers is all made of AlaInbGa1-a-bN, the material of the 4th sublayer and the material of the 6th sublayer are all made of
AlcIndGa1-c-dN, x, a, b, c, d are the positive number less than 1, (a/b) < (c/d).
10. preparation method according to claim 9, which is characterized in that the growth temperature of second sublayer and described
The growth temperature of five sublayers is T1, and the growth temperature of the growth temperature of first sublayer and the third sublayer is T2, described
The growth temperature of the growth temperature of 4th sublayer and the 6th sublayer is T3, and the growth temperature of the barrier layer is T4, T1≤T2
=T3 < T4.
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