CN109768080B - 一种具有mos控制空穴通路的igbt器件 - Google Patents

一种具有mos控制空穴通路的igbt器件 Download PDF

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CN109768080B
CN109768080B CN201910062000.7A CN201910062000A CN109768080B CN 109768080 B CN109768080 B CN 109768080B CN 201910062000 A CN201910062000 A CN 201910062000A CN 109768080 B CN109768080 B CN 109768080B
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igbt
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CN109768080A (zh
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李泽宏
彭鑫
赵一尚
任敏
张波
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University of Electronic Science and Technology of China
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Abstract

本发明提供一种具有MOS控制空穴通路的IGBT器件，属于功率半导体器件技术领域，本发明在传统IGBT器件的P+浮空pbody区内引入由栅介质层、MOS控制栅电极和P‑型MOS沟道区形成的MOS控制栅结构，MOS区等效为受到栅压控制作用的开关；在器件正向导通时使得pbody区电位浮空，实现空穴存储，降低了器件的饱和导通压降；在器件关断和短路条件下，提供了空穴的泄放通路，降低密勒电容，实现了低关断损耗和更稳固的短路能力。

Description

一种具有MOS控制空穴通路的IGBT器件
技术领域
本发明属于功率半导体器件技术领域，具体涉及一种具有MOS控制空穴通路的IGBT器件。
背景技术
绝缘栅双极晶体管(Insulated Gate Bipolar Transistor，IGBT)凭借着栅极易驱动、输入阻抗高、电流密度大、饱和压降低等优点，广泛应用在轨道交通、智能电网、风力发电等重要领域，已成为中高功率范围内的主流功率开关器件之一，同时还将继续朝着高压大电流、低功率损耗、高工作温度和高可靠性等方向发展。
平面栅结构是高压IGBT常采用的成熟结构，用于高铁、电力输运等对可靠性要求很高的环境，但平面栅型IGBT因为寄生MOS电阻，相比于槽栅型结构，其饱和压降大，增加了通态损耗；而槽栅型IGBT(Trench IGBT，TIGBT)元胞间距小，电流密度大，已成为降低导通损耗的常用结构。但是TIGBT在槽栅底部存在电场聚集现象，限制了阻断电压的提高，同时其短路电流较大，抗短路能力较弱；可通过在槽栅底部引入P-floating屏蔽层可降低电场峰值，但会引入额外的MOS电阻会使器件损耗增加；在槽栅间的P基区中同时引入钳位二极管，能同时改善关断损耗和导通压降(Eoff-Vcesat)折衷关系和强化器件短路承受能力，但现有方案多集中于1200V电压等级。通过采用宽槽栅间距或FP(Floating-Pbody)区域能降低器件电流密度，明显提高TIGBT的短路承受能力，然而FP结构的槽栅型IGBT(FP-TIGBT)因为负栅电容效应，通过密勒电容Cgc在栅极产生位移电流，引发控制栅压的波动，降低IGBT的栅极控制能力，同时会带来EMI噪声问题。
在1700V及其以下电压等级，通过Fin p-Body、Shield trench和Side-gate等结构能够改善EMI问题，但其对制造工艺精度要求严格；对于大于2500V电压等级的IGBT，国外IGBT供应商已经推出了3300V-TIGBT产品，其基本结构是通过内置结深超过槽栅深度的分立浮空P区(Separate Floating Pbody)，起到降低槽栅底部电场峰值和增强电导调制的作用，改善Eoff-Vcesat折衷关系，但分立浮空FP区会影响器件耐压和导通压降；而将分立FP通过固定电阻与地相连，提供部分空穴通路，易造成导通损耗增大，使得设计时的折衷窗口减小。
发明内容
鉴于上文所述，本发明针对现有分立浮空P区的槽栅IGBT器件存在P区电位变化致使器件耐压降低、开关损耗较大等问题，提供一种具有MOS控制空穴通路的IGBT器件。通过在分立FP中内置MOS结构形成空穴载流子泄放通路的控制结构；等效为可变电阻，能够在保证提高器件耐压可靠性、降低密勒电容的同时，降低器件关断损耗和短路承受能力。
为实现上述发明目的，本发明技术方案如下：
一种具有MOS控制空穴通路的IGBT器件，其元胞结构包括从下至上依次层叠的金属集电极7、P+集电区6、N型缓冲层5、N-漂移区4和金属发射极11；所述N-漂移区4的顶层中间区域设有P+浮空pbody区8，所述P+浮空pbody区8的两侧分别设有P+基区2，所述P+基区2的顶层设有N+发射区1；所述P+基区2和N+发射区1通过金属发射极11相接触；所述P+基区2和N+发射区1两者与P+浮空pbody区8之间设有IGBT栅极结构，P+浮空pbody区8和所述栅极结构不相邻，所述栅极结构包括栅电极9和栅介质层3，栅介质层3沿器件垂直方向延伸进入N-漂移区4中形成沟槽，所述栅电极9设置在沟槽中；所述栅介质层3的一侧与P+基区2、N+发射区1和N-漂移区4接触，所述栅介质层3的另一侧与P+浮空pbody区8通过N-漂移区4相隔离；所述P+浮空pbody区8中还设有栅介质层3、MOS控制栅电极14和P-型MOS沟道区15形成的MOS控制栅结构；P-型MOS沟道区15设置在P+浮空pbody区8顶层的中间区域，且通过P+型接触区13和金属发射极11、与P+基区2和N+发射区1相接触，所述MOS控制栅电极14对称设置在P-型MOS沟道区15的两侧，通过栅介质层3实现与P-型MOS沟道区15隔离，MOS控制栅电极14通过连接桥12与IGBT栅电极9相接触；所述MOS控制栅电极14与P+浮空pbody区8间通过栅介质层3相隔离；所述金属发射极11与连接桥12之间、以及连接桥12与N-漂移区4之间分别通过介质层10相隔离。
作为优选方式，所述MOS控制栅结构位于正向阻断状态下浮空pbody区8的中性区。
作为优选方式，所述P-型MOS沟道区15的宽度小于通态条件下MOS控制栅电极14产生的电子积累层宽度。
作为优选方式，所述MOS控制栅电极14采用与栅电极9相同结构，或采用尖角型MOS控制栅结构，以进一步减小密勒电容。
作为优选方式，P+浮空pbody区8的结深大于IGBT栅极结构的深度；这样在器件正向阻断时，P型浮空pbody区8能够与N-漂移区4形成耗尽区，减弱了正向阻断时栅极结构(即槽栅)底部的电场集聚现象，从而保证了槽栅型高压IGBT器件正向耐压的可靠性。
作为优选方式，器件所用半导体的材料为单晶硅、碳化硅或者氮化镓。
作为优选方式，P+浮空pbody区8的掺杂方式为非均匀掺杂。
本发明的分立P+浮空pbody区8中由栅介质层3、MOS控制栅电极14和P-型MOS沟道区15形成的MOS控制栅结构需要满足以下条件：
1P+浮空pbody区8与栅极结构之间通过N-漂移区4隔断；
2栅介质层3位于正向阻断时P+浮空pbody区8的中性区域；
3栅介质层3位于P-型MOS沟道区15一侧的厚度小于其在MOS控制栅电极14和分立P+浮空pbody区8之间的厚度；
4正向栅压作用下MOS控制栅电极14因为注入增强作用，在P-型MOS沟道区15中产生表面积累层电子宽度能将MOS沟道区完全阻断。
相比现有技术，本发明的有益效果在于：
(1)本发明通过在P+浮空pbody区中引入MOS结构，MOS区等效为受到栅压控制作用的开关；在器件正向导通时使得pbody区8电位浮空，实现空穴存储，降低了器件的饱和导通压降；在器件正向阻断时为空穴提供快速泄放回路，降低了关断时间和关断损耗。
(2)本发明通过MOS控制栅将P+浮空pbody区电位在关断时置零，降低了密勒电容Cgc，有效地降低了关断损耗。
(3)本发明MOS控制栅电极14因为正向电压作用，在P-型MOS沟道区15中产生表面积累层电子，在器件短路导通时消失，使得分立P+浮空pbody区电位置零，提供短路导通条件下空穴的泄放通路，抑制了短路时的热奔现象，提升器件的抗短路能力。
(4)本发明MOS控制栅结构可通过改变MOS控制栅电极14形状、P-型MOS沟道区15掺杂改变IGBT器件的密勒电容Cgc大小，实现对开关过程更好的控制。
(5)本发明提出的MOS控制栅结构，与现有高压IGBT器件栅电极制作工艺兼容。
附图说明
图1是传统分立浮空pbody区IGBT器件的结构示意图；
图2是本发明实施例1的具有MOS控制空穴通路的IGBT器件结构示意图；
图3是本发明实施例2的具有尖角型MOS控制栅结构的IGBT器件结构示意图；
图4是本发明提供的IGBT结构与传统结构输出特性曲线对比图；
图5是本发明提供的IGBT结构与传统结构关断波形对比图；
图中：1为N+发射区，2为P+基区，3为栅介质层，4为N-漂移区，5为N型缓冲层，6为P+集电区，7为金属集电极，8为P+浮空pbody区，9为栅电极，10为介质层，11为金属发射极，12为连接桥，13为P+型接触区，14为MOS控制栅电极，15为P-型MOS沟道区。
具体实施方式
以下通过特定的具体实例说明本发明的实施方式，本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用，本说明书中的各项细节也可以基于不同观点与应用，在没有背离本发明的精神下进行各种修饰或改变。
实施例1：
一种具有MOS控制空穴通路的IGBT器件，如图2所示，其元胞结构包括从下至上依次层叠的金属集电极7、P+集电区6、N型缓冲层5、N-漂移区4和金属发射极11；所述N-漂移区4的顶层中间区域设有P+浮空pbody区8，所述P+浮空pbody区8的两侧分别设有P+基区2，所述P+基区2的顶层设有N+发射区1；所述P+基区2和N+发射区1通过金属发射极11相接触；所述P+基区2和N+发射区1两者与P+浮空pbody区8之间设有IGBT栅极结构，P+浮空pbody区8和所述栅极结构不相邻，所述栅极结构包括栅电极9和栅介质层3，栅介质层3沿器件垂直方向延伸进入N-漂移区4中形成沟槽，所述栅电极9设置在沟槽中；所述栅介质层3的一侧与P+基区2、N+发射区1和N-漂移区4接触，所述栅介质层3的另一侧与P+浮空pbody区8通过N-漂移区4相隔离；所述P+浮空pbody区8中还设有栅介质层3、MOS控制栅电极14和P-型MOS沟道区15形成的MOS控制栅结构；P-型MOS沟道区15设置在P+浮空pbody区8顶层的中间区域，且通过P+型接触区13和金属发射极11、与P+基区2和N+发射区1相接触，所述MOS控制栅电极14对称设置在P-型MOS沟道区15的两侧，通过栅介质层3实现与P-型MOS沟道区15隔离，MOS控制栅电极14通过连接桥12与IGBT栅电极9相接触；所述MOS控制栅电极14与P+浮空pbody区8间通过栅介质层3相隔离；所述金属发射极11与连接桥12之间、以及连接桥12与N-漂移区4之间分别通过介质层10相隔离。
优选的，本实施例中P+浮空pbody区8的结深大于IGBT栅极结构(即槽栅)的深度；这样在器件正向阻断时，P型浮空pbody区8能够与N-漂移区4形成耗尽区，减弱了正向阻断时栅极结构(即槽栅)底部的电场集聚现象，从而保证了槽栅型高压IGBT器件正向耐压的可靠性。
优选的，所述MOS控制栅结构位于正向阻断状态下浮空pbody区8的中性区。
优选的，所述P-型MOS沟道区15的宽度小于通态条件下MOS控制栅电极14产生的电子积累层宽度。
优选的，器件所用半导体的材料为单晶硅、碳化硅或者氮化镓。
下面结合实施例对本发明原理进行详细说明：
所提结构在正向阻断时，IGBT栅极为零电位，此时MOS控制栅电极未产生注入增强效应，P+浮空pbody区8通过MOS沟道区15直接与地相连，增加了浮空pbody/N-漂移区耐压PN结；同时P+浮空pbody区8的结深大于栅极结构的深度，能够减弱正向阻断时槽栅底部的电场集聚现象，从而实现与浮空场限环相同的作用，有助于提升击穿电压。相比之下，图1的传统分立浮空pbody区IGBT器件结构，在正向阻断时，分立浮空pbody区电位浮空，虽然可以降低槽栅底部的电场峰值，但分压效果不如pbody区接地，使得正向阻断电压低于所提结构。
器件正向导通时，IGBT栅极为高电位，此时MOS控制栅电极14在P-型MOS沟道区15表面产生电子积累，因为MOS沟道区为P型轻掺杂同时宽度小于电子积累层宽度，P+浮空pbody区8将不会与地电位相接。电子从IGBT的导通沟道注入到漂移区中，空穴从背部的P+集电区6注入到N-漂移区4中，N-漂移区4发生电导调制作用；同时，空穴会存储在P+浮空pbody区8中，根据电中性原理，N-漂移区4中会有相应的电子，从而增强了N-漂移区4内载流子浓度，降低了器件饱和导通压降，与传统结构的浮空pbody区作用相同；因此两种结构的导通压降近似相同。
在关断过程中，所提结构的MOS控制栅电极电位随着IGBT栅压的降低而降低，此时其在P-型MOS沟道区产生的积累层电子数量逐渐减小，P+浮空pbody区在关断时逐渐通过P-型MOS沟道区与地相连，降低了密勒电容Cgc，从而减小了开关过程中栅电压的平台期，可有效地降低了关断时间和关断损耗。
同样在短路导通时，P+浮空pbody区因为承受耐压电位抬升，P-型MOS沟道区随之抬升，此时MOS控制栅电极虽然有正向栅压作用，但与MOS沟道区的电压降不足以产生积累层电子，P+浮空pbody区通过P-型MOS沟道区接地，使得短路时漂移区中过量空穴快速泄放到地，抑制了短路电流的增加，同时降低器件短路时发生热奔的可能性。传统结构的P+浮空pbody区8，在关断时和短路导通时空穴只能通过P-base区泄放空穴，使得关断损耗增大；同时在大电流情况下容易诱发载流子与温度之间形成正反馈，降低器件的抗短路能力。
为了验证本发明的有益效果，以3300V高压N沟道槽栅型IGBT设计为例，利用MEDICI软件对图1所示的传统IGBT器件结构以及图2所示本发明提出IGBT器件结构进行仿真比较，包括器件的静态参数：正向阻断电压、饱和导通压降和阈值电压，动态参数：密勒电容Cgc、开启损耗和关断损耗，对比结果如表1所示：
表1
Figure BDA0001954446830000051
Figure BDA0001954446830000061
从表中明显发现，本发明所提结构正向阻断电压为4279V，相比于传统结构提高了10.7％，导通压降两者相当，而开启损耗和关断损耗则明显降低，特别是密勒电容Cgc相比于传统结构降低了63％，关断损耗减低了22％。
图4输出特性结果直接表明，在200V-3000V的Vce电压范围内，所提结构的电流面密度相比于传统结构均有明显降低，在Vce＝2500V条件下，短路电流降低了5％，短路电流的降低可显著增强器件的抗短路能力。图5开关过程仿真结果表明，因为密勒电容Cgc的减小和MOS控制栅结构控制空穴通路的形成，本发明提出的IGBT器件结构的Vce和Ice变化速度明显加快，相比于传统结构有明显提升。
综上所述，本发明提供的一种具有MOS控制空穴通路的IGBT器件，相比于目前传统结构，本发明在分立浮空pbody区引入与现有IGBT工艺兼容的MOS控制栅结构，在器件正向导通时控制pbody区实现空穴存储，增强漂移区的电导调制，降低器件导通压降；在器件关断时和短路导通条件下，提供了空穴的泄放通路，改善器件密勒电容Cgc，降低了器件的关断时间和短路电流，实现了器件更低的关断损耗和更稳固的短路能力。
需要特别说明的是，本发明中关于MOS控制空穴通路的IGBT器件，不仅适用于目前普遍应用的3300V～6500V的高压范围IGBT器件，同样适用于基于平面栅和槽栅型的中压范围的IGBT器件。
实施例2
如图3所示，本实施例和实施例1的区别在于：所述MOS控制栅电极14采用尖角型MOS控制栅结构，以进一步减小密勒电容。
上述实施例仅例示性说明本发明的原理及其功效，而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下，对上述实施例进行修饰或改变。因此，凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变，仍应由本发明的权利要求所涵盖。

Claims (7)

1.一种具有MOS控制空穴通路的IGBT器件，其特征在于：其元胞结构包括从下至上依次层叠的金属集电极(7)、P+集电区(6)、N型缓冲层(5)、N-漂移区(4)和金属发射极(11)；所述N-漂移区(4)的顶层中间区域设有P+浮空pbody区(8)，所述P+浮空pbody区(8)的两侧分别设有P+基区(2)，所述P+基区(2)的顶层设有N+发射区(1)；所述P+基区(2)和N+发射区(1)通过金属发射极(11)相接触；所述P+基区(2)和N+发射区(1)两者与P+浮空pbody区(8)之间设有IGBT栅极结构，P+浮空pbody区(8)和所述栅极结构不相邻，所述栅极结构包括栅电极(9)和栅介质层(3)，栅介质层(3)沿器件垂直方向延伸进入N-漂移区(4)中形成沟槽，所述栅电极(9)设置在沟槽中；所述栅介质层(3)的一侧与P+基区(2)、N+发射区(1)和N-漂移区(4)接触，所述栅介质层(3)的另一侧与P+浮空pbody区(8)通过N-漂移区(4)相隔离；所述P+浮空pbody区(8)中还设有栅介质层(3)、MOS控制栅电极(14)和P-型MOS沟道区(15)形成的MOS控制栅结构；P-型MOS沟道区(15)设置在P+浮空pbody区(8)顶层的中间区域，且通过P+型接触区(13)和金属发射极(11)、与P+基区(2)和N+发射区(1)相接触，所述MOS控制栅电极(14)对称设置在P-型MOS沟道区(15)的两侧，通过栅介质层(3)实现与P-型MOS沟道区(15)隔离，MOS控制栅电极(14)通过连接桥(12)与IGBT栅电极(9)相接触；所述MOS控制栅电极(14)与P+浮空pbody区(8)之间通过栅介质层(3)相隔离；所述金属发射极(11)与连接桥(12)之间、以及连接桥(12)与N-漂移区(4)之间分别通过介质层(10)相隔离。
2.根据权利要求1所述的一种具有MOS控制空穴通路的IGBT器件，其特征在于：所述MOS控制栅结构位于正向阻断状态下P+浮空pbody区(8)的电中性区。
3.根据权利要求1所述的一种具有MOS控制空穴通路的IGBT器件，其特征在于：所述P-型MOS沟道区(15)的宽度小于通态条件下MOS控制栅电极(14)产生的电子积累层宽度。
4.根据权利要求1所述的一种具有MOS控制空穴通路的IGBT器件，其特征在于：所述MOS控制栅电极(14)采用与栅电极(9)相同结构，或采用尖角型MOS控制栅结构。
5.根据权利要求1所述的一种具有MOS控制空穴通路的IGBT器件，其特征在于：P+浮空pbody区(8)的结深大于IGBT栅极结构的深度。
6.根据权利要求1所述的一种具有MOS控制空穴通路的IGBT器件，其特征在于：器件所用半导体的材料为单晶硅、碳化硅或者氮化镓。
7.根据权利要求1所述的一种具有MOS控制空穴通路的IGBT器件，其特征在于：P+浮空pbody区(8)的掺杂方式为非均匀掺杂。
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