CN109726056B - Method and system for improving nonmonotonic VR time sequence signal - Google Patents
Method and system for improving nonmonotonic VR time sequence signal Download PDFInfo
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Abstract
The invention provides a method and a system for improving nonmonotonous VR time sequence signals, which comprise the following steps: s1, leading out 4 signals VIN, ENABLE, POWER, and VOUT of the VR chip through welding flying wires and connecting the signals with an oscilloscope through a single-ended probe; s2, leading out a positive cable and a negative cable on the DC Source, and connecting ENABLE signals; s3, after the ENABLE signal is disconnected with a pull-up power supply, the board card to be tested is electrified; s4, starting the DC Source, and supplying power to the ENABLE signal through the control panel; s5, setting the oscilloscope to trigger along the falling edge of the VOUT signal, and disconnecting the power supply for the ENABLE signal while disconnecting the board card to be tested; and S6, observing whether the VR power-down waveform captured by the oscilloscope is abnormal or not and storing the waveform. The problem that the power-down waveform of an ENABLE signal is not monotonous can be accurately and efficiently solved, the problem that the ENABLE signal is not monotonous in VR power-down time sequence test in the prior art is solved, the real working condition of VR is reflected, the test efficiency is improved, and the test is simple and efficient.
Description
Technical Field
The invention relates to the technical field of server mainboard design, in particular to a method and a system for improving nonmonotonous VR time sequence signals.
Background
The server mainboard and other board cards need to measure VR power down time sequence in the development stage, and whether the power down time sequence is abnormal or not is analyzed. The measured VR power-down time sequence waveform is smooth and monotonous before and after the decline, sudden changes such as abnormal uprush and fall are avoided, and the situation that the waveform is not monotonous is also not allowed to occur in the decline process.
However, in actual measurement, some ENABLE signals connected to the pull-up power supply through the pull-up resistor are found, and a non-monotonous situation occurs when the power is off, so that the judgment of the real working condition of the VR is influenced, and the test efficiency is reduced.
At present, for testing of a VR power-down time sequence, generally, VIN, ENABLE, power and VOUT 4 signals of a VR chip are led out through welding flying wires, and then, 4 single-ended probes are adopted to connect the 4 groups of signals.
The oscilloscope is set to be triggered by a signal falling edge, 4 paths of signal waveforms are captured when the oscilloscope is shut down (the shutdown is divided into two modes, namely 1, AC is directly cut off, 2, and normal shutdown is carried out), whether monotonous or abnormal sudden change exists in the waveform falling process or not is observed, and whether the power failure time sequence of the VR is normal or not is judged. However, when the ENABLE signal of the VR chip is connected to the pull-up power supply through the pull-up resistor, the captured power-down waveform of the ENABLE signal has a non-monotonous problem.
Disclosure of Invention
The invention aims to provide a method and a system for improving the nonmonotonous VR time sequence signal, which aim to solve the problem that the ENABLE signal is not monotonous in VR power-down time sequence test in the prior art, reflect the real working condition of VR, improve the test efficiency and realize conciseness and high efficiency.
To achieve the above technical object, the present invention provides a method for improving non-monotonicity of a VR timing signal, comprising the steps of:
s1, leading out 4 signals VIN, ENABLE, POWER, and VOUT of the VR chip through welding flying wires and connecting the signals with an oscilloscope through a single-ended probe;
s2, leading out a positive cable and a negative cable on the DC Source, and connecting ENABLE signals;
s3, after the ENABLE signal is disconnected with a pull-up power supply, the board card to be tested is electrified;
s4, starting the DC Source, and supplying power to the ENABLE signal through the control panel;
s5, setting the oscilloscope to trigger along the falling edge of the VOUT signal, and disconnecting the power supply for the ENABLE signal while disconnecting the board card to be tested;
and S6, observing whether the VR power-down waveform captured by the oscilloscope is abnormal or not and storing the waveform.
Preferably, the voltage of the DC Source is set to 3.3V and the current is set to 1A.
Preferably, the specific operation of disconnecting the ENABLE signal from the pull-up power supply is as follows:
the 0 Ω resistance between the P1V8_ STBY _ PG signal and the P1V0_ STBY _ EN signal is taken down.
Preferably, the connection ENABLE signal is specifically:
the anode is welded on an ENABLE signal of the VR to be measured, and the cathode is welded on a GND signal near the ENABLE signal.
The invention also provides a system for improving non-monotony of VR time sequence signals, which comprises:
the oscilloscope connecting module is used for leading out 4 signals of VIN, ENABLE, POWER, OOD and VOUT of the VR chip through welding flying wires and connecting the signals with an oscilloscope through a single-ended probe;
the ENABLE signal connection module is used for leading out a positive cable and a negative cable on the DC Source and connecting ENABLE signals;
the pull-up power supply power-off module is used for powering on the board to be tested after the ENABLE signal is disconnected with the pull-up power supply;
the DC power supply module is used for starting the DC Source and supplying power to the ENABLE signal through the control panel;
the DC power-off module is used for setting the oscilloscope to trigger along the falling edge of the VOUT signal, and switching off the board card to be tested and simultaneously switching off the power supply for supplying the ENABLE signal;
and the waveform simulation module is used for observing whether the VR power-down waveform captured by the oscilloscope is abnormal or not and storing the waveform.
Preferably, the voltage of the DC Source is set to 3.3V and the current is set to 1A.
Preferably, the specific operation of disconnecting the ENABLE signal from the pull-up power supply is as follows:
the 0 Ω resistance between the P1V8_ STBY _ PG signal and the P1V0_ STBY _ EN signal is taken down.
Preferably, the connection ENABLE signal is specifically:
the anode is welded on an ENABLE signal of the VR to be measured, and the cathode is welded on a GND signal near the ENABLE signal.
The effect provided in the summary of the invention is only the effect of the embodiment, not all the effects of the invention, and one of the above technical solutions has the following advantages or beneficial effects:
compared with the prior art, in the process of capturing the waveform in the VR power-down time sequence test, when the ENABLE signal is not monotonous and is connected to a pull-up power supply through a pull-up resistor, the ENABLE signal is disconnected from the pull-up power supply, the DC Source is used for independently supplying power to the ENABLE signal, the power supply supplied by the DC Source is disconnected while the board to be tested is shut down, the VR power-down waveform is captured, and the problem that the ENABLE signal is not monotonous in the power-down waveform can be accurately and efficiently solved. The problem that the ENABLE signal is not monotonous in VR power-down time sequence test in the prior art is solved, the real working condition of VR is reflected, the test efficiency is improved, and the method is simple and efficient.
Drawings
FIG. 1 is a flowchart of a method for improving the non-monotonicity of VR timing signals according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a VR power-down timing test ENABLE signal circuit provided in an embodiment of the invention;
fig. 3 is a schematic diagram illustrating a principle of a pull-up resistor circuit for VR power-down timing test according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a VR power-down test waveform with a non-monotonic problem before improvement in an embodiment of the present invention;
FIG. 5 is a schematic diagram of an improved VR power-down test waveform provided in an embodiment of the present invention;
fig. 6 is a block diagram of a system for improving the non-monotonicity of VR timing signals according to an embodiment of the present invention.
Detailed Description
In order to clearly explain the technical features of the present invention, the following detailed description of the present invention is provided with reference to the accompanying drawings. The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. To simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. It should be noted that the components illustrated in the figures are not necessarily drawn to scale. Descriptions of well-known components and processing techniques and procedures are omitted so as to not unnecessarily limit the invention.
A method and a system for improving non-monotony of VR timing signals according to embodiments of the present invention are described in detail below with reference to the accompanying drawings.
As shown in fig. 1, an embodiment of the present invention discloses a method for improving non-monotony of a VR timing signal, including the following steps:
s1, leading out 4 signals VIN, ENABLE, POWER, and VOUT of the VR chip through welding flying wires and connecting the signals with an oscilloscope through a single-ended probe;
s2, leading out a positive cable and a negative cable on the DC Source, and connecting ENABLE signals;
s3, after the ENABLE signal is disconnected with a pull-up power supply, the board card to be tested is electrified;
s4, starting the DC Source, and supplying power to the ENABLE signal through the control panel;
s5, setting the oscilloscope to trigger along the falling edge of the VOUT signal, and disconnecting the power supply for the ENABLE signal while disconnecting the board card to be tested;
and S6, observing whether the VR power-down waveform captured by the oscilloscope is abnormal or not and storing the waveform.
In the process of grabbing the waveform in the VR power-down time sequence test, when the problem that the ENABLE signal is not monotonous occurs and the ENABLE signal is connected to a pull-up power supply through a pull-up resistor, the ENABLE signal is disconnected from the pull-up power supply, the DC Source is used for supplying power to the ENABLE signal alone, the power supply supplied by the DC Source is disconnected while the board card to be tested is turned off, the VR power-down waveform is grabbed, and the problem that the ENABLE signal is not monotonous in the power-down waveform can be accurately and efficiently solved.
As shown in FIG. 2, the P1V8_ STBY _ PG signal is inputted as the ENABLE signal of P1V0_ STBY through a resistor with a resistance value of 0, and the signal name is P1V0_ STBY _ EN, which is the set of electrical ENABLE signals of P1V0_ STBY. It can be understood that P1V8_ STBY _ PG is equivalent to P1V0_ STBY _ EN.
As shown in FIG. 3, the P1V8_ STBY _ PG signal is connected to a pull-up power source VCC through a pull-up resistor of 3.3K Ω, i.e., the P1V0_ STBY _ EN signal is pulled up to VCC through a pull-up resistor of 3.3K Ω.
When the power-down operation is carried out, the ENABLE signal can be synchronously powered down along with the chip, the voltage is gradually reduced until the chip loses the control on the ENABLE signal, and the ENABLE signal is in a low level state.
However, since the power-down speed of the chip is fast, when the chip loses control over the ENABLE signal, the pull-up power source VCC is still in the power-down process, and the voltage does not drop to a low level. At this time, due to the action of the pull-up resistor, the voltage value of the ENABLE signal is the same as that of the pull-up power supply VCC, so that the power-down waveform of the ENABLE signal rises temporarily, namely the waveform does not drop monotonously, and then the power is synchronously powered down along with the pull-up power supply VCC until the power-down is finished.
As shown in fig. 4, the waveform is actually measured according to the conventional technique.
The waveform at the lowest end is an ENABLE waveform, and the waveform is obviously not monotonous at the marked position of the oval circle.
In order to solve the problem that an ENABLE signal is not monotonous in VR power-down time sequence test, the ENABLE signal needs to be disconnected with a pull-up power supply VCC, and the influence of the ENABLE signal on the ENABLE signal is eliminated.
In the embodiment of the invention, 4 signals of VIN, ENABLE, POWER, VOUT of a VR chip are led out through welding flying wires and are connected with an oscilloscope through a single-ended probe, a positive cable and a negative cable are led out from a DC Source, the positive electrode is welded on the ENABLE signal of the VR to be tested, the negative electrode is welded on a GND signal near the ENABLE signal, and the positive electrode and the negative electrode can not be connected reversely.
The 0 Ω resistor R248 in fig. 1 is removed, i.e., the ENABLE signal is disconnected from the pull-up power supply. And then, the DC Source is used for independently supplying power to the ENABLE signal, the DC Source is started, the OUTPUT voltage is set to be 3.3V through the control panel, the current is set to be 1A, and the OUTPUT key of the control panel is pressed to supply power to the ENABLE signal after the error is detected.
The oscilloscope is set to trigger along the falling edge of the VOUT signal, the board card to be tested is powered off, the OUTPUT key of the DCSource is pressed simultaneously, the power supply for the ENABLE signal is disconnected, the VR power-down waveform is grabbed, so that the situation that the ENABLE signal is temporarily raised when the ENABLE signal is powered down can be avoided, and the waveform is monotonically lowered.
Grabbing the waveform according to the above scheme as shown in fig. 5, the waveform at the lowermost end is the ENABLE signal, and in the figure, the waveform is monotonically decreasing. Therefore, according to the technical scheme, the ENABLE signal is disconnected with the pull-up power supply, and the DC Source is used for supplying power to the ENABLE signal independently, so that the problem that the ENABLE signal is not monotonous in VR power-down time sequence test can be accurately solved.
In the embodiment of the invention, when the ENABLE signal is not monotonous and is connected to a pull-up power supply through a pull-up resistor in the VR power-down time sequence test waveform grabbing process, the ENABLE signal is disconnected from the pull-up power supply, the DC Source is used for independently supplying power to the ENABLE signal, the power supply supplied by the DC Source is disconnected while the board card to be tested is shut down, the VR power-down waveform is grabbed, and the problem that the ENABLE signal is not monotonous in power-down waveform can be accurately and efficiently solved. The problem that the ENABLE signal is not monotonous in VR power-down time sequence test in the prior art is solved, the real working condition of VR is reflected, the test efficiency is improved, and the method is simple and efficient.
As shown in fig. 6, an embodiment of the present invention further discloses a system for improving non-monotonicity of a VR timing signal, where the system includes:
the oscilloscope connecting module is used for leading out 4 signals of VIN, ENABLE, POWER, OOD and VOUT of the VR chip through welding flying wires and connecting the signals with an oscilloscope through a single-ended probe;
the ENABLE signal connection module is used for leading out a positive cable and a negative cable on the DC Source and connecting ENABLE signals;
the pull-up power supply power-off module is used for powering on the board to be tested after the ENABLE signal is disconnected with the pull-up power supply;
the DC power supply module is used for starting the DC Source and supplying power to the ENABLE signal through the control panel;
the DC power-off module is used for setting the oscilloscope to trigger along the falling edge of the VOUT signal, and switching off the board card to be tested and simultaneously switching off the power supply for supplying the ENABLE signal;
and the waveform simulation module is used for observing whether the VR power-down waveform captured by the oscilloscope is abnormal or not and storing the waveform.
Leading out 4 signals of VIN, ENABLE, POWER, VOUT of the VR chip through welding flying wires and connecting the signals with an oscilloscope through a single-ended probe, leading out a positive cable and a negative cable on a DC Source, welding the positive electrode on the ENABLE signal of the VR to be detected, and welding the negative electrode on a GND signal near the ENABLE signal.
The 0 Ω resistor R248 in fig. 1 is removed, i.e., the ENABLE signal is disconnected from the pull-up power supply. And then, the DC Source is used for independently supplying power to the ENABLE signal, the DC Source is started, the OUTPUT voltage is set to be 3.3V through the control panel, the current is set to be 1A, and the OUTPUT key of the control panel is pressed to supply power to the ENABLE signal after the error is detected.
The oscilloscope is set to trigger along the falling edge of the VOUT signal, the board card to be tested is powered off, the OUTPUT key of the DCSource is pressed simultaneously, the power supply for the ENABLE signal is disconnected, the VR power-down waveform is grabbed, so that the situation that the ENABLE signal is temporarily raised when the ENABLE signal is powered down can be avoided, and the waveform is monotonically lowered.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
Claims (8)
1. A method for improving non-monotonicity of a VR timing signal, comprising:
s1, leading out 4 signals VIN, ENABLE, POWER, and VOUT of the VR chip through welding flying wires and connecting the signals with an oscilloscope through a single-ended probe;
s2, leading out a positive cable and a negative cable on the DC Source, and connecting ENABLE signals;
s3, after the ENABLE signal is disconnected with a pull-up power supply, the board card to be tested is electrified;
s4, starting the DC Source, and supplying power to the ENABLE signal through the control panel;
s5, setting the oscilloscope to trigger along the falling edge of the VOUT signal, and disconnecting the power supply for the ENABLE signal while disconnecting the board card to be tested;
and S6, observing whether the VR power-down waveform captured by the oscilloscope is abnormal or not and storing the waveform.
2. The method of claim 1, wherein the DC Source is set to 3.3V and the current is set to 1A.
3. The method of claim 1, wherein the specific operation of disconnecting the ENABLE signal from the pull-up power supply is:
the 0 Ω resistance between the P1V8_ STBY _ PG signal and the P1V0_ STBY _ EN signal is taken down.
4. A method of improving the non-monotonicity of VR timing signals according to any one of claims 1-3, wherein the ENABLE signal is specifically:
the anode is welded on an ENABLE signal of the VR to be measured, and the cathode is welded on a GND signal near the ENABLE signal.
5. A system for improving non-monotonicity of a VR timing signal, the system comprising:
the oscilloscope connecting module is used for leading out 4 signals of VIN, ENABLE, POWER, OOD and VOUT of the VR chip through welding flying wires and connecting the signals with an oscilloscope through a single-ended probe;
the ENABLE signal connection module is used for leading out a positive cable and a negative cable on the DC Source and connecting ENABLE signals;
the pull-up power supply power-off module is used for powering on the board to be tested after the ENABLE signal is disconnected with the pull-up power supply;
the DC power supply module is used for starting the DC Source and supplying power to the ENABLE signal through the control panel;
the DC power-off module is used for setting the oscilloscope to trigger along the falling edge of the VOUT signal, and switching off the board card to be tested and simultaneously switching off the power supply for supplying the ENABLE signal;
and the waveform simulation module is used for observing whether the VR power-down waveform captured by the oscilloscope is abnormal or not and storing the waveform.
6. The system of claim 5, wherein the DC Source is configured to have a voltage of 3.3V and a current of 1A.
7. The system of claim 5, wherein the specific operation of disconnecting the ENABLE signal from the pull-up power supply is:
the 0 Ω resistance between the P1V8_ STBY _ PG signal and the P1V0_ STBY _ EN signal is taken down.
8. The system for improving the non-monotonicity of the VR timing signal of any of claims 5-7, wherein the connection ENABLE signal is specifically:
the anode is welded on an ENABLE signal of the VR to be measured, and the cathode is welded on a GND signal near the ENABLE signal.
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| CN105576954A (en) * | 2014-10-10 | 2016-05-11 | 中兴通讯股份有限公司 | DCDC chip switching on/off time sequence control circuit provided with preset bias voltage and method thereof |
| CN105824388A (en) * | 2016-04-05 | 2016-08-03 | 浪潮电子信息产业股份有限公司 | Power-on/off detection method, device and system |
| CN108549009A (en) * | 2018-05-22 | 2018-09-18 | 郑州云海信息技术有限公司 | Solve the not dull method and system of VR power-off sequentials test POWERGOOD signals |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN105576954A (en) * | 2014-10-10 | 2016-05-11 | 中兴通讯股份有限公司 | DCDC chip switching on/off time sequence control circuit provided with preset bias voltage and method thereof |
| CN105824388A (en) * | 2016-04-05 | 2016-08-03 | 浪潮电子信息产业股份有限公司 | Power-on/off detection method, device and system |
| CN108549009A (en) * | 2018-05-22 | 2018-09-18 | 郑州云海信息技术有限公司 | Solve the not dull method and system of VR power-off sequentials test POWERGOOD signals |
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