CN109698241A - The flexible thin-film transistor and its manufacturing method of high-dielectric-coefficient grid medium layer - Google Patents
The flexible thin-film transistor and its manufacturing method of high-dielectric-coefficient grid medium layer Download PDFInfo
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- CN109698241A CN109698241A CN201811621372.0A CN201811621372A CN109698241A CN 109698241 A CN109698241 A CN 109698241A CN 201811621372 A CN201811621372 A CN 201811621372A CN 109698241 A CN109698241 A CN 109698241A
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- 239000010409 thin film Substances 0.000 title claims abstract description 21
- 238000004519 manufacturing process Methods 0.000 title claims description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 33
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 33
- 239000010703 silicon Substances 0.000 claims abstract description 33
- 239000010408 film Substances 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 24
- 238000001259 photo etching Methods 0.000 claims abstract description 22
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 claims abstract description 18
- 238000000034 method Methods 0.000 claims abstract description 15
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 14
- 239000000463 material Substances 0.000 claims abstract description 12
- 238000001755 magnetron sputter deposition Methods 0.000 claims abstract description 8
- 150000002500 ions Chemical class 0.000 claims abstract description 7
- 239000000377 silicon dioxide Substances 0.000 claims abstract description 7
- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 claims abstract description 7
- 238000010894 electron beam technology Methods 0.000 claims abstract description 6
- 238000001020 plasma etching Methods 0.000 claims abstract description 6
- 229910052681 coesite Inorganic materials 0.000 claims abstract description 5
- 229910052906 cristobalite Inorganic materials 0.000 claims abstract description 5
- 229910021421 monocrystalline silicon Inorganic materials 0.000 claims abstract description 5
- 229910052682 stishovite Inorganic materials 0.000 claims abstract description 5
- 229910052905 tridymite Inorganic materials 0.000 claims abstract description 5
- VEAHHGDAQKXNNG-UHFFFAOYSA-H C(C=1C(C(=O)[O-])=CC=CC1)(=O)[O-].[Zr+4].[Ba+2].C(C=1C(C(=O)[O-])=CC=CC1)(=O)[O-].C(C=1C(C(=O)[O-])=CC=CC1)(=O)[O-] Chemical compound C(C=1C(C(=O)[O-])=CC=CC1)(=O)[O-].[Zr+4].[Ba+2].C(C=1C(C(=O)[O-])=CC=CC1)(=O)[O-].C(C=1C(C(=O)[O-])=CC=CC1)(=O)[O-] VEAHHGDAQKXNNG-UHFFFAOYSA-H 0.000 claims abstract description 3
- 238000000137 annealing Methods 0.000 claims abstract description 3
- MRNHPUHPBOKKQT-UHFFFAOYSA-N indium;tin;hydrate Chemical compound O.[In].[Sn] MRNHPUHPBOKKQT-UHFFFAOYSA-N 0.000 claims abstract description 3
- 238000001039 wet etching Methods 0.000 claims abstract description 3
- CSCPPACGZOOCGX-UHFFFAOYSA-N Acetone Chemical compound CC(C)=O CSCPPACGZOOCGX-UHFFFAOYSA-N 0.000 claims description 31
- 229920002120 photoresistant polymer Polymers 0.000 claims description 7
- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 claims description 6
- 238000002360 preparation method Methods 0.000 claims description 6
- 239000003292 glue Substances 0.000 claims description 5
- 229910052751 metal Inorganic materials 0.000 claims description 5
- 239000002184 metal Substances 0.000 claims description 5
- 238000000992 sputter etching Methods 0.000 claims description 5
- 238000007740 vapor deposition Methods 0.000 claims description 4
- 238000004026 adhesive bonding Methods 0.000 claims description 3
- 238000001035 drying Methods 0.000 claims description 3
- 238000011049 filling Methods 0.000 claims description 3
- 238000002513 implantation Methods 0.000 claims description 3
- 238000002347 injection Methods 0.000 claims description 3
- 239000007924 injection Substances 0.000 claims description 3
- 238000004151 rapid thermal annealing Methods 0.000 claims description 3
- 239000000243 solution Substances 0.000 claims description 3
- 238000005566 electron beam evaporation Methods 0.000 claims description 2
- 238000007747 plating Methods 0.000 claims 1
- 238000004544 sputter deposition Methods 0.000 claims 1
- 238000005516 engineering process Methods 0.000 description 5
- 239000004033 plastic Substances 0.000 description 5
- 229920003023 plastic Polymers 0.000 description 5
- QPJSUIGXIBEQAC-UHFFFAOYSA-N n-(2,4-dichloro-5-propan-2-yloxyphenyl)acetamide Chemical compound CC(C)OC1=CC(NC(C)=O)=C(Cl)C=C1Cl QPJSUIGXIBEQAC-UHFFFAOYSA-N 0.000 description 4
- 238000005452 bending Methods 0.000 description 3
- 230000005611 electricity Effects 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- HHAVHBDPWSUKHZ-UHFFFAOYSA-N propan-2-ol;propan-2-one Chemical compound CC(C)O.CC(C)=O HHAVHBDPWSUKHZ-UHFFFAOYSA-N 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 235000019994 cava Nutrition 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- LYCAIKOWRPUZTN-UHFFFAOYSA-N ethylene glycol Natural products OCCO LYCAIKOWRPUZTN-UHFFFAOYSA-N 0.000 description 1
- -1 glycol ester Chemical class 0.000 description 1
- WGCNASOHLSPBMP-UHFFFAOYSA-N hydroxyacetaldehyde Natural products OCC=O WGCNASOHLSPBMP-UHFFFAOYSA-N 0.000 description 1
- 229910010272 inorganic material Inorganic materials 0.000 description 1
- 239000011147 inorganic material Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 239000011368 organic material Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- KUCOHFSKRZZVRO-UHFFFAOYSA-N terephthalaldehyde Chemical compound O=CC1=CC=C(C=O)C=C1 KUCOHFSKRZZVRO-UHFFFAOYSA-N 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78603—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the insulating substrate or support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
The present invention relates to flexible device fields, to propose flexible material transistor.The present invention, the flexible thin-film transistor of high-dielectric-coefficient grid medium layer, tin indium oxide ITO bottom gate thin film and barium zirconium phthalate BZT gate dielectric film are formed on PET flexible material substrate by way of magnetron sputtering, BZT gate dielectric layer top is one layer of monocrystalline silicon thin film, the source of this layer of monocrystalline silicon thin film is the silicon thin film of SOI, doped region pattern is formed by carrying out photoetching process in the top layer silicon of SOI, doped region at two is formed by ion implanting and the technique of annealing, square hole layer is formed by way of photoetching and reactive ion etching RIE in top layer silicon again, wet etching is carried out in hydrofluoric acid, remove intermediate SiO2, finally by the mode that photoetching and vacuum electron beam are deposited, doped region is respectively formed with source-drain electrode at two.Present invention is mainly applied to the manufactures of flexible material transistor design.
Description
Technical field
The present invention relates to flexible device fields, and in particular to a kind of high-dielectric-coefficient grid medium layer based on silicon nanometer film
Bottom gate thin film transistor structure design and preparation method.
Background technique
Flexible electronic be by organic and inorganic material electronics element manufacturing on flexible, Drawability plastics or thin metal matrix plate
New electronic science and technology, all there is extensive use in fields such as information, the energy, medical treatment, national defence.Such as print RFID tag
(RFID), electronics surface mount, Organic Light Emitting Diode OLED, flexible electronic displays etc..With traditional integrated circuit (IC)
Technology is the same, and the main drive of flexible electronic technology development is manufacturing process and equipment.With more on the substrate of more large format
Low cost, which produces the smaller flexible electronic device of characteristic size, becomes the key of manufacture.The present invention is based on silicon using a kind of
The novel process of nanometer film preparation forms bottom gate thin film using magnetron sputtering, and ion etching and hydrofluoric acid (HF) are wet after photoetching
The technology of method etching, by the silicon nanometer film stripping on silicon-on-insulator (SOI) and is transferred to the poly- terephthaldehyde of flexible
On sour glycol ester (PET) substrate, metal source and drain electrodes are then formed by photoetching and vacuum electron beam evaporation coating technique, are had in the future
Hope that, in wearable electronic, extensive flexible integration circuit etc. obtains extensive use.
Summary of the invention
In order to overcome the deficiencies of the prior art, the present invention is directed to propose flexible material transistor.For this purpose, the skill that the present invention takes
Art scheme is the flexible thin-film transistor of high-dielectric-coefficient grid medium layer, passes through the side of magnetron sputtering on PET flexible material substrate
Formula is formed with tin indium oxide ITO bottom gate thin film and barium zirconium phthalate BZT gate dielectric film, and BZT gate dielectric layer top is one layer of monocrystalline
The source of silicon thin film, this layer of monocrystalline silicon thin film is the silicon thin film of SOI, so-called SOI, be middle layer be silica SiO2, up and down
Layer is the three-decker of silicon, forms doped region pattern by carrying out photoetching process in the top layer silicon of SOI, by ion implanting and
The technique of annealing forms doped region at two, then forms square hole by way of photoetching and reactive ion etching RIE in top layer silicon
Layer, carries out wet etching in hydrofluoric acid, removes intermediate SiO2, finally by photoetching and the mode of vacuum electron beam vapor deposition
Doped region is respectively formed with source-drain electrode at two.
The flexible thin-film transistor manufacturing method of high-dielectric-coefficient grid medium layer, steps are as follows:
A, it selects PET flexible material as substrate, puts PET into the beaker for filling acetone soln first, then super
It is cleaned 5 minutes in sound wave washer, it then will in ultrasonic cleaner by the PET cleaned with acetone using aqueous isopropanol
Acetone cleans up, and obtains more clean substrate.
B, 200nm thickness ito film and 100nm thickness BZT bottom dielectric grid layer film are plated on PET substrate using magnetron sputtering.
C, SOI material is selected, is cleaned in ultrasonic cleaner using acetone, acetone is then cleaned using isopropanol
Residue dries up SOI.
D, 1813 positive photo glues are coated on the surface SOI, and uses sol evenning machine, setting revolving speed is 4000rpm, rotation time
For 30s, photoresist is got rid of uniformly, then carries out being lithographically formed specific doped region using litho machine and the mask plate made
Pattern then carries out N-type injection by the way of ion implanting, and parameter is that Implantation Energy is 40Kev, dosage 4*1015cm-
2, it generates source and drain doped region and after rapid thermal annealing 10s, photoetching is removed in acetone soln under the conditions of 750 DEG C of temperature
Glue.
E, according to label ready-made on mask plate, by the square hole of spacing 5um arrangement in source and drain doping area and mask plate
Layer carries out alignment photoetching, the small aperture layer of square of spacing 5um arrangement is formed after development on SOI, then using ion etching
Mode removes the silicon on square aperture.
F, in the hydrofluoric acid of 3:1 (HF) solution, ready-made SOI before being put into, buried oxide layer after two hours on SOI will be by
Corrosion is clean, and subsequent silicon nanometer film layer will fall off, and silicon nanometer film layer is transferred to the flexibility for having plated ITO and gate dielectric layer
On PET substrate, drying.
G, the gluing in the silicon nanometer film being transferred on PET is directed at photoetching, forms the photoengraving pattern of source-drain electrode, uses
The mode of vacuum electron beam vapor deposition forms the metal source and drain electrodes layer of 100nm, and after removing photoresist, the preparation of device is completed.
The features of the present invention and beneficial effect are:
Device in the present invention has higher integrated level, has and is more widely applied.In addition, the present invention is integrated in plastics
Transistor device on substrate still can satisfy the normal work of device when plastic supporting base bending, can wear intelligently
It wears, artificial skin, biologic medical, photoelectric device etc. acquirement are more widely applied.
Detailed description of the invention:
Attached drawing 1 is the sectional view of flexible bottom gate high dielectric constant film transistor.
Attached drawing 2 is the working principle diagram of invention, and meaning representated by each section region is made that mark in figure in figure
Note.
Specific embodiment
It is an object of the invention to design and prepare a kind of bottom of high-dielectric-coefficient grid medium layer based on flexible PET substrate
Grid structure transistor is designed in relatively simple technique and is prepared underdriven soft using the low temperature process of magnetron sputtering
Property thin film transistor (TFT), extreme enrichment use of the transistor as circuit components, so that the flexible device is in large-scale integrated
The application of circuit and photoelectric device provides possibility.
Technical program of the present invention lies in ITO bottom gate thin film and BZT are formed on PET substrate using magnetron sputtering technique
Gate dielectric film then forms doped region in such a way that photoetching process forms doped region pattern and ion implanting on SOI, adopts
Square hole layer is formed with the mode of photoetching and ion etching, silicon nanometer film layer is formed by the way of wet process HF etching, by turning
Silicon nano thin-film is transferred on PET substrate by shifting technology, forms source finally by the mode that photoetching and vacuum electron beam are deposited
Drain electrode, this completes the preparations of transistor.
The main operational principle of the flexibility bottom gate high-dielectric-coefficient grid medium layer film transistor is by bottom gate electricity
It is biased on extremely, will form electron inversion floor in place of gate dielectric layer in source and drain doping area, as the conducting channel of device,
Break-over of device, then adds bias between source-drain electrode, and whether device will start to work, be connected by grid voltage control device
And electric current between the source and drain of device, in addition, flexible substrate can reduce the ghost effect of traditional silicon substrate substrate transistor, and can
To work under different bending degree, be high-performance flexible circuit large-scale integrated and wearable electronic it is extensive
Using providing possibility.
Apply certain bias in ITO bottom gate thin film, when the voltage of application is smaller or no-bias, silicon nano thin-film
Since the generation of not no inversion layer will not generate electric current even if adding voltage between source and drain between source and drain, device closes layer
It is disconnected.When voltage is sufficiently large, silicon nanometer thin film layer will generate electron inversion layer, script crystal at the surface contacted with grid oxide layer
Surface transoid of the electron number greater than hole number will generated at gate dielectric layer surface by managing hollow more silicon nano thin-film of living in caves
Area, this region are referred to as the channel region of device, then, are biased in the source-drain electrode of n-type doping, can generate the electricity between source and drain
Stream, break-over of device.Device in the present invention has higher integrated level, has and is more widely applied.In addition, the present invention is integrated in
Transistor device in plastic supporting base still can satisfy the normal work of device when plastic supporting base bending, can be in intelligence
Wearing, artificial skin, biologic medical, photoelectric device etc. acquirement are more widely applied.
Specific manufacture craft is as follows:
A, it selects PET flexible material as substrate, puts PET into the beaker for filling acetone soln first, then super
It is cleaned 5 minutes in sound wave washer, it then will in ultrasonic cleaner by the PET cleaned with acetone using aqueous isopropanol
Acetone cleans up, and obtains more clean substrate.
B, 200nm thickness ito film and 100nm thickness BZT bottom dielectric grid layer film are plated on PET substrate using magnetron sputtering.
C, SOI material is selected, is cleaned in ultrasonic cleaner using acetone, acetone is then cleaned using isopropanol
Residue dries up SOI.
D, 1813 positive photo glues are coated on the surface SOI, and uses sol evenning machine, setting revolving speed is 4000rpm, rotation time
For 30s, photoresist is got rid of uniformly, then carries out being lithographically formed specific doped region using litho machine and the mask plate made
Pattern then carries out N-type injection by the way of ion implanting, and parameter is that Implantation Energy is 40Kev, dosage 4*1015cm-
2, it generates source and drain doped region and after rapid thermal annealing 10s, photoetching is removed in acetone soln under the conditions of 750 DEG C of temperature
Glue.
E, according to label ready-made on mask plate, by the square hole of spacing 5um arrangement in source and drain doping area and mask plate
Layer carries out alignment photoetching, the small aperture layer of square of spacing 5um arrangement is formed after development on SOI, then using ion etching
Mode removes the silicon on square aperture.
F, in the hydrofluoric acid of 3:1 (HF) solution, ready-made SOI before classical prescription aperture layer is put into, burying on SOI after two hours
Oxygen layer will be corroded completely, and subsequent silicon nanometer film layer will fall off, and silicon nanometer film layer is transferred to and has plated ITO and gate dielectric layer
Flexible PET substrate on, drying.
G, the gluing in the silicon nanometer film being transferred on PET is directed at photoetching, forms the photoengraving pattern of source-drain electrode, uses
The mode of vacuum electron beam vapor deposition forms the metal source and drain electrodes layer of 100nm, and after removing photoresist, the preparation of device is completed.
Claims (2)
1. a kind of flexible thin-film transistor of high-dielectric-coefficient grid medium layer, characterized in that pass through magnetic on PET flexible material substrate
The mode of control sputtering is formed with tin indium oxide ITO bottom gate thin film and barium zirconium phthalate BZT gate dielectric film, BZT gate dielectric layer top
One layer of monocrystalline silicon thin film, the source of this layer of monocrystalline silicon thin film is the silicon thin film of SOI, so-called SOI, be middle layer be silica
SiO2, upper and lower level is the three-decker of silicon, forms doped region pattern by carrying out photoetching process in the top layer silicon of SOI, passes through
Ion implanting and the technique of annealing form doped region at two, then pass through the side of photoetching and reactive ion etching RIE in top layer silicon
Formula forms square hole layer, and wet etching is carried out in hydrofluoric acid, removes intermediate SiO2, finally by photoetching and vacuum electron beam
The mode of vapor deposition doped region at two is respectively formed with source-drain electrode.
2. a kind of flexible thin-film transistor manufacturing method of high-dielectric-coefficient grid medium layer, characterized in that steps are as follows:
A, it selects PET flexible material as substrate, puts PET into the beaker for filling acetone soln first, then in ultrasonic wave
Cleaned 5 minutes in washer, then using aqueous isopropanol by the PET cleaned with acetone in ultrasonic cleaner by acetone
It cleans up, obtains more clean substrate.
B, 200nm thickness ito film and 100nm thickness BZT bottom dielectric grid layer film are plated on PET substrate using magnetron sputtering.
C, SOI material is selected, is cleaned in ultrasonic cleaner using acetone, acetone residue is then cleaned using isopropanol
Object dries up SOI.
D, 1813 positive photo glues are coated on the surface SOI, and uses sol evenning machine, setting revolving speed is 4000rpm, and rotation time is
30s gets rid of photoresist uniformly, then carries out being lithographically formed specific doped region figure using litho machine and the mask plate made
Case then carries out N-type injection by the way of ion implanting, and it is 40Kev, dosage 4*1015cm-2 that parameter, which is Implantation Energy,
It generates source and drain doped region and after rapid thermal annealing 10s, photoresist is removed in acetone soln under the conditions of 750 DEG C of temperature.
E, according to label ready-made on mask plate, by the square aperture layer of spacing 5um arrangement in source and drain doping area and mask plate into
Row alignment photoetching forms the small aperture layer of square of spacing 5um arrangement, then by the way of ion etching on SOI after development
By the silicon removal on square aperture.
F, in the hydrofluoric acid HF solution of 3:1, ready-made SOI before being put into, the buried oxide layer after two hours on SOI will be corroded dry
Only, subsequent silicon nanometer film layer will fall off, and silicon nanometer film layer is transferred to the flexible PET substrate for having plated ITO and gate dielectric layer
On, drying.
G, the gluing in the silicon nanometer film being transferred on PET is directed at photoetching, the photoengraving pattern of source-drain electrode is formed, using vacuum
The mode of electron beam evaporation plating forms the metal source and drain electrodes layer of 100nm, and after removing photoresist, the preparation of device is completed.
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|---|---|---|---|---|
| CN110459605A (en) * | 2019-07-29 | 2019-11-15 | 天津大学 | The heterogeneous gate dielectric layer flexible silicon thin film transistor (TFT) of multilayer material and its manufacturing method |
| CN110620155A (en) * | 2019-09-24 | 2019-12-27 | 天津大学 | Heterogeneous gate dielectric layer flexible silicon thin film transistor and manufacturing method thereof |
| CN111029402A (en) * | 2019-11-14 | 2020-04-17 | 天津大学 | Flexible bottom gate thin film transistor of zirconium-titanium oxide gate dielectric layer and manufacturing method thereof |
| CN111029341A (en) * | 2019-11-14 | 2020-04-17 | 天津大学 | Flexible bottom gate flash memory device with calcium copper titanate gate dielectric layer and manufacturing method thereof |
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| GB2589415A (en) * | 2019-07-31 | 2021-06-02 | Univ Northwestern Polytechnical | An in-plane displacement sensing unit based on a simplified optical nanometer scale resonant cavity |
| CN114078974A (en) * | 2020-08-21 | 2022-02-22 | 天津大学 | SiO growth by high temperature2Preparation method of silicon nano flexible thin film transistor of gate dielectric layer |
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| CN108689702A (en) * | 2018-05-08 | 2018-10-23 | 天津大学 | A kind of high-k low-loss barium zirconium phthalate dielectric material and preparation method thereof |
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