CN109698166B - 形成晶体管装置的栅极接触结构、交叉耦合接触结构的方法 - Google Patents
形成晶体管装置的栅极接触结构、交叉耦合接触结构的方法 Download PDFInfo
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Abstract
本发明涉及形成晶体管装置的栅极接触结构、交叉耦合接触结构的方法,所揭示的一示范方法主要包括:选择性地形成栅极至源极/漏极(GSD)接触开口及CB栅极接触开口于至少一层绝缘材料中以及在相应开口中形成初始栅极至源极/漏极(GSD)接触结构与初始CB栅极接触结构,其中,该GSD接触结构与该CB栅极接触结构中的各者的上表面位在第一层级,以及对该初始GSD接触结构及该初始CB栅极接触结构执行凹陷蚀刻制程以形成凹陷GSD接触结构与凹陷CB栅极接触结构,其中,这些凹陷接触结构中的各者的凹陷上表面位在低于该第一层级的第二层级。
Description
技术领域
本揭示内容大致有关于集成电路的制造,且更特别的是,有关于形成用于晶体管装置的栅极接触结构及交叉耦合接触结构的各种新颖方法与各种新颖装置结构。
背景技术
在例如微处理器、储存装置及其类似者的现代集成电路中,在有限的芯片面积上形成及运行有大量的电路组件,特别是场效应晶体管(FET)。FET有各种不同组态,例如平面装置、FinFET装置、纳米级装置等等。这些FET装置通常在切换模式下运行,亦即,这些装置展现高度导电状态(开启状态)与高阻抗状态(关闭状态)。场效应晶体管的状态是由栅极电极控制,该栅极电极在施加适当的控制电压时控制形成于漏极区、源极区之间的通道区的导电率。
在IC产品上形成各种装置层级接触以建立电气连接至形成于衬底上的各种半导体装置。例如,此类装置层级接触包括多个有时被称为“CA接触”结构,以用于建立分离的电气连接至晶体管装置的源极/漏极区中的各者,以及用于建立分离的电气连接至晶体管装置的栅极结构的分离的栅极接触结构,它有时被称为“CB接触”结构。这些CA接触结构通常接触形成于晶体管装置的源极/漏极区上方的有时被称为“沟槽硅化物”(TS)结构者。该CB栅极接触通常垂直地位在包围晶体管装置的隔离材料之上,亦即,该CB栅极接触通常不位在主动区之上,但是在有些先进架构中可能会这样。该CB栅极接触通常位在隔离区之上以避免或减少在CB接触与形成于晶体管的源极/漏极区中的TS导电结构之间产生电气短路(electrical short)的机会,亦即,在这两个结构之间必须根据企图防止此类电气短路的各种设计规格而维持有最小间隔。可惜,会有与CB接触只能位在隔离区上方的要求相关的面积损失(area penalty)。因此,一直努力想要建立使得CB接触可完全形成于主动区上方的制程流程。
不过,在例如SRAM电路的一些应用中,必须形成导电接触或导电条带(conductivestrap)于晶体管的栅极电极与该晶体管的源极/漏极区中的一者之间,亦即,栅极至源极/漏极(gate-to-source/drain,GSD)接触结构。该GSD接触结构有时被称为“交叉耦合”接触或CAREC(CA RECtangular)结构。该GSD接触结构建立第一晶体管的栅极电极与第二晶体管的源极/漏极区中的一者之间的电气短路。当然,此类交叉耦合接触结构也可形成于其他IC装置上以及于除SRAM电路以外的不同应用中。
通常,由于大量的半导体装置(亦即,电路组件,例如晶体管、电阻器、电容器等等)以及现代集成电路的必要复杂布局,在有半导体装置制造于其上的相同装置层级内无法建立个别半导体装置的电气连接或“布线排列”。因此,构成IC产品的整体布线图案的各种电气连接被形成于金属化***中,其包含形成于产品的装置层级之上的多个堆栈的“金属化层”。这些金属化层通常由数层绝缘材料构成,在这些绝缘材料层中形成导电金属线及导电通孔。一般而言,导线提供层内(intra-level)电气连接,同时导电通孔在导线的不同层级之间提供层间(inter-level)连接或垂直连接。这些导线及导电通孔可由各种不同材料构成,例如铜、钨、铝等等(以及适当的阻障层)。集成电路产品中的第一金属化层通常被称为“M1”层。通常,多个导电通孔(通常被称为“V0”通孔)用来在M1层与大致被称为装置层级接触(以下会有更完整的解释)的较低层级导电结构之间建立电气连接。在有些更先进的装置中,在装置层级接触与V0通孔之间形成由导线(有时称为“M0”层)构成的另一金属化层。
栅极接触结构及GSD接触结构在现代IC产品上的形成可能极具挑战性。本揭示内容针对在IC产品上形成用于晶体管装置的栅极接触结构及交叉耦合接触结构的各种新颖方法与各种新颖装置结构。
发明内容
以下提出本发明的简化概要以提供本发明的一些方面的基本理解。此概要并非本发明的穷举式总览。它不是旨在确认本发明的关键或重要组件或者是描绘本发明的范畴。唯一的目的是要以简要的形式提出一些概念作为以下更详细的说明的前言。
大体上,本揭示内容是针对形成用于晶体管装置的栅极接触结构及交叉耦合接触结构的各种新颖方法与各种新颖装置结构。揭示的一示范方法主要包括:选择性地形成栅极至源极/漏极(GSD)接触开口及CB栅极接触开口于至少一层绝缘材料中且形成初始栅极至源极/漏极(GSD)接触结构于该GSD接触开口中以及一初始CB栅极接触结构于该CB栅极接触开口中,其中该GSD接触结构与该CB栅极接触结构中的各者的上表面位在第一层级。在一实施例中,该方法也包括:对该初始GSD接触结构及该初始CB栅极接触结构执行凹陷蚀刻制程以形成凹陷GSD接触结构与凹陷CB栅极接触结构,其中该凹陷GSD接触结构与该凹陷CB栅极接触结构中的各者的凹陷上表面位在低于该第一层级的第二层级。
揭示于本文的一示范集成电路(IC)产品包括第一晶体管的第一导电源极/漏极接触结构,该第一晶体管具有至少位在该第一导电源极/漏极接触结构的上表面的一部分之上的绝缘源极/漏极帽盖与导电耦合至该第一导电源极/漏极接触结构及第二晶体管的第一栅极结构的栅极至源极/漏极(GSD)接触结构。在此实施例中,该产品也包括导电耦合至第三晶体管的第二栅极结构的CB栅极接触结构,其中该GSD接触结构与该CB栅极接触结构中的各者的上表面位在第一层级,该第一层级是在高于该绝缘源极/漏极帽盖的上表面的层级的层级。
附图说明
参考以下结合附图的说明可明白本揭示内容,其中类似的组件以相同的附图标记表示,且其中:
图1至图2图标用于集成电路产品的装置层级接触及金属化层的各种示范先前技术配置;以及
图3至图39图示揭示于本文形成用于晶体管装置的栅极接触结构及交叉耦合接触结构的各种新颖方法与各种新颖装置结构。
尽管揭示于本文的专利目标容易做成各种修改及替代形式,然而本文仍以附图为例图示本发明的几个特定具体实施例且详述于本文。不过,应了解本文所描述的特定具体实施例并非旨在把本发明限定为本文所揭示的特定形式,反而是,本发明应涵盖落在如随附权利要求书所界定的本发明精神及范畴内的所有修改、等效及替代性陈述。。
具体实施方式
以下描述本发明的各种示范具体实施例。为了清楚说明,本专利说明书并未描述实际具体实作的所有特征。当然,应了解,在开发任一此类的实际具体实施例时,必需做许多与具体实作有关的决策以达成开发人员的特定目标,例如遵循与***相关及商务有关的限制,这些都会随着每一个具体实作而有所不同。此外,应了解,此类开发即复杂又花时间,但对本领域一般技术人员而言,在阅读本揭示内容后仍将如例行工作。
此时以参照附图来描述本发明。示意图标于附图的各种结构、***及装置仅供解释以及避免本领域技术人员所熟知的细节混淆本发明。尽管如此,仍纳入附图以描述及解释本揭示内容的示范实施例。应使用与相关技艺技术人员所熟悉的意思一致的方式理解及解释用于本文的字汇及词组。本文没有特别定义的术语或词组(亦即,与本领域技术人员所理解的普通惯用意思不同的定义)旨在用术语或词组的一致用法来说明。如果术语或词组旨在具有特定的意思时(亦即,不同于本领域技术人员所理解的意思),则会在本专利说明书中以直接明白地提供特定定义的方式清楚地陈述用于该术语或词组的特定定义。
图1的横截面图图示一示范先前技术IC产品10,其由形成于半导体衬底12中及半导体衬底12之上的晶体管装置11构成。也图标用于建立电气连接至装置11的示意图标的源极/漏极区20的多个CA接触结构14,与CB栅极接触结构16。CB栅极接触16通常垂直地位在包围装置11的隔离材料13之上,亦即,CB栅极接触16通常不位在界定于衬底12中的主动区之上,但是在有些先进架构中可能会这样。
晶体管11包含示范的栅极结构22(亦即,栅极绝缘层22A与栅极电极22B)、栅极帽盖24、侧壁间隔件26、以及示意图示的源极/漏极区20。在图标于图1的制造点,在衬底12之上已形成数层绝缘材料30A、30B,亦即,层间介电材料。附图未图示其他的材料层,例如接触蚀刻中止层(contact etch stop layer)及其类似者。也图示示范的突起外延源极/漏极区32与源极/漏极接触结构34,它通常包括所谓的“沟槽硅化物”(TS)结构36。CA接触结构14的形式可为形成于层间介电材料中的分离的接触组件,亦即,在从上面观看时有大致像方形的形状或圆柱形形状的一或多个个别接触插塞。在其他的应用中,CA接触结构14也可为线路型特征,其接触下方的线路型特征,例如,接触源极/漏极区20的TS结构36通常朝与晶体管11的栅极宽度方向平行的方向延伸越过源极/漏极区20上的整个主动区,亦即,进出图1之图纸的平面。CA接触14与CB接触16在工业内都被视为装置层级接触。
IC产品10包括用于产品10的多层级金属化***的M0金属化层。该M0金属化层形成于例如低k绝缘材料的一绝缘材料层46中,且被形成为可建立电气连接至装置层级接触–CA接触14与CB接触16。也图示于图1中的是用于产品10的M1金属化层,其形成于例如低k绝缘材料的一绝缘材料层38中。提供多个导电通孔–V0通孔40–以建立M0金属化层与M1金属化层之间的电气连接。M0金属化层与M1金属化层两者通常包括(各自)依照需要而路由越过产品10的多个金属线44、42。M0金属化层的形成有助于减少形成于衬底12上的电路的总电阻。不过,在有些IC产品中,可省略M0金属化层且使M1金属化层的V0通孔40与CA接触14及CB接触16接触。
图2为单一FinFET晶体管装置52的简化平面图。晶体管52包含多个示范鳍片65、栅极帽盖层53、侧壁间隔件51、与形成于源极/漏极区之上的沟槽硅化物结构56。也图示用于建立电气连接至源极/漏极区的多个CA接触结构54,与CB栅极接触结构58,其经形成为通过在栅极帽盖53中形成开口而建立电气接触至栅极结构(未图标)。
如图2所示,CB栅极接触58通常垂直地位在包围装置52的隔离材料55之上,亦即,CB栅极接触58通常不位在主动区之上,但是在有些先进架构中可能会这样。CB栅极接触58通常位在隔离区55之上以避免或减少在CB接触58与TS结构56之间产生电气短路的机会,亦即,在这两个结构之间必须根据企图防止此类电气短路的各种设计规格而维持有最小间隔66。可惜,会有与CB接触58只能位在隔离区55之上的要求相关的面积损失。
本揭示内容针对形成用于晶体管装置的栅极接触结构及交叉耦合接触结构的各种新颖方法与各种新颖装置结构。在使用各种技术来制造产品时可采用揭示于本文的方法及装置,例如NMOS、PMOS、CMOS等等,且在制造各种不同装置时可采用它们,例如内存产品、逻辑产品、ASIC等等。本领域技术人员在读完本申请案后应了解,在以各种不同组态使用晶体管装置来形成集成电路产品时可采用揭示于本文的发明,例如平面装置、FinFET装置、纳米线装置等等。在描绘于本文的示范实施例中,晶体管装置为FinFET装置。用于晶体管装置的栅极结构可使用“栅极优先(gate first)”或者是“取代栅极(replace gate)”制造技术形成。因此,揭示于本文的发明不应视为受限于晶体管的任何特定形式或形成晶体管装置的栅极结构的方式。当然,揭示于本文的发明不应视为受限于图示及描述于本文的示范实施例。此时参考附图,更详细地描述揭示于本文的方法及装置的各种示范具体实施例。以下所描述的各种材料层可用各种不同已知技术中的任一形成,例如化学气相沉积(CVD)制程、原子层沉积(ALD)制程、热成长制程、旋涂技术等等。此外,如使用于本文及随附权利要求书中的,用词“邻接”是要赋予宽广的解释且应被解释成可涵盖一特征与另一特征实际接触或与该另一特征靠得很近的情况。
图3至图15图示揭示于本文的各种新颖方法用以形成用于集成电路(IC)产品100上的晶体管装置的栅极接触结构及交叉耦合接触结构和所产生的新颖结构。在图标实施例中,IC产品100各自包含第一、第二及第三晶体管101A、101B、101C,以及用于形成于半导体衬底102中及半导体衬底102之上的各种晶体管装置的多个栅极106(为便于参考以1至4编号)。也图示于平面图中的是导电耦合至晶体管装置的源极/漏极区的示范源极/漏极接触结构120、120X(例如,沟槽硅化物结构)。示范源极/漏极接触结构120X为第一晶体管101A的一部分(未图示第一晶体管101A的栅极),栅极1为第二晶体管101B的主动栅极而栅极3为第三晶体管101C的主动栅极。栅极2及4因为与第三晶体管101C有关而为“虚拟”或非主动栅极,但是栅极2及4可为形成于衬底102之上的其他晶体管装置(未图标)的主动栅极。图3也包括IC产品100的简化平面图,其图示各种绝缘材料层被移除的IC产品100。如以下更完整地所示的,除了揭示于本文的其他方面以外,GSD(交叉耦合)接触133会形成于第一晶体管101A的源极/漏极区120X与第二晶体管101B的栅极结构108的导电栅极电极之间。
在描绘于本文的示范实施例中,晶体管装置为FinFET装置,但是揭示于本文的发明不应视为受限于包括FinFET晶体管装置的IC产品,因为在制造其他形式的晶体管时,例如平面晶体管装置,可采用揭示于本文的各种发明。在图示于图3的加工点,已使用传统制造技术在衬底102中形成多个鳍片103,且已形成越过鳍片103的栅极106。该平面图也描绘出会形成接触栅极3的栅极结构108的示范的CB栅极接触结构130。揭示于本文的CB栅极接触结构130会位在晶体管的主动区之上。如本文所使用的,用语“主动区”应被理解为被位在栅极3的相对两侧上的两个导电源极/漏极接触结构120以与栅极3的位在两个源极/漏极接触结构120之间的部分所占用的区域或“占位面积(footprint)”。也图示于图3的平面图中的是将形成CA接触结构132的位置,其接触第三晶体管101C的源极/漏极接触结构120中的一者。也图示将形成栅极至源极/漏极(GSD)接触结构133的位置,其使第二晶体管101B的栅极1的栅极结构108的栅极电极导电耦合至为第一晶体管101A的一部分的源极/漏极接触结构120X。
包括在本文中的附图也包括在图3的平面图所示处绘出的两个横截面图(“X-X”与“Y-Y”)。具体而言,横截面图X-X是在会形成CB栅极接触结构130及GSD接触结构133(以及在此会形成用于其他晶体管装置的紧密包装的栅极接触结构151(未图标),下文有更完整的描述)的位置处沿着晶体管装置的栅极-长度方向穿过栅极106绘出。在晶体管装置为FinFET装置的情形下,视图X-X应理解为是朝对应至FinFET装置的栅极长度(电流输送)方向的方向沿着晶体管的鳍片103长轴绘出的横截面图。横截面图Y-Y是在会形成CA接触结构132的位置处沿着晶体管装置的栅极-长度方向穿过栅极106绘出。
衬底102可具有各种组态,例如图示的块硅组态。衬底102也可具有绝缘体上覆半导体(semiconductor-on-insulator;SOI)组态,其包括块状半导体层、埋藏绝缘层及位在埋藏绝缘层上的主动半导体层,其中半导体装置形成于主动层中及主动层之上。衬底102可由硅制成或可由除硅以外的材料制成。因此,应了解用语“衬底”或“半导体衬底”涵盖所有半导体材料及此类材料的所有形式。另外,附图中并未图示各种掺杂区,例如晕圈植入区、井区及其类似者。
图3图示在执行数个制程操作之后的IC产品100。首先,如上述,鳍片103的形成通过执行通过图案化鳍片形成蚀刻掩模(未图示)的一或多个蚀刻制程,例如,非等向性蚀刻制程,以形成多个鳍片形成沟槽(fin-formation trench)于衬底102中而由此形成这些多个鳍片103。鳍片103的宽度及高度可取决于特定应用而有所不同。另外,鳍片形成沟槽及鳍片103的整体大小、形状及组态可取决于特定应用而有所不同。接下来,随后沉积一绝缘材料层107(例如,二氧化硅)以便过填(overfill)这些鳍片形成沟槽。然后执行化学机械研磨(CMP)制程以平坦化绝缘材料层107的上表面与鳍片103的上表面,由此移除图案化鳍片形成硬掩模。接下来,对绝缘材料层107执行凹陷蚀刻制程致使它具有凹陷上表面107R,以暴露在该凹陷上表面107R之上所欲数量的鳍片103。
仍参考图3,在使绝缘材料层107凹陷后,形成栅极106于鳍片103之上。栅极106各自包括示意图标的最终栅极结构108、最终栅极帽盖110、第一侧壁间隔件112及第二侧壁间隔件113。侧壁间隔件112、113与栅极帽盖110可由各种不同材料构成,例如氮化硅、SiNC、SiN、SiCO、SiNOC等等。在一示范具体实施例中,第一间隔件112与栅极帽盖110可由相同的材料制成,例如氮化硅,同时第二间隔件113可由相对于第一间隔件112与栅极帽盖110的材料具有良好蚀刻选择性的不同材料制成,例如SiCO。通常,当使用传统取代栅极制造技术来制造栅极结构108时,会在衬底102之上形成牺牲栅极结构(未图标)以及位于牺牲栅极结构之上的原始栅极帽盖(未图示)。这时,可形成邻接牺牲栅极结构及原始栅极帽盖的第一间隔件112。接下来,在形成最终栅极结构108之前,通过执行外延成长制程来形成外延半导体材料116于主动区103(或在FinFET装置的情形下,为鳍片)的暴露部分上,亦即,在装置的源极/漏极区中。可形成外延材料116至任何所欲厚度。不过,应了解,外延材料116不必形成在所有的应用中。附图未图示其他的材料层,例如接触蚀刻中止层及其类似者。也图示通常包括所谓“沟槽硅化物”(TS)结构(未单独图标)的示范源极/漏极接触结构120、120X。如图标,当产品100制造完成时,源极/漏极接触结构120、120X的上表面通常大约与栅极帽盖110的上表面齐平。
在形成外延材料116后,毯覆沉积一绝缘材料层109(例如,二氧化硅)于衬底102上。之后,使用位于牺牲栅极结构之上作为研磨中止层的原始栅极帽盖(未图示)来执行CMP制程以平坦化绝缘材料层109。这时,执行蚀刻制程以便移除这些原始栅极帽盖与第一间隔件112的垂直部分,从而暴露牺牲栅极结构的上表面以供移除。然后,执行传统取代栅极制程以移除这些牺牲栅极结构以便界定在间隔件112之间的取代栅极空腔,在此会形成最终栅极结构108。最终栅极结构108的形成通过依序沉积各种材料层于取代栅极空腔中且执行CMP制程以移除栅极材料位于栅极空腔之外的部分。之后,凹陷用于栅极结构108的材料以便腾出空间给第二间隔件113与栅极帽盖110。接下来,通过沉积间隔件材料的共形层且执行非等向性蚀刻制程,在凹陷栅极材料上方的空间中形成第二间隔件113作为内部间隔件。然后,通过在凹陷栅极材料之上并且在第二间隔件113之间的空间中沉积一层间隔件材料,然后执行CMP制程来形成栅极帽盖110。接下来,移除绝缘材料109在源极/漏极区上方的部分且在装置的源极/漏极区中形成上述源极/漏极接触结构120、120X。然后,对源极/漏极接触结构120、120X执行凹陷蚀刻制程以腾出空间给将会形成于源极/漏极接触结构120、120X中的各者之上的绝缘源极/漏极帽盖115。可通过沉积一层绝缘材料(例如,二氧化硅、SiC、SiCO等等)于凹陷源极/漏极接触结构120、120X之上,然后执行CMP制程来形成绝缘源极/漏极帽盖115。
图4图示在通过执行独立毯覆沉积制程来形成蚀刻中止层117及一绝缘材料层119于产品100之上之后的IC产品100。构造的材料以及层117、119的厚度可取决于应用而有所不同。在一示范具体实施例中,蚀刻中止层117可包含氮化硅,同时绝缘材料层119可包含二氧化硅。
图5图示在绝缘材料层119中形成各自用于GSD接触结构133及CB栅极接触结构130的开口133X及130X之后的产品。通过形成图案化蚀刻掩模(未图标),例如图案化光阻层,于绝缘材料层119之上,且随后执行蚀刻制程,而形成开口133X及130X。如图示,该蚀刻制程在蚀刻中止层117停止。
图6图示在通过开口133X、130X来执行蚀刻制程以相对于周围材料而选择性地移除蚀刻中止层117的暴露部分以与栅极1及3的栅极帽盖110之后的产品100。此制程操作暴露栅极1及3的栅极结构108的上表面108S。应注意,在此蚀刻制程期间,第二间隔件113及绝缘源极/漏极帽盖115保护源极/漏极接触结构120、120X。此制程操作也形成CB栅极接触结构130的CB栅极接触开口130Z。
图7图标在形成例如图案化OPL层的牺牲掩模层121以便填满且覆盖CB栅极接触开口130Z之后的产品100。如图示,掩模层121让栅极1暴露以供进一步加工。
图8图示在执行数个制程操作之后的产品100。首先,在一示范制程流程中,执行蚀刻制程以选择性地至少移除第二侧壁间隔件113与第一晶体管装置101A的源极/漏极接触结构120X邻接的部分且由此暴露源极/漏极接触结构120X的侧面120Y的一部分。之后,若需要,可执行视需要的蚀刻制程以选择性地移除绝缘源极/漏极帽盖115的暴露部分以便暴露源极/漏极接触结构120X的凹陷上表面120Z的一部分。如果这两种蚀刻制程都执行,则可用任何所欲次序来执行它们。此制程操作也形成GSD接触结构133的GSD接触开口133Z。在此示范制程流程中,GSD接触开口是在CD栅极接触开口130Z之后形成。
图9图示在执行数个制程操作之后的产品。首先,移除掩模层121以便二次暴露(re-expose)CB栅极接触开口130Z。之后,通过同时执行数个制程操作,亦即,数个共同制程操作,初始导电CB栅极接触结构130与初始的导电GSD接触结构133各自形成于CB栅极接触开口130Z与GSD接触开口133Z中。在一示范制程流程中,沉积导电CB栅极接触结构130及导电GSD接触结构133(例如,其包括共形阻障层(未图示)及任何块状导电材料层)的导电材料于开口130Z及133X中。之后,执行一或多个CMP制程操作以使用绝缘材料119作为研磨中止物(polish-stop)来移除导电材料位在开口130Z、133Z外的多余数量。导电CB栅极接触结构130及导电GSD接触结构133可包含各种导电材料,例如钨、铜等等。在初始形成时,初始的导电CB栅极接触结构130具有上表面130S且初始的导电GSD接触结构133有与绝缘材料层119的上表面实质齐平的上表面133S,且上表面130S、133S位于在衬底102之上的共同第一层级。
图10图示在对导电CB栅极接触结构130及导电GSD接触结构133同时执行凹陷蚀刻制程之后的产品100。此制程操作形成各自具有蚀刻后的凹陷上表面(post-etch recessedupper surface)130R、133R的凹陷导电CB栅极接触结构130与凹陷导电GSD接触结构133。凹陷数量可取决于特定应用而有所不同。在一示范具体实施例中,该凹陷蚀刻制程应让凹陷上表面130R、133R位在蚀刻中止层117之上有一给定距离123(例如,至少约5纳米)的层级。此外,在该凹陷蚀刻制程完成后,凹陷上表面130R、133R位在第二层级,其低于上述第一层级且高于绝缘源极/漏极帽盖115的上表面115S的层级。
图11图示在形成附加绝缘材料119X于开口130X、133X各自在导电CB栅极接触结构130及导电GSD接触结构133之上的剩余部分中之后的产品100。通过沉积例如二氧化硅的一层绝缘材料以便过填开口130X及133X,然后执行CMP制程,可形成附加绝缘材料119X。附加绝缘材料119X可由与绝缘材料119相同的材料制成,然而所有的应用可能并非如此。
图12及图13(视图Y-Y(参考图3))图示在执行数个制程操作以形成导电接触132至用于形成于衬底102之上的各种晶体管装置的源极/漏极接触结构120之后的产品100。在图示实施例中,导电接触132中的一者经形成为其导电接触第三晶体管101C的源极/漏极接触结构120中的一者。不过,在图标于此的示范制程流程期间,如图12所示,也形成导电耦合至凹陷导电CB栅极接触结构130的另一导电接触132。导电接触132旨在本质上具有代表性,因为它们可使用各种技术及材料形成,例如铜、钨、含金属材料。首先,在一示范制程流程中,在绝缘材料119、119X中形成多个接触开口132X。接下来,形成一或多个共形阻障层及/或种子层(未单独图示)以便用阻障材料衬垫(line)开口132X。接下来,在产品100上随后形成一层导电材料(例如,铜、含金属材料、金属化合物等等)以便过填开口132X。这时,执行CMP制程以从绝缘材料层119、119X之上表面移除导电材料的多余部份。这些制程操作导致形成导电耦合至第三晶体管101C的栅极3的栅极结构108的导电接触132与导电耦合至第三晶体管101C的源极/漏极接触结构120中的一者的导电接触132。
图14及图15图示在执行数个制程操作以形成导电M0金属化层于产品100之上之后的产品100。该M0金属化层由多个独立导线139A、139B(全体用附图标记139表示)构成。首先,在产品100之上形成一绝缘材料层137。然后,在绝缘材料137中形成用于导电金属线139的各种开口。之后,在绝缘材料层137的开口中形成用于导电金属线139的导电材料。如图示,金属线139A导电耦合至与CB栅极接触130耦合的导电接触132,同时导线139B导电耦合至与第三晶体管的源极/漏极接触结构120耦合的导电接触132。应注意,如图14所示,由于GSD接触结构133的凹陷,金属线139A与凹陷的GSD接触结构133(垂直)实体隔开(有绝缘材料位在这两个结构之间),由此提供物理空间以将导线139A垂直安置在GSD接触结构133之上。换言之,使用揭示于本文的新颖方法,通过形成凹陷GSD接触结构133,金属线139A没有被阻挡,使得好像GSD接触结构133之前没有被凹陷一般。在一示范制程流程中,金属线139的形成可使用类似以上在说明导电接触132的形成时所描述的技术。
图16至图39图示揭示于本文形成用于晶体管装置的栅极接触结构及交叉耦合(或GSD)接触结构的各种其他新颖方法与各种新颖装置结构。图16为IC产品100的简化平面图,其包括形成于衬底102之上的其他晶体管装置的附加栅极5-7。在此实施例中,会形成会各自导电耦合至栅极5、6及7的栅极结构108的紧密间隔而独立的CB栅极接触结构151A、151B及151C(全体用附图标记151表示)。在图标实施例中,CB栅极接触结构151会形成于隔离材料之上,亦即,CB栅极接触结构151不会形成于这些晶体管装置的主动区之上。也应注意,在图示实施例中,由于CB栅极接触结构151各自直接邻接在直接邻接栅极结构上的另一CB栅极接触结构151,所以此一配置可称为紧密包装CB栅极接触结构。不过,本领域技术人员在读完本申请案后应了解,揭示于本文的各种发明不应视为受限于IC产品100包括此类紧密包装CB栅极接触结构的情形。例如,在不紧密包装CB栅极接触结构151的情形下可采用揭示于本文的发明,亦即,在以每隔一个栅极的方式在栅极上形成在同一行或同一排的相邻CB栅极接触结构151而不是在每一个栅极上的情况时。
图17及图18图示在对应至图4的制造点处的IC产品100,亦即,在形成上述蚀刻中止层117及绝缘材料层119之后。
图19及图20图示在形成上述开口133X及130X于绝缘材料层119中之后以及在会形成CB栅极接触结构151以接触栅极5-7的栅极结构108的位置处形成开口151X于绝缘材料层119中之后的IC产品100。
图21及图22图示在通过开口133X、130X及151X来执行蚀刻制程以相对于周围材料而选择性地移除蚀刻中止层117的暴露部分以与栅极1、3及5-7的栅极帽盖110之后的IC产品100。此制程操作暴露栅极1、3及5-7之栅极结构108的上表面108S。应注意,在此蚀刻制程期间,第二间隔件113及绝缘源极/漏极帽盖115保护源极/漏极接触结构120、120X。此制程操作也形成CB栅极接触结构130的CB栅极接触开口130Z以及用于各个栅极5-7的多个CB栅极接触开口151Z。
图23及图24图标在形成例如图案化OPL层的上述掩模层121以填满且覆盖CB栅极接触开口130Z之后的IC产品100。如图示,掩模层121使栅极1及5-7暴露以供进一步加工。
图25及图26图示在执行蚀刻制程以选择性地至少移除第二侧壁间隔件113邻接第一晶体管装置101A的源极/漏极接触结构120X的部分且由此暴露源极/漏极接触结构120X的侧面120Y的一部分之后的IC产品100。如图26所示,此蚀刻制程也移除多个附加晶体管装置的栅极5-7的第二间隔件113。应注意,不像前一个具体实施例,在此示范制程流程中,不移除绝缘源极/漏极帽盖115位于源极/漏极接触结构120X之上的暴露部分,亦即,不暴露凹陷源极/漏极接触结构120X的上表面。此制程操作也形成GSD接触结构133的GSD接触开口133Z的一具体实施例。
图27及图28图示在执行数个制程操作之后的IC产品100。首先,移除掩模层121以便二次暴露CB栅极接触开口130Z。之后,各自在CB栅极接触开口130Z与GSD接触开口133Z中形成上述导电CB栅极接触结构130与上述导电GSD接触结构133,且通过同时执行数个制程操作,在开口151X与栅极接触开口151Z中形成导电栅极结构161。如图示,上表面133S、130S及161S大致共平面且位于在半导体衬底102的上的同一个第一层级。用来形成这些结构130、133及161的制程流程可与以上在说明CB栅极接触结构130及导电GSD接触结构133的形成时所描述的相同。
图29及图30图示在执行数个制程操作之后的IC产品100。首先,形成例如图案化OPL层的另一掩模层163以便覆盖CB栅极接触结构130。如图标,掩模层163使GSD接触结构133及导电栅极结构161暴露以供进一步加工。然后,对导电GSD接触结构133及导电栅极结构161执行凹陷蚀刻制程致使它们各自有大致在同一个层级的蚀刻后的凹陷上表面133R、161R。凹陷数量可取决于特定应用而有所不同。在一示范具体实施例中,该凹陷蚀刻制程应让凹陷上表面133R的层级低于绝缘源极/漏极帽盖115的上表面115S的层级并且使凹陷上表面161R的层级低于绝缘材料层109的上表面109S的层级。导电栅极结构161的凹陷导致形成用于附加晶体管装置的各个栅极5-7的栅极结构108的独立CB栅极接触结构151A、151B及151C。应注意,与前一个具体实施例相比,在此示范制程流程中,不凹陷CB栅极接触结构130。
图31及图32图示在执行数个制程操作之后的IC产品100。首先,移除掩模层163。然后,各自在凹陷导电GSD接触结构133与栅极接触结构151之上,形成附加绝缘材料165于开口133X及151X的剩余部分中。可通过沉积一层绝缘材料,例如氮化硅,以便过填开口133X及151X,然后执行CMP制程,从而形成附加绝缘材料165。附加绝缘材料165可由与层119相同的材料制成,或可由不同的材料制成(以便促进自对准通孔稍后在制程中的形成)。
图33图示在执行数个制程操作之后的产品。首先,在该层绝缘材料中,形成导电接触132的接触开口132X,它会被形成为可建立电气连接至第三晶体管101C的源极/漏极接触结构120。之后,形成另一层牺牲材料167,例如,OPL材料,以便填满接触开口132X且在执行附加制程操作时暂时保护底下的源极/漏极接触结构120。可通过沉积OPL材料,然后执行CMP制程,从而形成牺牲材料167。
图34及图35图示在执行初始制程操作以形成上述导电M0金属化层于产品100之上之后的IC产品100。如前述,M0金属化层包含多个独立导线139A、139B(全体用附图标记139表示)。如图34及图35所示,用于导电金属线139的各种开口或沟槽169形成于绝缘材料层119、165中。通过通过图案化蚀刻掩模(未图示)使用传统光刻及蚀刻制程来执行蚀刻制程,可形成沟槽169。
图36及图37图示在执行数个制程操作之后的IC产品100。首先,移除牺牲材料167以便暴露邻接栅极3的源极/漏极接触结构120。然后,该方法涉及形成多个导电金属线139以及在绝缘材料层119、165中接触邻接栅极3的源极/漏极接触结构120的导电通孔170(参考图37的视图Y-Y)。如图示,第一金属线139A导电耦合且实体接触CB栅极接触130,同时第二导线139B导电耦合至与第三晶体管的源极/漏极接触结构120耦合的导电通孔170。应注意,如图36所示,由于GSD接触结构133的凹陷,第一金属线139A与GSD接触结构133实体(垂直)隔开,由此提供物理空间以安置在GSD接触结构133之上的第一导线139A。换言之,使用揭示于本文的新颖方法,凹陷GSD接触结构133不妨碍或阻挡第一金属线139A的形成,好像GSD接触结构133之前没有被凹陷一般。在一示范制程流程中,金属线139及通孔170的形成可使用类似以上在说明导电接触132的形成所描述的技术。
图38及图39图示在执行数个制程操作以形成示范M1金属化层于M0金属化层之上之后的IC产品100。M1金属化层包含多个示意图示的M1金属线及导电V0通孔。如图标,在产品之上形成一绝缘材料层171。之后,在产品100上的各种绝缘材料层中形成各种开口或沟槽。然后,用于导电M1金属线及导电V0通孔的导电材料形成于这些绝缘材料层的开口中且执行CMP制程。如图示,位在第二金属化层中的第一导线M1线及第一导电V0通孔导电耦合至CB栅极接触结构130。另外,多个第二导线M1与延伸长度的V0导电通孔位在该第二金属化层中且导电耦合至附加晶体管装置的独立CB栅极接触结构151中的一者。
以上所揭示的特定具体实施例均仅供图解说明,因为本领域技术人员在受益于本文的教导后显然可以不同但等效的方式来修改及实施本发明。例如,可用不同的顺序完成以上所提出的制程步骤。此外,除非在以下权利要求书中有提及,不希望本发明受限于本文所示的构造或设计的细节。因此,显然可改变或修改以上所揭示的特定具体实施例而所有此类变体都被认为仍然是在本发明的范畴与精神内。应注意,在本专利说明书及随附权利要求书中为了描述各种制程或结构而使用的例如“第一”、“第二”、“第三”或“第四”用语只是用来作为这些步骤/结构的简写参考且不一定暗示这些步骤/结构的执行/形成按照该有序序列。当然,取决于确切的权利要求语言,可能需要或不需要这些制程的有序序列。因此,本文提出以下的权利要求书寻求保护。
Claims (19)
1.一种形成栅极接触结构的方法,该方法包含:
在至少一层绝缘材料中形成栅极至源极/漏极(GSD)接触开口与栅极接触开口;
形成初始栅极至源极/漏极(GSD)接触结构于该GSD接触开口中以及初始栅极接触结构于该栅极接触开口中,其中,该初始GSD接触结构与该初始栅极接触结构中的各者的上表面位在第一层级;
对该初始GSD接触结构及该初始栅极接触结构执行凹陷蚀刻制程以形成凹陷GSD接触结构与凹陷栅极接触结构,其中,该凹陷GSD接触结构与该凹陷栅极接触结构中的各者的凹陷上表面位在低于该第一层级的第二层级;以及
形成附加绝缘材料于该凹陷GSD接触结构与该凹陷栅极接触结构中的各者的该凹陷上表面上,以及形成导电金属化层于该附加绝缘材料之上,使得该导电金属化层与该凹陷GSD接触结构实体隔开。
2.如权利要求1所述的方法,其中,形成该GSD接触开口包含:暴露第一晶体管的导电源极/漏极接触结构与第二晶体管的第一栅极结构中的至少一表面,且其中,该凹陷GSD接触结构导电耦合至该第一晶体管的该导电源极/漏极接触结构及该第二晶体管的该第一栅极结构。
3.如权利要求2所述的方法,其中,形成该GSD接触开口包含:暴露该导电源极/漏极接触结构的至少一侧面。
4.如权利要求2所述的方法,其中,形成该GSD接触开口包含:执行蚀刻制程以至少移除绝缘源极/漏极帽盖位在该导电源极/漏极接触结构之上的一部分,以便至少暴露该导电源极/漏极接触结构的上表面的一部分。
5.如权利要求2所述的方法,其中,形成该栅极接触开口包含:移除位在第三晶体管的第二栅极结构之上的栅极帽盖,其中,该栅极接触结构导电耦合至该第三晶体管的该第二栅极结构。
6.如权利要求1所述的方法,其中,该凹陷GSD接触结构导电耦合至具有绝缘源极/漏极帽盖的导电源极/漏极接触结构,该绝缘源极/漏极帽盖至少位在该导电源极/漏极接触结构的上表面的一部分之上,其中,该第二层级是在高于该绝缘源极/漏极帽盖的该上表面的层级的层级。
7.如权利要求1所述的方法,进一步包含:同时形成第一及第二独立导电接触结构,该第一独立导电接触结构位在该凹陷栅极接触结构之上且与该凹陷栅极接触结构导电耦合,该第二独立导电接触结构位于在晶体管装置的源极/漏极区之上的导电源极/漏极接触结构之上且与该晶体管装置的该源极/漏极区之上的该导电源极/漏极接触结构导电耦合。
8.如权利要求1所述的方法,进一步包含:形成单一导线,该单一导线垂直地位在该凹陷GSD接触结构与凹陷栅极接触结构两者的至少一部分之上,其中,该单一导线导电耦合至该凹陷栅极接触结构,且其中,绝缘材料垂直地位在该单一导线与该凹陷GSD接触结构之间。
9.如权利要求7所述的方法,进一步包含:形成第一及第二独立导线,该第一独立导线垂直地位在该凹陷GSD接触结构与该凹陷栅极接触结构两者的至少一部分之上,其中,该第一独立导线导电耦合至该第一独立导电接触结构,且其中,绝缘材料垂直地位在该第一独立导线与该凹陷GSD接触结构之间,该第二独立导线导电耦合至该第二独立导电接触结构。
10.如权利要求1所述的方法,进一步包含:在形成该GSD接触开口之前,形成该栅极接触开口。
11.如权利要求2所述的方法,其中,形成该GSD接触开口包含:移除邻接该第一晶体管的该导电源极/漏极接触结构的侧壁间隔件的至少一部分。
12.一种形成栅极接触结构的方法,该方法包含:
在至少一层绝缘材料中形成栅极至源极/漏极(GSD)接触开口与栅极接触开口;
形成初始栅极至源极/漏极(GSD)接触结构于该栅极至源极/漏极GSD接触开口中以及初始栅极接触结构于该栅极接触开口中,其中,该初始栅极至源极/漏极GSD接触结构与该初始栅极接触结构中的各者的上表面位在第一层级,该初始栅极至源极/漏极GSD接触结构导电耦合至具有绝缘源极/漏极帽盖的第一导电源极/漏极接触结构,该绝缘源极/漏极帽盖位在该导电源极/漏极接触结构的上表面的至少一部分之上;
同时在第一时间对该初始栅极至源极/漏极GSD接触结构与该初始栅极接触结构执行凹陷蚀刻制程以形成凹陷GSD接触结构与凹陷栅极接触结构,其中,该凹陷GSD接触结构与该凹陷栅极接触结构中的各者的凹陷上表面位在低于该第一层级的第二层级,且其中,该第二层级是在高于该绝缘源极/漏极帽盖的上表面的层级的层级;
同时在第二时间形成第一及第二独立导电接触结构,该第一独立导电接触结构位在该栅极接触结构之上且与该栅极接触结构导电耦合,该第二独立导电接触结构位在第二导电源极/漏极接触结构之上且与该第二导电源极/漏极接触结构导电耦合;以及
形成附加绝缘材料于该凹陷GSD接触结构与该凹陷栅极接触结构中的各者的该凹陷上表面上,以及形成导电金属化层于该附加绝缘材料之上,使得该导电金属化层与该凹陷GSD接触结构实体隔开。
13.如权利要求12所述的方法,其中,形成该GSD接触开口包含:暴露该第一导电源极/漏极接触结构的至少一侧面。
14.如权利要求13所述的方法,其中,形成该GSD接触开口包含:执行蚀刻制程以至少移除绝缘源极/漏极帽盖位在该第一导电源极/漏极接触结构之上的一部分以便至少暴露该第一导电源极/漏极接触结构的上表面的一部分。
15.如权利要求12所述的方法,进一步包含:形成第一及第二独立导线,该第一独立导线垂直地位在该凹陷GSD接触结构与该凹陷栅极接触结构两者的一部分之上,其中,该第一独立导线导电耦合至该第一独立导电接触结构,且其中,绝缘材料垂直地位在该第一独立导线与该凹陷GSD接触结构之间,该第二独立导线导电耦合至该第二独立导电接触结构。
16.一种集成电路(IC)产品,包含:
第一晶体管的第一导电源极/漏极接触结构;
绝缘源极/漏极帽盖,位在该第一导电源极/漏极接触结构的上表面的至少一部分之上;
栅极至源极/漏极(GSD)接触结构,导电耦合至该第一导电源极/漏极接触结构及第二晶体管的第一栅极结构;
栅极接触结构,导电耦合至第三晶体管的第二栅极结构,其中,该GSD接触结构与该栅极接触结构中的各者的上表面位在第二层级,该第二层级是在高于该绝缘源极/漏极帽盖的上表面的层级的层级;
附加绝缘材料,形成于该GSD接触结构与该栅极接触结构中的各者的该上表面上;以及
导电金属化层,形成于该附加绝缘材料之上,使得该导电金属化层与该GSD接触结构实体隔开。
17.如权利要求16所述的IC产品,其中,该GSD接触结构导电耦合至该第一导电源极/漏极接触结构的侧面与上表面中的至少一者。
18.如权利要求16所述的IC产品,其中,该第三晶体管进一步包含第二导电源极/漏极接触结构,且其中,该IC产品进一步包含第一及第二独立导电接触结构,该第一导电接触结构位在该栅极接触结构之上且与该栅极接触结构导电耦合,该第二导电接触位在该第二导电源极/漏极接触结构之上且与该第二导电源极/漏极接触结构导电耦合。
19.如权利要求18所述的IC产品,进一步包含:
第一导线,垂直地位在该GSD接触结构与该栅极接触结构两者的至少一部分之上,其中,该第一导线导电耦合至该第一导电接触结构,且其中,绝缘材料垂直地位在该第一导线与该GSD接触结构之间;以及
第二导线,垂直地位在该第二导电接触结构之上且与该第二导电接触结构导电耦合。
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CN109698166A (zh) | 2019-04-30 |
US20190123162A1 (en) | 2019-04-25 |
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US11469309B2 (en) | 2022-10-11 |
US20200203497A1 (en) | 2020-06-25 |
TWI677922B (zh) | 2019-11-21 |
US10651284B2 (en) | 2020-05-12 |
US12002869B2 (en) | 2024-06-04 |
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