CN109697306B - Encoder based on TDPL logic - Google Patents

Abstract

The invention discloses a TDPL logic-based encoder, which comprises nine working logics, namely a NOR gate and six buffers, wherein the three working logics are three-phase double-rail pre-charging logic respectively; when the evaluation signal is changed from low level to high level, the encoder realizes evaluation operation, and when the discharge control signal is changed from low level to high level, the encoder enters a discharge state to prepare for the next evaluation operation, so that the encoder of the invention realizes different logic functions only by configuring threshold voltage by taking a NOR gate of three-phase double-rail pre-charge logic as a basic unit, and the output is discharged to low level from the pre-charge high level in each working cycle, thereby the consumed energy is constant; the method has the advantages of resisting DPA attack while defending reverse engineering attack, and low power consumption.

Description

Encoder based on TDPL logic

Technical Field

The invention relates to an encoder, in particular to an encoder based on TDPL logic.

Background

With the continuous development of integrated circuit design and chip manufacturing, information leakage events occur continuously, attack modes such as reverse engineering and differential power analysis seriously threaten the safety of the integrated circuit design, and related safety problems are widely concerned. The reverse engineering is designed by reducing anatomical products, a circuit netlist is extracted, and the actual functions of the chip are mastered. Differential Power Analysis (DPA) collects Power leakage information and speculates data information, and both of the data information and the data information pose serious threats to chip security. Therefore, the digital device resistant to reverse engineering and differential power analysis has wide application prospect.

The encoder is one of the commonly used digital devices in digital circuit systems, is an important device for data communication, transmission and storage, and has important application in the aspects of audio and video compression and the like. In the aspect of the implementation technology of the encoder, the encoder implemented by the differential logic based on the lookup table needs more transistors, has higher power consumption, and has poor reverse engineering defense capability although having good DPA attack resistance. Hu Hui et al adopts multi-threshold CMOS tube technology, combines redundancy suppression technology with multi-threshold technology, designs multi-threshold encoder, and this circuit power consumption has been reduced, but has adverse engineering and differential power analysis ability poor, all can become the breakthrough of attack, and corresponding manufacturing cost has also improved.

Disclosure of Invention

The invention aims to provide a coder based on TDPL logic, which can resist reverse engineering and differential power analysis attacks simultaneously on the basis of low power consumption.

The technical scheme adopted by the invention for solving the technical problems is as follows: a TDPL logic-based encoder comprises nine NOR gates and six buffers, wherein nine working logics are three-phase double-rail pre-charging logic respectively, each NOR gate is provided with a first input end, a first inverted input end, a second inverted input end, an output end, an inverted output end, a pre-charging control end, a discharging control end and an evaluation control end respectively; -nine of said nor-gates are called first nor-gate, second nor-gate, third nor-gate, fourth nor-gate, fifth nor-gate, sixth nor-gate, seventh nor-gate, eighth nor-gate and ninth nor-gate, respectively, -six of said buffers are called first buffer, second buffer, third buffer, fourth buffer, fifth buffer and sixth buffer, respectively, -the input terminal of said first buffer, the discharge control terminal of said first nor-gate, the discharge control terminal of said second nor-gate, the discharge control terminal of said fourth nor-gate, the discharge control terminal of said fifth nor-gate, the discharge control terminal of said seventh nor-gate and the discharge control terminal of said eighth nor-gate are connected and the connection terminal thereof is the discharge control terminal of said encoder for accessing a discharge control signal, -the input terminal of said second buffer, the input terminal of said first buffer, the discharge control terminal of said seventh nor-gate and the discharge control terminal of said eighth nor-gate are connected and the connection terminal thereof is the discharge control terminal of said encoder for accessing a discharge control signal, -the evaluation of said second nor-gate, said first nor-gate and said second nor-gate are connected and said precharge control terminal of said fifth nor-gate are connected and said evaluation control terminal of said precharge control terminal of said encoder for accessing said precharge control terminal of said evaluation of said precharge control terminal of said fifth nor-gate, the first input terminal of the first nor gate, the first input terminal of the fourth nor gate and the first input terminal of the seventh nor gate are connected and the connection terminal thereof is the seventh input terminal of the encoder, and are configured to receive a 7 th bit encoded input signal, the first inverting input terminal of the first nor gate, the first inverting input terminal of the fourth nor gate and the first inverting input terminal of the seventh nor gate are connected and the connection terminal thereof is the seventh inverting input terminal of the encoder, and are configured to receive a 7 th bit inverted encoded input signal, the second input terminal of the first nor gate and the second input terminal of the fourth nor gate are connected and the connection terminal thereof is the sixth input terminal of the encoder, and are configured to receive a 6 th bit encoded input signal, the second inverting input terminal of the first nor gate is connected to the second inverting input terminal of the fourth nor gate, and the connection terminal thereof is the sixth inverting input terminal of the encoder, and is used for receiving a 6 th bit inverted encoded input signal, the first input terminal of the second nor gate is connected to the second input terminal of the seventh nor gate, and the connection terminal thereof is the fifth input terminal of the encoder, and is used for receiving a 5 th bit encoded input signal, the first inverting input terminal of the second nor gate is connected to the second inverting input terminal of the seventh nor gate, and the connection terminal thereof is the fifth inverting input terminal of the encoder, and is used for receiving a 5 th bit inverted encoded input signal, the second input terminal of the second nor gate is the fourth input terminal of the encoder, and is used for receiving a 4 th bit encoded input signal, and the second inverting input terminal of the second nor gate is the fourth inverting input terminal of the encoder, for receiving a 4 th bit encoded inverted input signal, a first input terminal of the fifth nor gate is connected to a first input terminal of the eighth nor gate and a connection terminal thereof is the third input terminal of the encoder for receiving a 3 rd bit encoded input signal, a first inverted input terminal of the fifth nor gate is connected to a first inverted input terminal of the eighth nor gate and a connection terminal thereof is the third inverted input terminal of the encoder for receiving a 3 rd bit encoded inverted input signal, a second input terminal of the fifth nor gate is a second input terminal of the encoder for receiving a 2 nd bit encoded input signal, a second inverted input terminal of the fifth nor gate is a second inverted input terminal of the encoder for receiving a 2 nd bit encoded inverted input signal, a second input terminal of the eighth nor gate is the first input terminal of the encoder, for receiving a 1 st bit encoded input signal, a second inverting input terminal of the eighth nor gate is a first inverting input terminal of the encoder, and is configured to receive the 1 st bit encoded input signal, an output terminal of the first buffer is connected to an input terminal of the fourth buffer, an output terminal of the second buffer is connected to an input terminal of the fifth buffer, an output terminal of the third buffer is connected to an input terminal of the sixth buffer, an output terminal of the fourth buffer, a discharge control terminal of the third nor gate, a discharge control terminal of the sixth nor gate is connected to a discharge control terminal of the ninth nor gate, an output terminal of the fifth buffer, a precharge control terminal of the third nor gate, a precharge control terminal of the sixth nor gate is connected to a precharge control terminal of the ninth nor gate, the output of said sixth buffer, the evaluation control terminal of said third nor gate, the evaluation control terminal of said sixth nor gate and the evaluation control terminal of said ninth nor gate are connected, the output of said first nor gate and the first inverting input of said third nor gate are connected, the inverting output of said first nor gate and the first input of said third nor gate are connected, the output of said second nor gate and the second inverting input of said third nor gate are connected, the inverting output of said second nor gate and the second input of said third nor gate are connected, the output of said fourth nor gate and the first inverting input of said sixth nor gate are connected, the inverting output of said fourth nor gate and the first input of said sixth nor gate are connected, the output of said fifth nor gate and the second inverting input of said sixth nor gate are connected, the inverting output of said sixth nor gate and the first input of said sixth nor gate are connected, the inverting output of said fifth nor gate and the inverting input of said seventh nor gate are connected, the output of said ninth nor gate and the third inverting input of said ninth nor gate is connected, the output of said seventh nor gate and the third nor gate is connected, the third and the third inverting input of said ninth nor gate is connected, the seventh nor gate is connected, the third and the third input of said ninth nor gate is connected, the output end of the sixth NOR gate is the second output end of the encoder and is used for outputting the 2 nd bit encoded output signal, the inverted output end of the sixth NOR gate is the second inverted output end of the encoder and is used for outputting the 2 nd bit inverted encoded output signal, the output end of the ninth NOR gate is the first output end of the encoder and is used for outputting the 1 st bit encoded output signal, and the inverted output end of the ninth NOR gate is the first inverted output end of the encoder and is used for outputting the 1 st bit inverted encoded output signal.

Each NOR gate comprises a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a first NMOS (N-channel metal oxide semiconductor) tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube, a tenth NMOS tube, an eleventh NMOS tube, a twelfth NMOS tube, a thirteenth NMOS tube, a fourteenth NMOS tube, a fifteenth NMOS tube, a sixteenth NMOS tube, a seventeenth NMOS tube, an eighteenth NMOS tube, a nineteenth NMOS tube, a twentieth NMOS tube and a twenty-first NMOS tube; the source electrode of the first PMOS tube is connected with a power supply, the grid electrode of the first PMOS tube, the grid electrode of the first NMOS tube and the grid electrode of the fourth NMOS tube are connected, and the connecting end of the first PMOS tube, the grid electrode of the first NMOS tube and the grid electrode of the fourth NMOS tube is the discharge control end of the NOR gate. The drain electrode of the first PMOS transistor, the source electrode of the second PMOS transistor, the source electrode of the third PMOS transistor, the source electrode of the fourth PMOS transistor and the source electrode of the fifth PMOS transistor are connected, the gate electrode of the second PMOS transistor and the gate electrode of the fifth PMOS transistor are connected, and the connection end thereof is the precharge control end of the nor gate, the drain electrode of the second PMOS transistor, the drain electrode of the third PMOS transistor, the drain electrode of the first NMOS transistor, the drain electrode of the second NMOS transistor, the gate electrode of the fourth PMOS transistor and the gate electrode of the third NMOS transistor are connected, and the connection end thereof is the output end of the nor gate, the gate electrode of the third PMOS transistor, the gate electrode of the second NMOS transistor, the drain electrode of the fourth PMOS transistor, the drain electrode of the third NMOS transistor, the drain electrode of the fifth PMOS transistor and the drain electrode of the fourth NMOS transistor are connected, and the connection end thereof is the inverted output end of the nor gate; the source of the first NMOS transistor is grounded, the drain of the second NMOS transistor, the drain of the fifth NMOS transistor, the drain of the sixth NMOS transistor, the drain of the seventh NMOS transistor and the drain of the eighth NMOS transistor are connected, the source of the third NMOS transistor, the drain of the ninth NMOS transistor, the drain of the tenth NMOS transistor, the drain of the eleventh NMOS transistor and the drain of the twelfth NMOS transistor are connected, the source of the fourth NMOS transistor is grounded, the gate of the fifth NMOS transistor, the gate of the seventh NMOS transistor, the gate of the tenth NMOS transistor and the gate of the twelfth NMOS transistor are connected, and the connection end thereof is the first input end of the nor gate, the source of the fifth NMOS transistor and the drain of the thirteenth NMOS transistor are connected, the gate of the sixth NMOS transistor, the gate of the eighth NMOS transistor, the gate of the ninth NMOS transistor and the gate of the eleventh NMOS transistor are connected, and the connection end thereof is the inverted input end of the nor gate, a source electrode of the sixth NMOS transistor is connected to a drain electrode of the fourteenth NMOS transistor, a source electrode of the seventh NMOS transistor is connected to a drain electrode of the fifteenth NMOS transistor, a source electrode of the eighth NMOS transistor is connected to a drain electrode of the sixteenth NMOS transistor, a source electrode of the ninth NMOS transistor is connected to a drain electrode of the seventeenth NMOS transistor, a source electrode of the tenth NMOS transistor is connected to a drain electrode of the eighteenth NMOS transistor, a source electrode of the eleventh NMOS transistor is connected to a drain electrode of the nineteenth NMOS transistor, a source electrode of the twelfth NMOS transistor is connected to a drain electrode of the twentieth NMOS transistor, a gate electrode of the thirteenth NMOS transistor, a gate electrode of the fourteenth NMOS transistor, a gate electrode of the tenth NMOS transistor and a gate electrode of the nineteenth NMOS transistor are connected, and a gate connecting end of the ninth NMOS transistor is a second input end of the nor gate, a source of the thirteenth NMOS transistor, a source of the fourteenth NMOS transistor, a source of the fifteenth NMOS transistor, a source of the sixteenth NMOS transistor, a source of the seventeenth NMOS transistor, a source of the eighteenth NMOS transistor, a source of the nineteenth NMOS transistor, a source of the twentieth NMOS transistor and a drain of the twenty-first NMOS transistor are connected, a gate of the fifteenth NMOS transistor, a gate of the sixteenth NMOS transistor, a gate of the seventeenth NMOS transistor and a gate of the eighteenth NMOS transistor are connected, a connection end of the gate of the fifteenth NMOS transistor and the gate of the eighteenth NMOS transistor is a second inverting input end of the nor gate, a gate of the twenty-first NMOS transistor is an evaluation control end of the nor gate, and a source of the twenty-first NMOS transistor is grounded, the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, and the fifth PMOS transistor are common threshold voltage PMOS transistors, the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor, and the twenty-first NMOS transistor are common threshold voltage NMOS transistors, the fifth NMOS transistor, the sixth NMOS transistor, the seventh NMOS transistor, the ninth NMOS transistor, the thirteenth NMOS transistor, the fourteenth NMOS transistor, the fifteenth NMOS transistor, and the seventeenth NMOS transistor are low threshold voltage NMOS transistors, and the eighth NMOS transistor, the tenth NMOS transistor, the eleventh NMOS transistor, the twelfth NMOS transistor, the sixteenth NMOS transistor, the eighteenth NMOS transistor, the nineteenth NMOS transistor, and the twentieth NMOS transistor are high threshold voltage NMOS transistors. The NOR gate based on the three-phase double-rail pre-charge logic has three stages, namely a pre-charge stage, an evaluation stage and a discharge stage in each working cycle, the level of the output end of the NOR gate is discharged from a power supply voltage VDD to a low level VSS in each working cycle, the consumed energy is constant, and the NOR gate has the characteristic that the energy consumption and the processed data are mutually independent, so that the NOR gate has good capability of resisting power consumption attack.

The threshold voltage of the common threshold voltage PMOS tube is-0.404V, the threshold voltage of the common threshold voltage NMOS tube is 0.397V, the threshold voltage of the low threshold voltage NMOS tube is 0.243V, and the threshold voltage of the high threshold voltage NMOS tube is 0.489V.

Each buffer respectively comprises a first phase inverter and a second phase inverter, the input end of the first phase inverter is the input end of the buffer, the output end of the first phase inverter is connected with the input end of the second phase inverter, and the output end of the second phase inverter is the output end of the buffer.

Compared with the prior art, the invention provides an encoder circuit scheme capable of defending reverse engineering and DPA attack by researching the relation between a logic confusion circuit and data power consumption, adopting three-phase double-rail pre-charging logic and utilizing the threshold voltage characteristic. The invention has the advantages that the encoder is formed by nine two-input NOR gates and six buffers, the working logic of each NOR gate is respectively a three-phase double-rail pre-charging logic, the encoder realizes one-time encoding operation in one period, and the one period is divided into three stages, when the discharging control signal and the pre-charging control signal enter low level, the encoder enters the pre-charging stage; when the evaluation signal is changed from low level to high level, the evaluation stage is entered, and the encoder realizes evaluation operation to realize the function of the circuit; when the discharge control signal changes from low level to high level, the encoder enters a discharge state to prepare for the next evaluation operation. The encoder of the invention uses the NOR gate of the three-phase double-rail precharging logic as the basic unit of the encoder, the NOR gate unit realizes different logic functions only by configuring the threshold voltage, and each NOR gate discharges from the precharging high level to the low level in each working period, the consumed energy is constant, and the characteristics of the energy consumption and the processed data are mutually independent. Similarly, the encoder circuit of the invention also has the characteristic that the energy consumption and the processed data are mutually independent, so that the encoder circuit has the characteristic of resisting DPA attack while defending against reverse engineering attack, and has lower power consumption.

Drawings

FIG. 1 is a circuit diagram of a TDPL logic-based encoder of the present invention;

FIG. 2 is a circuit diagram of a NOR gate of a TDPL logic-based encoder of the present invention;

FIG. 3 is a circuit diagram of a buffer of an encoder based on TDPL logic according to the present invention;

FIG. 4 is a timing diagram illustrating the operation of the NOR gate of the encoder based on TDPL logic according to the present invention;

FIG. 5 is a simulation diagram of a NOR gate of an encoder based on TDPL logic according to the present invention;

fig. 6 is a simulation diagram of an encoder based on TDPL logic of the present invention.

Detailed Description

The invention is described in further detail below with reference to the following examples of the drawings.

The first embodiment is as follows: as shown in fig. 1, an encoder based on TDPL logic includes nine nor gates and six buffers, where the nine working logics are three-phase dual-rail pre-charging logics, and each of the nor gates has a first input terminal, a first inverted input terminal, a second inverted input terminal, an output terminal, an inverted output terminal, a pre-charging control terminal, a discharging control terminal, and an evaluation control terminal; the nine NOR gates are respectively referred to as a first NOR gate NOR1, a second NOR gate NOR2, a third NOR gate NOR3, a fourth NOR gate NOR4, a fifth NOR gate NOR5, a sixth NOR gate NOR6, a seventh NOR gate NOR7, an eighth NOR gate NOR8, and a ninth NOR gate NOR9, and the six buffers are respectively referred to as a first buffer BUFF1, a second buffer BUFF2, a third buffer BUFF3, a fourth buffer BUFF4, a fifth buffer BUFF4A buffer BUFF5 and a sixth buffer BUFF6, an input terminal of the first buffer BUFF1, a discharge control terminal of the first NOR gate NOR1, a discharge control terminal of the second NOR gate NOR2, a discharge control terminal of the fourth NOR gate NOR4, a discharge control terminal of the fifth NOR gate NOR5, a discharge control terminal of the seventh NOR gate NOR7 and a discharge control terminal of the eighth NOR gate NOR8 are connected and connection terminals thereof are discharge control terminals of the encoder, an input terminal of the second buffer BUFF2, a precharge control terminal of the first NOR gate NOR1, a precharge control terminal of the second NOR gate NOR2, a precharge control terminal of the fourth NOR gate NOR4, a precharge control terminal of the fifth NOR gate NOR5, a precharge control terminal of the seventh NOR gate NOR7 and a precharge control terminal of the eighth NOR gate NOR8 are connected and a connection terminal thereof is a precharge control terminal of the encoder, for receiving a precharge control signal CHARGEB, an input terminal of the third buffer BUFF3, an evaluation control terminal of the first NOR gate NOR1, an evaluation control terminal of the second NOR gate NOR2, an evaluation control terminal of the fourth NOR gate NOR4, an evaluation control terminal of the fifth NOR gate NOR5, an evaluation control terminal of the seventh NOR gate NOR7 and an evaluation control terminal of the eighth NOR gate NOR8 are connected and their connection terminals are evaluation control terminals of the encoder, for the purpose of receiving the evaluation control signal EVAL, a first input of the first NOR gate NOR1, a first input of the fourth NOR gate NOR4 and a first input of the seventh NOR gate NOR7 are connected and their connection terminals are a seventh input of the encoder, for receiving the 7 th bit-encoded input signal I7, the first inverting input terminal of the first NOR gate NOR1, the first inverting input terminal of the fourth NOR gate NOR4 and the first inverting input terminal of the seventh NOR gate NOR7 are connected and their connection terminals are the seventh inverting input terminal of the encoder for receiving the 7 th bit-encoded input signal.

The second input terminal of the first NOR gate NOR1 and the second input terminal of the fourth NOR gate NOR4 are connected and the connection terminal thereof is the sixth input terminal of the encoder for receiving the 6 th bit encoded input signal I6, the second inverting input terminal of the first NOR gate NOR1 and the second inverting input terminal of the fourth NOR gate NOR4 are connected and the connection terminal thereof is the sixth inverting input terminal of the encoder for receiving the sixth inverting input terminal of the encoderInput the 6 th bit reverse-phase coded input signal

A first input terminal of the second NOR gate NOR2 and a second input terminal of the seventh NOR gate NOR7 are connected and a connection terminal thereof is a fifth input terminal of the encoder for receiving the 5 th bit encoded input signal I5, a first inverting input terminal of the second NOR gate NOR2 and a second inverting input terminal of the seventh NOR gate NOR7 are connected and a connection terminal thereof is a fifth inverting input terminal of the encoder for receiving the 5 th bit inverted encoded input signal

The second input terminal of the second NOR gate NOR2 is the fourth input terminal of the encoder for receiving the 4 th bit encoded input signal I4, and the second inverting input terminal of the second NOR gate NOR2 is the fourth inverting input terminal of the encoder for receiving the 4 th bit inverted encoded input signal

The first input terminal of the fifth NOR gate NOR5 is connected to the first input terminal of the eighth NOR gate NOR8, the connection terminal thereof being the third input terminal of the encoder for receiving the 3 rd bit encoded input signal I3, the first inverting input terminal of the fifth NOR gate NOR5 is connected to the first inverting input terminal of the eighth NOR gate NOR8, the connection terminal thereof being the third inverting input terminal of the encoder for receiving the 3 rd bit inverted encoded input signal

The second input terminal of the fifth NOR gate NOR5 is the second input terminal of the encoder for receiving the 2 nd bit encoded input signal I2, and the second inverting input terminal of the fifth NOR gate NOR5 is the second inverting input terminal of the encoder for receiving the 2 nd bit inverted encoded input signal

The second input terminal of the eighth NOR gate NOR8 is the first input terminal of the encoder for receiving the 1 st bit encoded input signal I1, the second inverting input terminal of the eighth NOR gate NOR8A first inverting input terminal of the encoder for receiving a 1 st bit inverting encoded input signal

An output terminal of the first buffer BUFF1 and an input terminal of the fourth buffer BUFF4 are connected, an output terminal of the second buffer BUFF2 and an input terminal of the fifth buffer BUFF5, an output terminal of the third buffer BUFF3 and an input terminal of the sixth buffer BUFF6 are connected, an output terminal of the fourth buffer BUFF4, a discharge control terminal of the third NOR gate NOR3, a discharge control terminal of the sixth NOR gate NOR6 and a discharge control terminal of the ninth NOR gate NOR9 are connected, an output terminal of the fifth buffer BUFF5, a precharge control terminal of the third NOR gate NOR3, a precharge control terminal of the sixth NOR gate NOR6 and a precharge control terminal of the ninth NOR gate NOR9 are connected, an output terminal of the sixth buffer BUFF6, an evaluation control terminal of the third NOR gate NOR3, an evaluation control terminal of the sixth NOR gate 6 and an evaluation control terminal of the ninth NOR gate NOR9 are connected, an output terminal of the first NOR1 and an inverted input terminal of the third NOR gate NOR3 are connected, an inverting output terminal of the first NOR gate NOR1 is connected to a first input terminal of the third NOR gate NOR3, an output terminal of the second NOR gate NOR2 is connected to a second inverting input terminal of the third NOR gate NOR3, an inverting output terminal of the second NOR gate NOR2 is connected to a second input terminal of the third NOR gate NOR3, an output terminal of the fourth NOR gate NOR4 is connected to a first inverting input terminal of the sixth NOR gate NOR6, an inverting output terminal of the fourth NOR gate NOR4 is connected to a first input terminal of the sixth NOR gate NOR6, an output terminal of the fifth NOR gate NOR5 is connected to the second inverting input terminal of the sixth NOR gate NOR6, an inverting output terminal of the fifth NOR gate NOR5 is connected to the second input terminal of the sixth NOR gate NOR6, an output terminal of the seventh NOR gate NOR7 is connected to the first inverting input terminal of the ninth NOR gate NOR9, an inverting output terminal of the seventh NOR gate NOR7 is connected to the first input terminal of the ninth NOR gate NOR9, an output terminal of the eighth NOR gate NOR8 is connected to the second inverting input terminal of the ninth NOR gate NOR9, an inverting output terminal of the eighth NOR gate NOR8 is connected to a second input terminal of the ninth NOR gate NOR9, and an output terminal of the third NOR gate NOR3 is a third output terminal of the encoder for outputting a 3 rd bit encoded outputThe inverted output terminal of the third NOR gate NOR3 is the third inverted output terminal of the encoder for outputting the 3 rd bit inverted encoded output signal

The output terminal of the sixth NOR gate NOR6 is the second output terminal of the encoder for outputting the 2 nd bit encoded output signal Y1, and the inverted output terminal of the sixth NOR gate NOR6 is the second inverted output terminal of the encoder for outputting the 2 nd bit inverted encoded output signal

The output terminal of the ninth NOR gate NOR9 is the first output terminal of the encoder for outputting the 1 st bit encoded output signal Y0, and the inverted output terminal of the ninth NOR gate NOR9 is the first inverted output terminal of the encoder for outputting the 1 st bit inverted encoded output signal

In this embodiment, as shown in fig. 2, each nor gate includes a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a fourth NMOS transistor N4, a fifth NMOS transistor N5, a sixth NMOS transistor N6, a seventh NMOS transistor N7, an eighth NMOS transistor N8, a ninth NMOS transistor N9, a tenth NMOS transistor N10, an eleventh NMOS transistor N11, a twelfth NMOS transistor N12, a thirteenth NMOS transistor N13, a fourteenth NMOS transistor N14, a fifteenth NMOS transistor N15, a sixteenth NMOS transistor N16, a seventeenth NMOS transistor N17, an eighteenth NMOS transistor N18, a nineteenth NMOS transistor N19, a twentieth NMOS transistor N20, and a twenty-first NMOS transistor N21, respectively; the source electrode of the first PMOS tube P1 is connected with a power supply VDD, the grid electrode of the first PMOS tube P1, the grid electrode of the first NMOS tube N1 and the grid electrode of the fourth NMOS tube N4 are connected, and the connecting end of the grid electrode of the first PMOS tube P1 and the grid electrode of the fourth NMOS tube N4 is the discharge control end of the NOR gate. The drain electrode of the first PMOS tube P1, the source electrode of the second PMOS tube P2, the source electrode of the third PMOS tube P3, the source electrode of the fourth PMOS tube P4 and the source electrode of the fifth PMOS tube P5 are connected, the grid electrode of the second PMOS tube P2 is connected with the grid electrode of the fifth PMOS tube P5, the connection end of the grid electrode of the second PMOS tube P2 is the pre-charge control end of the NOR gate, the drain electrode of the second PMOS tube P2, the drain electrode of the third PMOS tube P3, the drain electrode of the first NMOS tube N1, the drain electrode of the second NMOS tube N2, the grid electrode of the fourth PMOS tube P4 is connected with the grid electrode of the third NMOS tube N3, the connection end of the grid electrode of the third PMOS tube P3, the grid electrode of the second NMOS tube N2, the drain electrode of the fourth PMOS tube P4, the drain electrode of the third NMOS tube N3, the drain electrode of the fifth PMOS tube P5 is connected with the drain electrode of the fourth NMOS tube N4, and the connection end of the reverse phase of the NOR gate; a source electrode of the first NMOS transistor N1 is grounded VSS, a source electrode of the second NMOS transistor N2, a drain electrode of the fifth NMOS transistor N5, a drain electrode of the sixth NMOS transistor N6, a drain electrode of the seventh NMOS transistor N7 and a drain electrode of the eighth NMOS transistor N8 are connected, a source electrode of the third NMOS transistor N3, a drain electrode of the ninth NMOS transistor N9, a drain electrode of the tenth NMOS transistor N10, a drain electrode of the eleventh NMOS transistor N11 and a drain electrode of the twelfth NMOS transistor N12 are connected, a source electrode of the fourth NMOS transistor N4 is grounded VSS, a gate electrode of the fifth NMOS transistor N5, a gate electrode of the seventh NMOS transistor N7, a gate electrode of the tenth NMOS transistor N10 and a gate electrode of the twelfth NMOS transistor N12 are connected and a connection end thereof is a first input end of a nor gate, a source electrode of the fifth NMOS transistor N5 and a drain electrode of the thirteenth NMOS transistor N13 are connected, a gate electrode of the sixth NMOS transistor N6, a gate electrode of the eighth NMOS transistor N8, a gate electrode of the ninth NMOS transistor N9 and a gate electrode of the eleventh NMOS transistor N11 are connected and a connection end thereof is an inverted input end of the nor gate, a source electrode of a sixth NMOS transistor N6 is connected to a drain electrode of a fourteenth NMOS transistor N14, a source electrode of a seventh NMOS transistor N7 is connected to a drain electrode of a fifteenth NMOS transistor N15, a source electrode of an eighth NMOS transistor N8 is connected to a drain electrode of a sixteenth NMOS transistor N16, a source electrode of a ninth NMOS transistor N9 is connected to a drain electrode of a seventeenth NMOS transistor N17, a source electrode of a tenth NMOS transistor N10 is connected to a drain electrode of an eighteenth NMOS transistor N18, a source electrode of an eleventh NMOS transistor N11 is connected to a drain electrode of a nineteenth NMOS transistor N19, a source electrode of the twelfth NMOS transistor N12 is connected to a drain electrode of the twentieth NMOS transistor N20, a gate electrode of the thirteenth NMOS transistor N13, a gate electrode of the fourteenth NMOS transistor N14, a gate electrode of the nineteenth NMOS transistor N19 and a gate electrode of the twentieth NMOS transistor N20 are connected, and a connection end thereof is a second input end of the NOR gate, a source electrode of the thirteenth NMOS transistor N13, a source electrode of the fourteenth NMOS transistor N14, a source electrode of the fifteenth NMOS transistor N15, a source electrode of the sixteenth NMOS transistor N16, a source electrode of the seventeenth NMOS transistor N17, a source electrode of the eighteenth NMOS transistor N18, a gate electrode of the twelfth NMOS transistor N20, a gate electrode of the fourteenth NMOS transistor N14, a gate electrode of the fifteenth NMOS transistor N15, a gate electrode of the sixteenth NMOS transistor N16, a source electrode of the seventeenth NMOS transistor N17, a gate electrode of the eighteenth NMOS transistor N18, a gate electrode of the NMOS transistor, and a gate electrode of the NMOS transistor N20, the source electrode of the nineteenth NMOS transistor N19, the source electrode of the twentieth NMOS transistor N20 and the drain electrode of the twenty-first NMOS transistor N21 are connected, the gate electrode of the fifteenth NMOS transistor N15, the gate electrode of the sixteenth NMOS transistor N16, the gate electrode of the seventeenth NMOS transistor N17 and the gate electrode of the eighteenth NMOS transistor N18 are connected, and the connection end thereof is the second inverting input end of the NOR gate, the grid electrode of a twenty-first NMOS transistor N21 is an evaluation control end of a NOR gate, the source electrode of the twenty-first NMOS transistor N21 is grounded VSS, a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4 and a fifth PMOS transistor P5 are all common threshold voltage PMOS transistors, the first NMOS transistor N1, the second NMOS transistor N2, the third NMOS transistor N3, the fourth NMOS transistor N4, and the twenty-first NMOS transistor N21 are common threshold voltage NMOS transistors, the fifth NMOS transistor N5, the sixth NMOS transistor N6, the seventh NMOS transistor N7, the ninth NMOS transistor N9, the thirteenth NMOS transistor N13, the fourteenth NMOS transistor N14, the fifteenth NMOS transistor N15, and the seventeenth NMOS transistor N17 are low threshold voltage NMOS transistors, and the eighth NMOS transistor N8, the tenth NMOS transistor N10, the eleventh NMOS transistor N11, the twelfth NMOS transistor N12, the sixteenth NMOS transistor N16, the eighteenth NMOS transistor N18, the nineteenth NMOS transistor N19, and the twentieth NMOS transistor N20 are high threshold voltage NMOS transistors.

In this embodiment, the threshold voltage of the common threshold voltage PMOS transistor is-0.404V, the threshold voltage of the common threshold voltage NMOS transistor is 0.397V, the threshold voltage of the low threshold voltage NMOS transistor is 0.243V, and the threshold voltage of the high threshold voltage NMOS transistor is 0.489V.

Example two: this embodiment is substantially the same as the first embodiment, except that: in this embodiment, as shown in fig. 3, each buffer includes a first inverter INV1 and a second inverter INV2, an input end of the first inverter INV1 is an input end of the buffer, an output end of the first inverter INV1 is connected to an input end of the second inverter INV2, and an output end of the second inverter INV2 is an output end of the buffer.

The operational timing diagram of the nor gate of the TDPL logic-based codec of the present invention is shown in fig. 4, and it can be seen from analyzing fig. 4 that: the working process of the NOR gate is divided into three stages of pre-charging, evaluation and discharging in each period, when a pre-charging control signal CHARGEB, a discharging control signal DISCHARGE and an evaluation control signal EVAL are all low level, the NOR gate enters the pre-charging stage, the first PMOS tube P1, the second PMOS tube P2 and the fifth PMOS tube are conducted, and the output end O of the NOR gate is conductedUT and inverting output

Precharging to a high level; with the evaluation control signal EVAL and the precharge control signal charge changed to high level and the DISCHARGE control signal DISCHARGE kept unchanged at the previous low level state, the second PMOS transistor P2 and the fifth PMOS transistor P5 are turned off, the circuit precharge is finished, and at the same time, the twenty-first NMOS transistor N21 of the evaluation transistor is turned on, the circuit enters the evaluation phase, at this time, the first input signal a =1 and the second input signal B =1, the fifth NMOS transistor N5, the thirteenth NMOS transistor N13, the twelfth NMOS transistor N12 and the twentieth NMOS transistor N20 in the pull-down network are turned on, the gate voltages of the second NMOS transistor N2 and the third NMOS transistor N3 are precharged to high level before, therefore, currents flow through the second NMOS transistor N2 and the third NMOS transistor N3, the current flowing through the second NMOS transistor N2 is denoted as I1, the current flowing through the third NMOS transistor N3 is denoted as I2, and since the fifth NMOS transistor N5 and the thirteenth NMOS transistor N13 are low-threshold transistors, a sense amplifier composed of the third PNOS transistor P3, the fourth PMOS transistor P4, the second NMOS transistor N2, and the third NMOS transistor N3 amplifies a difference between the current I1 and the current I2, the output terminal of the nor gate DISCHARGEs to a low level at first, the fourth PMOS transistor P4 is turned on, and the inverted output terminal OUT of the nor gate is turned on

Still remains high; when the evaluation control signal EVAL is low level and the DISCHARGE control signal DISCHARGE is high level, the pre-charge control signal CHARGEB keeps the last state, the twenty-first NMOS transistor N21 is cut off, the evaluation is finished, the first NMOS transistor N1 and the fourth NMOS transistor N4 are conducted at the same time, the circuit enters a DISCHARGE stage, and the output end OUT and the reverse output end of the NOR gate

And discharging to a low level, finishing one working period and realizing the NOR logic function.

Similarly, for the invention, the working process of the invention is mainly composed of NOR gates with the same structure and is also divided into three stages of pre-charging, evaluating and discharging. When the pre-charge control signal CHARGEB, the DISCHARGE control signal DISCHARGE and the evaluation control signal EVAL are all low level, the encoder of the invention enters a pre-charge stage, thirty-two output ports are all charged to high level, the DISCHARGE control signal DISCHARGE keeps low level along with the change of the evaluation control signal EVAL and the pre-charge control signal CHARGEB to high level, the encoder enters an evaluation stage, when the evaluation control signal EVAL is low level and the DISCHARGE control signal DISCHARGEG changes to high level, the pre-charge control signal CHARGEB keeps high level, the evaluation is finished, the encoder enters a DISCHARGE stage, one working cycle is finished, and the encoding function is realized.

Fig. 5 shows a simulation diagram of a nor gate of an encoder based on TDPL logic according to the present invention, fig. 6 shows a simulation diagram of an encoder based on TDPL logic according to the present invention, and fig. 5 shows that the nor gate has a correct logic function, and fig. 6 shows that the logic function of the encoder is correct.

Claims (4)

1. An encoder based on TDPL logic is characterized by comprising nine NOR gates and six buffers, wherein the nine working logics are three-phase double-rail pre-charging logics respectively, and each NOR gate is provided with a first input end, a first inverted input end, a second inverted input end, an output end, an inverted output end, a pre-charging control end, a discharging control end and an evaluation control end respectively; -nine of said nor-gates are called first nor-gate, second nor-gate, third nor-gate, fourth nor-gate, fifth nor-gate, sixth nor-gate, seventh nor-gate, eighth nor-gate and ninth nor-gate, respectively, -six of said buffers are called first buffer, second buffer, third buffer, fourth buffer, fifth buffer and sixth buffer, respectively, -the input terminal of said first buffer, the discharge control terminal of said first nor-gate, the discharge control terminal of said second nor-gate, the discharge control terminal of said fourth nor-gate, the discharge control terminal of said fifth nor-gate, the discharge control terminal of said seventh nor-gate and the discharge control terminal of said eighth nor-gate are connected and the connection terminal thereof is the discharge control terminal of said encoder for accessing a discharge control signal, -the input terminal of said second buffer, the input terminal of said first buffer, the discharge control terminal of said seventh nor-gate and the discharge control terminal of said eighth nor-gate are connected and the connection terminal thereof is the discharge control terminal of said encoder for accessing a discharge control signal, -the evaluation of said second nor-gate, said first nor-gate and said second nor-gate are connected and said precharge control terminal of said fifth nor-gate are connected and said evaluation control terminal of said precharge control terminal of said encoder for accessing said precharge control terminal of said evaluation of said precharge control terminal of said fifth nor-gate, the first input terminal of the first nor gate, the first input terminal of the fourth nor gate and the first input terminal of the seventh nor gate are connected and the connection terminal thereof is the seventh input terminal of the encoder, and are configured to receive a 7 th bit encoded input signal, the first inverting input terminal of the first nor gate, the first inverting input terminal of the fourth nor gate and the first inverting input terminal of the seventh nor gate are connected and the connection terminal thereof is the seventh inverting input terminal of the encoder, and are configured to receive a 7 th bit inverted encoded input signal, the second input terminal of the first nor gate and the second input terminal of the fourth nor gate are connected and the connection terminal thereof is the sixth input terminal of the encoder, and are configured to receive a 6 th bit encoded input signal, the second inverting input terminal of the first nor gate is connected to the second inverting input terminal of the fourth nor gate, and the connection terminal thereof is the sixth inverting input terminal of the encoder, and is configured to receive a 6 th bit inverting encoded input signal, the first input terminal of the second nor gate is connected to the second input terminal of the seventh nor gate, and the connection terminal thereof is the fifth input terminal of the encoder, and is configured to receive a 5 th bit encoded input signal, the first inverting input terminal of the second nor gate is connected to the second inverting input terminal of the seventh nor gate, and the connection terminal thereof is the fifth inverting input terminal of the encoder, and is configured to receive a 5 th bit inverting encoded input signal, the second input terminal of the second nor gate is the fourth input terminal of the encoder, and is configured to receive a 4 th bit encoded input signal, and the second inverting input terminal of the second nor gate is the fourth inverting input terminal of the encoder, for receiving a 4 th bit encoded inverted input signal, a first input terminal of the fifth nor gate is connected to a first input terminal of the eighth nor gate and a connection terminal thereof is the third input terminal of the encoder for receiving a 3 rd bit encoded input signal, a first inverted input terminal of the fifth nor gate is connected to a first inverted input terminal of the eighth nor gate and a connection terminal thereof is the third inverted input terminal of the encoder for receiving a 3 rd bit encoded inverted input signal, a second input terminal of the fifth nor gate is a second input terminal of the encoder for receiving a 2 nd bit encoded input signal, a second inverted input terminal of the fifth nor gate is a second inverted input terminal of the encoder for receiving a 2 nd bit encoded inverted input signal, a second input terminal of the eighth nor gate is the first input terminal of the encoder, the second inverting input terminal of the eighth nor gate is the first inverting input terminal of the encoder, and is configured to receive the 1 st bit inverting encoded input signal, the output terminal of the first buffer is connected to the input terminal of the fourth buffer, the output terminal of the second buffer is connected to the input terminal of the fifth buffer, the output terminal of the third buffer is connected to the input terminal of the sixth buffer, the output terminal of the fourth buffer, the discharge control terminal of the third nor gate, the discharge control terminal of the sixth nor gate is connected to the discharge control terminal of the ninth nor gate, the output terminal of the fifth buffer, the precharge control terminal of the third nor gate, the precharge control terminal of the sixth nor gate is connected to the precharge control terminal of the ninth nor gate, the output of said sixth buffer, the evaluation control terminal of said third nor gate, the evaluation control terminal of said sixth nor gate and the evaluation control terminal of said ninth nor gate are connected, the output of said first nor gate and the first inverting input of said third nor gate are connected, the inverting output of said first nor gate and the first input of said third nor gate are connected, the output of said second nor gate and the second inverting input of said third nor gate are connected, the inverting output of said second nor gate and the second input of said third nor gate are connected, the output of said fourth nor gate and the first inverting input of said sixth nor gate are connected, the inverting output of said fourth nor gate and the first input of said sixth nor gate are connected, the output of said fifth nor gate and the second inverting input of said sixth nor gate are connected, the inverting output of said sixth nor gate and the first input of said sixth nor gate are connected, the inverting output of said fifth nor gate and the inverting input of said seventh nor gate are connected, the output of said ninth nor gate and the third inverting input of said ninth nor gate is connected, the output of said seventh nor gate and the third nor gate is connected, the third and the third inverting input of said ninth nor gate is connected, the seventh nor gate is connected, the third and the third input of said ninth nor gate is connected, the output end of the sixth NOR gate is the second output end of the encoder and is used for outputting the 2 nd bit encoded output signal, the inverted output end of the sixth NOR gate is the second inverted output end of the encoder and is used for outputting the 2 nd bit inverted encoded output signal, the output end of the ninth NOR gate is the first output end of the encoder and is used for outputting the 1 st bit encoded output signal, and the inverted output end of the ninth NOR gate is the first inverted output end of the encoder and is used for outputting the 1 st bit inverted encoded output signal.

2. The TDPL logic-based encoder according to claim 1, wherein each of the nor gates comprises a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a first NMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a thirteenth NMOS transistor, a fourteenth NMOS transistor, a fifteenth NMOS transistor, a sixteenth NMOS transistor, a seventeenth NMOS transistor, an eighteenth NMOS transistor, a nineteenth NMOS transistor, a twentieth NMOS transistor, and a twenty-first NMOS transistor, respectively; the source electrode of the first PMOS tube is connected with a power supply, the grid electrode of the first PMOS tube, the grid electrode of the first NMOS tube and the grid electrode of the fourth NMOS tube are connected, and the connecting end of the grid electrode of the first PMOS tube and the grid electrode of the first NMOS tube is the discharge control end of the NOR gate; the drain electrode of the first PMOS transistor, the source electrode of the second PMOS transistor, the source electrode of the third PMOS transistor, the source electrode of the fourth PMOS transistor, and the source electrode of the fifth PMOS transistor are connected, the gate electrode of the second PMOS transistor is connected with the gate electrode of the fifth PMOS transistor, and the connection end thereof is the precharge control end of the nor gate, the drain electrode of the second PMOS transistor, the drain electrode of the third PMOS transistor, the drain electrode of the first NMOS transistor, the drain electrode of the second NMOS transistor, the gate electrode of the fourth PMOS transistor is connected with the gate electrode of the third NMOS transistor, and the connection end thereof is the output end of the nor gate, the gate electrode of the third PMOS transistor, the gate electrode of the second NMOS transistor, the drain electrode of the fourth PMOS transistor, the drain electrode of the third NMOS transistor, the drain electrode of the fifth PMOS transistor is connected with the drain electrode of the fourth NMOS transistor, and the connection end thereof is the inverted output end of the nor gate; the source of the first NMOS transistor is grounded, the drain of the second NMOS transistor, the drain of the fifth NMOS transistor, the drain of the sixth NMOS transistor, the drain of the seventh NMOS transistor and the drain of the eighth NMOS transistor are connected, the source of the third NMOS transistor, the drain of the ninth NMOS transistor, the drain of the tenth NMOS transistor, the drain of the eleventh NMOS transistor and the drain of the twelfth NMOS transistor are connected, the source of the fourth NMOS transistor is grounded, the gate of the fifth NMOS transistor, the gate of the seventh NMOS transistor, the gate of the tenth NMOS transistor and the gate of the twelfth NMOS transistor are connected, and the connection end thereof is the first input end of the nor gate, the source of the fifth NMOS transistor and the drain of the thirteenth NMOS transistor are connected, the gate of the sixth NMOS transistor, the gate of the eighth NMOS transistor, the gate of the ninth NMOS transistor and the gate of the eleventh NMOS transistor are connected, and the connection end thereof is the inverted input end of the nor gate, a source electrode of the sixth NMOS transistor is connected to a drain electrode of the fourteenth NMOS transistor, a source electrode of the seventh NMOS transistor is connected to a drain electrode of the fifteenth NMOS transistor, a source electrode of the eighth NMOS transistor is connected to a drain electrode of the sixteenth NMOS transistor, a source electrode of the ninth NMOS transistor is connected to a drain electrode of the seventeenth NMOS transistor, a source electrode of the tenth NMOS transistor is connected to a drain electrode of the eighteenth NMOS transistor, a source electrode of the eleventh NMOS transistor is connected to a drain electrode of the nineteenth NMOS transistor, a source electrode of the twelfth NMOS transistor is connected to a drain electrode of the twentieth NMOS transistor, a gate electrode of the thirteenth NMOS transistor, a gate electrode of the fourteenth NMOS transistor, a gate electrode of the tenth NMOS transistor and a gate electrode of the nineteenth NMOS transistor are connected, and a gate connecting end of the ninth NMOS transistor is a second input end of the nor gate, a source of the thirteenth NMOS transistor, a source of the fourteenth NMOS transistor, a source of the fifteenth NMOS transistor, a source of the sixteenth NMOS transistor, a source of the seventeenth NMOS transistor, a source of the eighteenth NMOS transistor, a source of the nineteenth NMOS transistor, a source of the twentieth NMOS transistor and a drain of the twenty-first NMOS transistor are connected, a gate of the fifteenth NMOS transistor, a gate of the sixteenth NMOS transistor, a gate of the seventeenth NMOS transistor and a gate of the eighteenth NMOS transistor are connected, a connection end of the gate of the fifteenth NMOS transistor and the gate of the eighteenth NMOS transistor is a second inverting input end of the nor gate, a gate of the twenty-first NMOS transistor is an evaluation control end of the nor gate, and a source of the twenty-first NMOS transistor is grounded, the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, and the fifth PMOS transistor are common threshold voltage PMOS transistors, the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor, and the twenty-first NMOS transistor are common threshold voltage NMOS transistors, the fifth NMOS transistor, the sixth NMOS transistor, the seventh NMOS transistor, the ninth NMOS transistor, the thirteenth NMOS transistor, the fourteenth NMOS transistor, the fifteenth NMOS transistor, and the seventeenth NMOS transistor are low threshold voltage NMOS transistors, and the eighth NMOS transistor, the tenth NMOS transistor, the eleventh NMOS transistor, the twelfth NMOS transistor, the sixteenth NMOS transistor, the eighteenth NMOS transistor, the nineteenth NMOS transistor, and the twentieth NMOS transistor are high threshold voltage NMOS transistors.

3. A TDPL logic-based encoder according to claim 2, wherein the threshold voltage of said normal threshold voltage PMOS transistor is-0.404V, the threshold voltage of said normal threshold voltage NMOS transistor is 0.397V, the threshold voltage of said low threshold voltage NMOS transistor is 0.243V, and the threshold voltage of said high threshold voltage NMOS transistor is 0.489V.

4. A TDPL logic based encoder according to claim 1, wherein each of said buffers comprises a first inverter and a second inverter, respectively, an input of said first inverter being an input of said buffer, an output of said first inverter being connected to an input of said second inverter, and an output of said second inverter being an output of said buffer.

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