CN110610106B

CN110610106B - Three-input confusion operation circuit based on DCVS (data communication and voltage switching) logic

Info

Publication number: CN110610106B
Application number: CN201910719484.8A
Authority: CN
Inventors: 那谱丹; 张跃军; 孙嘉昕; 戴晟; 徐渊博
Original assignee: Ningbo University
Current assignee: Ningbo University
Priority date: 2019-08-05
Filing date: 2019-08-05
Publication date: 2022-11-22
Anticipated expiration: 2039-08-05
Also published as: CN110610106A

Abstract

The invention discloses a three-input confusion operation circuit based on DCVS (data communication versus voltage) logic, which comprises a first PMOS (P-channel metal oxide semiconductor) tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a first NMOS (N-channel metal oxide semiconductor) tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube and sixteen dynamic nodes, wherein each dynamic node is respectively provided with a real connection state representing a path and a virtual connection state representing a broken circuit, the real connection state of each dynamic node is realized by a real hole, and the virtual connection state of each dynamic node is realized by a virtual hole; the method has the advantages that different functions can be realized by configuring sixteen dynamic nodes, an attacker cannot crack the functions of the logic gate through reverse engineering under the condition that the sixteen dynamic nodes are unknown, power consumption analysis attack and reverse engineering attack can be defended at the same time, and the safety is high.

Description

Three-input confusion operation circuit based on DCVS (data communication and voltage switching) logic

Technical Field

The present invention relates to a three-input garbled operation circuit, and more particularly, to a three-input garbled operation circuit based on DCVS logic.

Background

DCVS (Differential cascade Voltage Switch) logic belongs to dual-rail logic, and implements both the required logic function and its inverse function. The existing DCVS logic-based multi-input operation circuit is composed of two cross-coupled PMOS tubes and two complementary pull-down networks, and has two complementary output ends, wherein the two cross-coupled PMOS tubes are used for driving the output ends of the multi-input operation circuit to high level, the two complementary pull-down networks are used for pulling down the output ends of the multi-input operation circuit to low level, when the level of the input end of the multi-input operation circuit is changed, the levels of the two output ends are correspondingly changed, and the levels of the two output ends are just opposite.

In a multi-input operation circuit based on DCVS (digital-to-analog converter) logic, two complementary pull-down networks simultaneously realize the required logic function and the opposite function. If one pull-down network is turned on, its responsive output will be pulled down to a low level and its complementary output will be set to a high level. Therefore, when the output end level of the multi-input operation circuit based on the DCVS logic changes, the power consumption of the multi-input operation circuit is almost unchanged, and an attacker cannot distinguish the change situation of the output end according to the power consumption situation, so that the multi-input operation circuit based on the DCVS logic has the function of resisting power consumption analysis attack.

The current main attack means includes power consumption analysis attack and reverse engineering attack. Although the existing multi-input operation circuit based on DCVS logic has the function of resisting power consumption analysis, two complementary pull-down networks in the multi-input operation circuit belong to complementary structures, and connecting lines in the multi-input operation circuit are different, which can be obviously reflected in a layout. When an attacker carries out reverse engineering attack, a circuit netlist can be obtained directly through contact hole placement and metal wiring in a layout, and then the IP core is stolen successfully. Therefore, the conventional DCVS logic-based multi-input operation circuit does not have the function of resisting reverse engineering, and the safety is not high.

Disclosure of Invention

The invention aims to solve the technical problem of providing a DCVS (direct current-to-average converter switching) logic-based three-input confusion operation circuit which can defend against power consumption analysis attacks and reverse engineering attacks simultaneously and has high safety.

The technical scheme adopted by the invention for solving the technical problems is as follows: a three-input confusion operation circuit based on DCVS logic comprises a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube and sixteen dynamic nodes, wherein each dynamic node is respectively provided with a real connection state representing a path and a virtual connection state representing a broken circuit, the real connection state of the dynamic nodes is realized by real holes, and the virtual connection state of the dynamic nodes is realized by virtual holes; sixteen dynamic nodes are called a first dynamic node, a second dynamic node, a third dynamic node, a fourth dynamic node, a fifth dynamic node, a sixth dynamic node, a seventh dynamic node, an eighth dynamic node, a ninth dynamic node, a tenth dynamic node, an eleventh dynamic node, a twelfth dynamic node, a thirteenth dynamic node, a fourteenth dynamic node, a fifteenth dynamic node and a sixteenth dynamic node; the source electrode of the first PMOS tube, the source electrode of the second PMOS tube and the source electrode of the third PMOS tube; the source electrode of the fourth PMOS tube and the source electrode of the fifth PMOS tube are both connected with a power supply; a gate of the first PMOS transistor, a drain of the second PMOS transistor and a drain of the fourth NMOS transistor are connected and a connection end thereof is an output end of the three-input garbled operation circuit, an output end of the three-input garbled operation circuit is connected with the first dynamic node, a drain of the first PMOS transistor, a gate of the second PMOS transistor and a drain of the first NMOS transistor are connected and a connection end thereof is an inverted output end of the three-input garbled operation circuit, an inverted output end of the three-input garbled operation circuit is connected with the second dynamic node, a gate of the third PMOS transistor, a gate of the seventh NMOS transistor and a gate of the first NMOS transistor are connected and a connection end thereof is a first input end of the three-input garbled operation circuit, a drain of the third PMOS transistor, a drain of the seventh NMOS transistor and a gate of the fourth NMOS transistor are connected, a gate of the fourth PMOS transistor, a gate of the eighth NMOS transistor and a drain of the second NMOS transistor are connected and a gate of the third NMOS transistor and a drain of the fifth NMOS transistor are connected, a gate of the fifth NMOS transistor and a drain of the fifth NMOS transistor are connected respectively, the source of the second NMOS transistor is connected to the tenth dynamic node and the twelfth dynamic node, the drain of the third NMOS transistor is connected to the tenth dynamic node and the fourteenth dynamic node, the source of the third NMOS transistor is connected to ground, the source of the third NMOS transistor is connected to the sixteenth dynamic node, the source of the fourth NMOS transistor is connected to the third dynamic node and the fifth dynamic node, the drain of the fifth NMOS transistor is connected to the third dynamic node and the seventh dynamic node, the source of the fifth NMOS transistor is connected to the ninth dynamic node and the eleventh dynamic node, the drain of the sixth NMOS transistor is connected to the ninth dynamic node and the thirteenth dynamic node, the source of the sixth NMOS transistor is connected to ground, the source of the sixth NMOS transistor is connected to the fifteenth dynamic node, the source of the seventh NMOS transistor, the source of the eighth NMOS transistor and the thirteenth dynamic node, the sixth dynamic node and the twelfth dynamic node are connected to the sixth dynamic node, the sixth dynamic node and the twelfth dynamic node, the source of the sixth NMOS transistor is connected to the sixteenth dynamic node and the eleventh dynamic node, and the sixth dynamic node are connected to ground.

The first dynamic node, the fourth dynamic node, the fifth dynamic node, the seventh dynamic node, the tenth dynamic node, the eleventh dynamic node, the thirteenth dynamic node and the fifteenth dynamic node are all in a real connection state and are respectively realized by real holes, the second dynamic node, the third dynamic node, the sixth dynamic node, the eighth dynamic node, the ninth dynamic node, the twelfth dynamic node, the fourteenth dynamic node and the sixteenth dynamic node are all in a virtual connection state and are respectively realized by virtual holes, the output end of the three-input obfuscation operation circuit outputs a logical operation result, and the inverted output end of the three-input obfuscation operation circuit outputs a non-logical operation result.

The first dynamic node, the fourth dynamic node, the fifth dynamic node, the seventh dynamic node, the tenth dynamic node, the eleventh dynamic node, the thirteenth dynamic node and the fifteenth dynamic node are all in a virtual connection state and are respectively realized by adopting a virtual hole, the second dynamic node, the third dynamic node, the sixth dynamic node, the eighth dynamic node, the ninth dynamic node, the twelfth dynamic node, the fourteenth dynamic node and the sixteenth dynamic node are all in a real connection state and are respectively realized by adopting a real hole, the output end of the three-input obfuscation operation circuit outputs a logical operation result, and the inverted output end of the three-input obfuscation operation circuit outputs a non-logical operation result.

Compared with the prior art, the invention has the advantages that a DCVS logic circuit is formed by a first PMOS tube, a second PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube and a sixth NMOS tube, the first PMOS tube and the second PMOS tube are used for driving the output end of the three-input aliasing arithmetic circuit to a high level, the first NMOS tube, the second NMOS tube, the third NMOS tube, the fourth NMOS tube, the fifth NMOS tube and the sixth NMOS tube form two complementary pull-down networks in the DCVS logic circuit, the third PMOS tube and the seventh NMOS tube form a first phase inverter, the first phase inverter is used for carrying out negation operation on a first input signal A, the fourth PMOS tube and the eighth NMOS tube form a second phase inverter, the second phase inverter is used for carrying out negation operation on a second input signal B, the fifth PMOS tube and the ninth NMOS tube form a third inverter, the third inverter is used for carrying out negation operation on a third input signal C, and the first dynamic node, the second dynamic node, the third dynamic node, the fourth dynamic node, the fifth dynamic node, the sixth dynamic node, the seventh dynamic node, the eighth dynamic node, the ninth dynamic node, the tenth dynamic node, the eleventh dynamic node, the twelfth dynamic node, the thirteenth dynamic node, the fourteenth dynamic node, the fifteenth dynamic node and the sixteenth dynamic node are arranged in the DCVS logic circuit, the DCVS logic and the virtual hole arrangement are combined, and different logic functions can be realized through different arrangements of the sixteen dynamic nodes.

Drawings

FIG. 1 is a circuit diagram of a three-input aliasing circuit based on DCVS logic according to the present invention;

FIG. 2 is a simplified circuit diagram of a three-input garbled operation circuit based on DCVS logic according to the present invention for implementing AND/NAND function;

FIG. 3 is a simplified circuit diagram of a three-input garbled operation circuit based on DCVS logic according to the present invention for performing an OR/NOR function;

FIG. 4 is a simulation graph of a three-input garbled operation circuit based on DCVS logic according to the present invention during the implementation of OR operation;

FIG. 5 is a simulation graph of a three-input garbled operation circuit based on DCVS logic according to the present invention when performing NOR operation;

FIG. 6 is a simulation graph of the three-input garbled operation circuit based on DCVS logic according to the present invention during the implementation and operation.

FIG. 7 is a simulation graph of a three-input garbled operation circuit based on DCVS logic according to the present invention when NAND operation is performed.

Detailed Description

The invention is described in further detail below with reference to the accompanying examples.

The first embodiment is as follows: as shown in fig. 1, a DCVS logic-based three-input confusion operation circuit includes a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a fourth NMOS transistor N4, a fifth NMOS transistor N5, a sixth NMOS transistor N6, a seventh NMOS transistor N7, an eighth NMOS transistor N8, a ninth NMOS transistor N9, and sixteen dynamic nodes, where each dynamic node has a real connection state representing a path and a virtual connection state representing a broken circuit, the real connection state of the dynamic node is implemented by a real hole, and the virtual connection state of the dynamic node is implemented by a virtual hole; the sixteen dynamic nodes are referred to as a first dynamic node ha1, a second dynamic node ha2, a third dynamic node ha3, a fourth dynamic node ha4, a fifth dynamic node ha5, a sixth dynamic node ha6, a seventh dynamic node ha7, an eighth dynamic node ha8, a ninth dynamic node ha9, a tenth dynamic node ha10, an eleventh dynamic node ha11, a twelfth dynamic node ha12, a thirteenth dynamic node ha13, a fourteenth dynamic node ha14, a fifteenth dynamic node ha15, and a sixteenth dynamic node ha16; a source electrode of the first PMOS tube P1, a source electrode of the second PMOS tube P2 and a source electrode of the third PMOS tube P3; the source electrode of the fourth PMOS tube P4 and the source electrode of the fifth PMOS tube P5 are both connected to a power supply VDD; the grid of the first PMOS tube P1, the drain of the second PMOS tube P2 and the drain of the fourth NMOS tube N4 are connected and the connection end is the output end of the three-input aliasing arithmetic circuit, the output end of the three-input aliasing arithmetic circuit is connected with the first dynamic node ha1, the drain of the first PMOS tube P1, the grid of the second PMOS tube P2 and the drain of the first NMOS tube N1 are connected and the connection end is the inverse output end of the three-input aliasing arithmetic circuit, the inverse output end of the three-input aliasing arithmetic circuit is connected with the second dynamic node ha2, the grid of the third PMOS tube P3, the grid of the seventh NMOS tube N7 and the grid of the first NMOS tube N1 are connected and the connection end is the first input end of the three-input aliasing arithmetic circuit, the drain of the third PMOS tube P3, the drain of the seventh NMOS tube N7 and the grid of the fourth NMOS tube N4 are connected, the grid of the fourth PMOS tube P4, the grid of the eighth NMOS tube N8 and the grid of the second NMOS tube N2 are connected and the connection end is the second input end of the third aliasing arithmetic circuit, the drain electrode of a fourth PMOS tube P4, the drain electrode of an eighth NMOS tube N8 and the gate electrode of a fifth NMOS tube N5, the gate electrode of the fifth PMOS tube P5, the gate electrode of a ninth NMOS tube N9 and the gate electrode of a third NMOS tube N3 are connected, the connection end of the fifth PMOS tube P5 and the gate electrode of the ninth NMOS tube N9 is the third input end of the three-input aliasing arithmetic circuit, the drain electrode of the fifth PMOS tube P5, the drain electrode of the ninth NMOS tube N9 and the gate electrode of the sixth NMOS tube N6 are connected, the source electrode of the first NMOS tube N1 is respectively connected with a fourth dynamic node ha4 and a sixth dynamic node ha6, the drain electrode of the second NMOS tube N2 is respectively connected with a fourth dynamic node ha4 and an eighth dynamic node ha8, the source electrode of the second NMOS tube N2 is respectively connected with a tenth dynamic node ha10 and a twelfth dynamic node ha12, the drain electrode of the third NMOS tube N3 is respectively connected with a tenth dynamic node ha10 and a fourteenth dynamic node ha14, and the source electrode of the third NMOS tube N3 is grounded, a source of the third NMOS transistor N3 is connected to the sixteenth dynamic node ha16, a source of the fourth NMOS transistor N4 is connected to the third dynamic node ha3 and the fifth dynamic node ha5, a drain of the fifth NMOS transistor N5 is connected to the third dynamic node ha3 and the seventh dynamic node ha7, a source of the fifth NMOS transistor N5 is connected to the ninth dynamic node ha9 and the eleventh dynamic node ha11, a drain of the sixth NMOS transistor N6 is connected to the ninth dynamic node ha9 and the thirteenth dynamic node ha13, a source of the sixth NMOS transistor N6 is grounded, a source of the sixth NMOS transistor N6 is connected to the fifteenth dynamic node ha15, a source of the seventh NMOS transistor N7, a source of the eighth NMOS transistor N8, and a source of the ninth NMOS transistor N9 are grounded, the first dynamic node ha1 is connected to the seventh dynamic node ha7 and the thirteenth dynamic node ha13, the second dynamic node ha2 is connected to the eighth dynamic node ha8, the fourteenth dynamic node ha8, and the fourteenth dynamic node ha5 are connected to the fifteenth node ha16, and the fifteenth dynamic node ha11, and the fifteenth dynamic node ha6 are connected to the twelfth dynamic node 12, respectively.

As shown in fig. 2, in this embodiment, the first dynamic node ha1, the fourth dynamic node ha4, the fifth dynamic node ha5, the seventh dynamic node ha7, the tenth dynamic node ha10, the eleventh dynamic node ha11, the thirteenth dynamic node ha13, and the fifteenth dynamic node ha15 are all in a real connection state, and are implemented by using real holes, respectively, the second dynamic node ha2, the third dynamic node ha3, the sixth dynamic node ha6, the eighth dynamic node ha8, the ninth dynamic node ha9, the twelfth dynamic node ha12, the fourteenth dynamic node ha14, and the sixteenth dynamic node ha16 are all in a virtual connection state, and are implemented by using virtual holes, respectively, an output end of the three-input obfuscation operation circuit outputs a logical operation result, and an inverted output end of the three-input obfuscation operation circuit outputs a non-logical operation result.

The second embodiment: as shown in fig. 1, a DCVS logic-based three-input confusion operation circuit includes a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4, a fifth PMOS transistor P5, a first NMOS transistor N1, a second NMOS transistor N2, a third NMOS transistor N3, a fourth NMOS transistor N4, a fifth NMOS transistor N5, a sixth NMOS transistor N6, a seventh NMOS transistor N7, an eighth NMOS transistor N8, a ninth NMOS transistor N9, and sixteen dynamic nodes, where each dynamic node has a real connection state representing a path and a virtual connection state representing an open circuit, the real connection state of the dynamic node is implemented by a real hole, and the virtual connection state of the dynamic node is implemented by a virtual hole; the sixteen dynamic nodes are referred to as a first dynamic node ha1, a second dynamic node ha2, a third dynamic node ha3, a fourth dynamic node ha4, a fifth dynamic node ha5, a sixth dynamic node ha6, a seventh dynamic node ha7, an eighth dynamic node ha8, a ninth dynamic node ha9, a tenth dynamic node ha10, an eleventh dynamic node ha11, a twelfth dynamic node ha12, a thirteenth dynamic node ha13, a fourteenth dynamic node ha14, a fifteenth dynamic node ha15, and a sixteenth dynamic node ha16; a source electrode of a first PMOS tube P1, a source electrode of a second PMOS tube P2 and a source electrode of a third PMOS tube P3; the source electrode of the fourth PMOS pipe P4 and the source electrode of the fifth PMOS pipe P5 are both connected to a power supply VDD; the grid of the first PMOS transistor P1, the drain of the second PMOS transistor P2 and the drain of the fourth NMOS transistor N4 are connected and their connection ends are the output ends of the three-input garbled circuit, the output end of the three-input garbled circuit is connected with the first dynamic node ha1, the drain of the first PMOS transistor P1, the grid of the second PMOS transistor P2 and the drain of the first NMOS transistor N1 are connected and their connection ends are the inverting output ends of the three-input garbled circuit, the inverting output end of the three-input garbled circuit is connected with the second dynamic node ha2, the grid of the third PMOS transistor P3, the grid of the seventh NMOS transistor N7 and the grid of the first NMOS transistor N1 are connected and their connection ends are the first input end of the three-input garbled circuit, the drain of the third PMOS transistor P3, the drain of the seventh NMOS transistor N7 and the grid of the fourth NMOS transistor N4 are connected, the grid of the eighth NMOS transistor N8 and the grid of the second NMOS transistor N2 and their connection ends are the second input end of the third garbled circuit, the drain electrode of a fourth PMOS transistor P4, the drain electrode of an eighth NMOS transistor N8 and the gate electrode of a fifth NMOS transistor N5 are connected, the gate electrode of the fifth PMOS transistor P5, the gate electrode of a ninth NMOS transistor N9 and the gate electrode of a third NMOS transistor N3 are connected, and the connection end is the third input end of the three-input aliasing arithmetic circuit, the drain electrode of the fifth PMOS transistor P5, the drain electrode of the ninth NMOS transistor N9 and the gate electrode of the sixth NMOS transistor N6 are connected, the source electrode of the first NMOS transistor N1 is respectively connected with a fourth dynamic node ha4 and a sixth dynamic node ha6, the drain electrode of the second NMOS transistor N2 is respectively connected with a fourth dynamic node ha4 and an eighth dynamic node ha8, the source electrode of the second NMOS transistor N2 is respectively connected with a tenth dynamic node ha10 and a twelfth dynamic node ha12, the drain electrode of the third NMOS transistor N3 is respectively connected with a tenth dynamic node ha10 and a fourteenth dynamic node ha14, and the source electrode of the third NMOS transistor N3 is grounded, the source of the third NMOS transistor N3 is connected to the sixteenth dynamic node ha16, the source of the fourth NMOS transistor N4 is connected to the third dynamic node ha3 and the fifth dynamic node ha5, the drain of the fifth NMOS transistor N5 is connected to the third dynamic node ha3 and the seventh dynamic node ha7, the source of the fifth NMOS transistor N5 is connected to the ninth dynamic node ha9 and the eleventh dynamic node ha11, the drain of the sixth NMOS transistor N6 is connected to the ninth dynamic node ha9 and the thirteenth dynamic node ha13, the source of the sixth NMOS transistor N6 is grounded, the source of the sixth NMOS transistor N6 is connected to the fifteenth dynamic node ha15, the source of the seventh NMOS transistor N7, the source of the eighth NMOS transistor N8 and the source of the ninth NMOS transistor N9 are grounded, the first dynamic node ha1 is connected to the seventh dynamic node ha7 and the thirteenth dynamic node ha13, the second dynamic node ha2 is connected to the eighth dynamic node ha8, the fourteenth dynamic node ha5 is connected to the fourteenth dynamic node ha12, and the fifteenth dynamic node ha6, and the twelfth dynamic node ha11 are connected to the twelfth dynamic node ha 6.

As shown in fig. 3, in this embodiment, the first dynamic node ha1, the fourth dynamic node ha4, the fifth dynamic node ha5, the seventh dynamic node ha7, the tenth dynamic node ha10, the eleventh dynamic node ha11, the thirteenth dynamic node ha13, and the fifteenth dynamic node ha15 are all in a virtual connection state, and are implemented by virtual holes, respectively, the second dynamic node ha2, the third dynamic node ha3, the sixth dynamic node ha6, the eighth dynamic node ha8, the ninth dynamic node ha9, the twelfth dynamic node ha12, the fourteenth dynamic node ha14, and the sixteenth dynamic node ha16 are all in a real connection state, and are implemented by real holes, respectively, an output end of the three-input obfuscation circuit outputs or a logic operation result, and an inverted output end of the three-input obfuscation circuit outputs or a non-logic operation result.

The three-input garbled operation circuit based on the DCVS of the invention is simulated, wherein the simulation curve of the three-input garbled operation circuit based on the DCVS of the invention in the implementation or operation is shown in FIG. 4, the simulation curve of the three-input garbled operation circuit based on the DCVS of the invention in the implementation nor operation is shown in FIG. 5, the simulation curve of the three-input garbled operation circuit based on the DCVS of the invention in the implementation and operation is shown in FIG. 6, and the simulation curve of the three-input garbled operation circuit based on the DCVS of the invention in the implementation nand operation is shown in FIG. 7. In fig. 4, from top to bottom, the signals are the first input signal A1, the second input signal A2, the third input signal A3 and the output result Z of the or operation of A1, A2 and A3, respectively, eight cases of the three input signals of the first input signal A1, the second input signal A2 and the third input signal A3 are traversed in the simulation graph, when one of the first input signal A1, the second input signal A2 and the third input signal A3 is at a high level, the output result Z is at a high level, otherwise, the output result Z is at a low level, and it can be known from analyzing fig. 4 that the present invention can implement a three-input or logic function, and has a correct three-input or logic function. In fig. 5, from top to bottom, the signals are the first input signal A1, the second input signal A2, the third input signal A3 and the output result ZN of the nor operation performed by A1, A2 and A3, respectively, the simulation graph traverses eight cases of the three input signals, i.e., the first input signal A1, the second input signal A2 and the third input signal A3, when one of the first input signal A1, the second input signal A2 and the third input signal A3 is at a high level, the output result ZN is at a low level, otherwise, the output result ZN is at a high level, and it can be known from fig. 5 that the present invention can implement a three-input nor function, and has a correct three-input nor function. In fig. 6, from top to bottom, the signals are the first input signal A1, the second input signal A2, the third input signal A3 and the output result Z of the and operation of A1, A2 and A3, respectively, eight cases of the three input signals of the first input signal A1, the second input signal A2 and the third input signal A3 are traversed in the simulation graph, when one of the first input signal A1, the second input signal A2 and the third input signal A3 is at a low level, the output result Z is at a low level, otherwise, the output result Z is at a high level, and it can be known from analyzing fig. 6 that the present invention can realize a three-input and logic function, and has a correct three-input and logic function. In fig. 7, from top to bottom, the signals are the first input signal A1, the second input signal A2, the third input signal A3 and the output result ZN of the nand operations performed by A1, A2 and A3, respectively, eight cases of the three input signals of the first input signal A1, the second input signal A2 and the third input signal A3 are traversed in the simulation graph, when one of the first input signal A1, the second input signal A2 and the third input signal A3 is at a low level, the output result ZN is at a high level, otherwise, the output result ZN is at a low level, and it can be known from fig. 7 that the present invention can implement a three-input nand logic function, and has a correct three-input nand logic function.

Claims

1. A three-input confusion operation circuit based on DCVS logic is characterized by comprising a first PMOS tube, a second PMOS tube, a third PMOS tube, a fourth PMOS tube, a fifth PMOS tube, a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, a fifth NMOS tube, a sixth NMOS tube, a seventh NMOS tube, an eighth NMOS tube, a ninth NMOS tube and sixteen dynamic nodes, wherein each dynamic node is respectively provided with a real connection state representing a path and a virtual connection state representing a broken path, the real connection state of each dynamic node is realized by a real hole, and the virtual connection state of each dynamic node is realized by a virtual hole; sixteen dynamic nodes are called a first dynamic node, a second dynamic node, a third dynamic node, a fourth dynamic node, a fifth dynamic node, a sixth dynamic node, a seventh dynamic node, an eighth dynamic node, a ninth dynamic node, a tenth dynamic node, an eleventh dynamic node, a twelfth dynamic node, a thirteenth dynamic node, a fourteenth dynamic node, a fifteenth dynamic node and a sixteenth dynamic node;

the source electrode of the first PMOS tube, the source electrode of the second PMOS tube, the source electrode of the third PMOS tube, the source electrode of the fourth PMOS tube and the source electrode of the fifth PMOS tube are all connected with a power supply; a gate of the first PMOS transistor, a drain of the second PMOS transistor and a drain of the fourth NMOS transistor are connected and a connection end thereof is an output end of the three-input garbled operation circuit, an output end of the three-input garbled operation circuit is connected with the first dynamic node, a drain of the first PMOS transistor, a gate of the second PMOS transistor and a drain of the first NMOS transistor are connected and a connection end thereof is an inverted output end of the three-input garbled operation circuit, an inverted output end of the three-input garbled operation circuit is connected with the second dynamic node, a gate of the third PMOS transistor, a gate of the seventh NMOS transistor and a gate of the first NMOS transistor are connected and a connection end thereof is a first input end of the three-input garbled operation circuit, a drain of the third PMOS transistor, a drain of the seventh NMOS transistor and a gate of the fourth NMOS transistor are connected, a gate of the fourth PMOS transistor, a gate of the eighth NMOS transistor and a drain of the second NMOS transistor are connected and a gate of the third NMOS transistor and a drain of the fifth NMOS transistor are connected, a gate of the fifth NMOS transistor and a drain of the fifth NMOS transistor are connected respectively, the source of the second NMOS transistor is connected to the tenth dynamic node and the twelfth dynamic node, the drain of the third NMOS transistor is connected to the tenth dynamic node and the fourteenth dynamic node, the source of the third NMOS transistor is connected to ground, the source of the third NMOS transistor is connected to the sixteenth dynamic node, the source of the fourth NMOS transistor is connected to the third dynamic node and the fifth dynamic node, the drain of the fifth NMOS transistor is connected to the third dynamic node and the seventh dynamic node, the source of the fifth NMOS transistor is connected to the ninth dynamic node and the eleventh dynamic node, the drain of the sixth NMOS transistor is connected to the ninth dynamic node and the thirteenth dynamic node, the source of the sixth NMOS transistor is connected to ground, the source of the sixth NMOS transistor is connected to the fifteenth dynamic node, the source of the seventh NMOS transistor, the source of the eighth NMOS transistor and the thirteenth dynamic node, the sixth dynamic node and the twelfth dynamic node are connected to the sixth dynamic node, the sixth dynamic node and the twelfth dynamic node, the source of the sixth NMOS transistor is connected to the sixteenth dynamic node and the eleventh dynamic node, and the sixth dynamic node are connected to ground.

2. The DCVS logic-based three-input garbled circuit as claimed in claim 1, wherein the first dynamic node, the fourth dynamic node, the fifth dynamic node, the seventh dynamic node, the tenth dynamic node, the eleventh dynamic node, the thirteenth dynamic node and the fifteenth dynamic node are all in a real connection state, and implemented by using real vias, respectively, the second dynamic node, the third dynamic node, the sixth dynamic node, the eighth dynamic node, the ninth dynamic node, the twelfth dynamic node, the fourteenth dynamic node and the sixteenth dynamic node are all in a virtual connection state, and implemented by using virtual vias, respectively, an output terminal of the three-input garbled circuit outputs a result of logic operation, and an inverted output terminal of the three-input garbled circuit outputs a result of non-logic operation.

3. The DCVS logic based three-input garbled circuit as claimed in claim 1, wherein the first dynamic node, the fourth dynamic node, the fifth dynamic node, the seventh dynamic node, the tenth dynamic node, the eleventh dynamic node, the thirteenth dynamic node and the fifteenth dynamic node are all in a virtual connection state, and implemented by using virtual vias, respectively, the second dynamic node, the third dynamic node, the sixth dynamic node, the eighth dynamic node, the ninth dynamic node, the twelfth dynamic node, the fourteenth dynamic node and the sixteenth dynamic node are all in a real connection state, and implemented by using real vias, respectively, the output terminal of the three-input garbled circuit outputs or logic operation results, and the inverted output terminal of the three-input garbled circuit outputs nor logic operation results.