CN110119640B - Dual-rail pre-charging logic unit and pre-charging method thereof - Google Patents
Dual-rail pre-charging logic unit and pre-charging method thereof Download PDFInfo
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Abstract
The invention discloses a double-track pre-charging logic unit and a pre-charging method thereof, wherein the double-track pre-charging logic unit respectively improves a single-track LBDL logic AND gate and a single-track LBDL logic NOT gate in the existing double-track pre-charging logic unit, the improved double-track pre-charging logic unit comprises 28 transistors including N1-N12, P1-P12 and I1-I2, compared with the existing double-track pre-charging logic unit, the double-track pre-charging logic unit adopts fewer transistors, occupies less layout area, and simultaneously ensures the DPA attack resistance of the logic unit.
Description
Technical Field
The present invention relates to the field of power consumption attack resistance of security chips, and more particularly, to a dual-rail precharge logic unit and a precharge method thereof.
Background
Today's social information exchange has become an indispensable part of daily life, and people are receiving more and more attention on information security while enjoying various conveniences brought by the development of IT technology. The way of realizing the cryptographic algorithm by using the cryptographic chip represented by an Application Specific Integrated Circuit (ASIC) has incomparable advantages of software implementation modes such as low cost, good closure, high cracking difficulty, high encryption speed and the like, and has become an important carrier of the cryptographic algorithm. Although the embeddability of the cryptographic device makes it impossible for an attacker to directly acquire the key information in the cryptographic chip, with the rapid development of the integrated circuit analysis technology, the attacker also develops a unique attack mode for the hardware encryption circuit.
Side-Channel Attack (SCA) aims to acquire information processed in an encryption device by detecting physical information (power consumption information, electromagnetic information) leaked by the encryption device at the time of operation. SCAs can be non-invasive, typically requiring little equipment so they are easy to implement. Differential Power Analysis (DPA) is the simplest and most efficient attack method in side channel attack, and greatly threatens the security of a cryptographic chip.
In order to cope with DPA attacks, power consumption defense measures are in force. The basic idea behind DPA attacks is to eliminate the correlation between the current and the internal data when the cryptographic chip is working. The conventional side channel protection method comprises blind leakage protection, leakage protection elimination, leakage protection weakening and the like; protection is usually implemented at the circuit level by designing a novel Logic unit, and the main design concept is dual-rail precharge Logic, and a unit implemented by using dual-rail precharge Logic mainly includes sensitive Amplifier Logic (SABL), traveling Wave Dynamic Differential Logic (WDDL), look-up table Based Differential Logic (LUT Based Differential Logic, LBDL), and the like.
The WDDL logic adopts an AND gate and an OR gate in a standard unit to construct a dual-rail pre-charge logic unit. This simplifies the design process. However, the technical scheme has obvious defects: due to the asymmetric structure of the AND gate and the OR gate, the power consumption of the unit still has certain difference when different data are operated by using the AND gate and the OR gate as two ends of the double-track output respectively.
LBDL uses a similar working principle as WDDL logic, with the same advantages as WDDL: firstly, double-track pre-charging logic is adopted, so that gradual charging can be realized, and overhigh peak current is avoided; and the other one adopts a semi-customized implementation method, and is suitable for the existing design process. In addition, LBDL has better NED (standard deviation of power consumption) index and higher DPA attack resistance compared with WDDL.
Although LBDL has the advantage of protection performance and has better effect of power consumption equalization, certain area is sacrificed accordingly. For a dual-rail logic AND-NAND gate, 12 transistors are needed for WDDL implementation, while for dual-rail LBDL logic with strictly balanced internal nodes, the number of the needed transistors is 40, the unit area is increased by three times, FIG. 1 is a single-rail LBDL logic AND gate circuit structure of the prior art, FIG. 2 is a single-rail LBDL logic NAND gate circuit structure of the prior art, AND the two-rail logic AND-NAND gate composed of FIG. 1 AND FIG. 2 comprises 12 NMOS transistors of N1-N12, 24 PMOS transistors of P1-P24 AND 2 inverters of I1-I2 (each inverted logic AND-NAND gate comprises 12 NMOS transistors of N1-N12, 24 PMOS transistors of P1-P24 AND 2 inverters of I38
A phase inverter has 2 transistors), of which the input signal is a,
B，
the output signals are Y,
The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person skilled in the art.
Disclosure of Invention
The invention aims to provide a dual-rail pre-charging logic unit and a pre-charging method thereof, which can use fewer transistors and occupy less layout area compared with the conventional dual-rail pre-charging logic unit based on LBDL.
To achieve the above object, the present invention provides a dual-rail precharge logic unit, comprising: a single-rail LBDL logic and gate and a single-rail LBDL logic nand gate.
The single-rail LBDL logic AND gate comprises: the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, the sixth NMOS transistor, the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor, the sixth PMOS transistor and the first inverter. The source electrode of the first NMOS transistor is connected with a power supply end; the source electrode of the second NMOS transistor is connected with a power supply end; the source electrode of the third NMOS transistor is connected with a power supply end, and the source electrode of the fourth NMOS transistor is connected with a ground end; the source electrode of the fifth NMOS transistor, the drain electrode of the first NOMS transistor, the drain electrode of the second NMOS transistor and the drain electrode of the first PMOS transistor are connected in common; the source electrode of the sixth NMOS transistor, the drain electrode of the third NMOS transistor, the drain electrode of the fourth NMOS transistor and the drain electrode of the second PMOS transistor are connected in common; the drain electrode of the fourth PMOS transistor is connected with the source electrode of the third PMOS transistor, and the source electrode of the fourth PMOS transistor is connected with a power supply end; the drain electrode of the sixth PMOS transistor is connected with the source electrode of the fifth PMOS transistor, and the source electrode of the sixth PMOS transistor is connected with a power supply end; an input end of the first inverter, a source electrode of the first PMOS transistor, a source electrode of the second PMOS transistor, a drain electrode of the third PMOS transistor, a drain electrode of the fifth NMOS transistor, and a drain electrode of the sixth NMOS transistor are commonly connected.
The single-rail LBDL logic nand gate comprises: a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, an eleventh NMOS transistor, a twelfth NMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, an eleventh PMOS transistor, a twelfth PMOS transistor, and a second inverter. The source terminal of the seventh NMOS transistor; the source terminal of the eighth NMOS transistor; the source electrode of the ninth NMOS transistor is grounded, and the source electrode of the tenth NMOS transistor is grounded; a source of the eleventh NMOS transistor, a drain of the seventh NOMS transistor, a drain of the eighth NMOS transistor, and a drain of the seventh PMOS transistor are commonly connected; a source of the twelfth NMOS transistor, a drain of the ninth NMOS transistor, a drain of the tenth NMOS transistor, and a drain of the eighth PMOS transistor are commonly connected; the drain electrode of the tenth PMOS transistor is connected with the source electrode of the ninth PMOS transistor, and the source electrode of the tenth PMOS transistor is connected with a power supply end; the drain electrode of the twelfth PMOS transistor is connected with the source electrode of the eleventh PMOS transistor, and the source electrode of the twelfth PMOS transistor is connected with a power supply end; an input end of the second inverter, a source of the seventh PMOS transistor, a source of the eighth PMOS transistor, a drain of the ninth PMOS transistor, a drain of the eleventh NMOS transistor, and a drain of the twelfth NMOS transistor are commonly connected.
The grid electrode of the first PMOS transistor, the grid electrode of the sixth NMOS transistor, the grid electrode of the seventh PMOS transistor and the grid electrode of the twelfth NMOS transistor are all connected with a first input signal; the grid electrode of the fifth NMOS transistor, the grid electrode of the second PMOS transistor, the grid electrode of the eleventh MMOS transistor and the grid electrode of the eighth PMOS transistor are all connected with a second input signal; the gate of the second NMOS transistor, the gate of the fourth NMOS transistor, the gate of the third PMOS transistor, the gate of the sixth PMOS transistor, the gate of the eighth NMOS transistor, the gate of the tenth NMOS transistor, the gate of the ninth PMOS transistor, and the gate of the twelfth PMOS transistor are all connected to a third input signal; the gate of the first NMOS transistor, the gate of the third NMOS transistor, the gate of the fourth PMOS transistor, the gate of the fifth PMOS transistor, the gate of the seventh NMOS transistor, the gate of the ninth NMOS transistor, the gate of the tenth PMOS transistor and the gate of the eleventh PMOS transistor are all connected with a fourth input signal; the first inverter outputs a first output signal and the second inverter outputs a second output signal.
In a preferred embodiment, the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, the sixth NMOS transistor, the seventh NMOS transistor, the eighth NMOS transistor, the ninth NMOS transistor, the tenth NMOS transistor, the eleventh NMOS transistor, and the twelfth NMOS transistor all have the same size; the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor, the sixth PMOS transistor, the seventh PMOS transistor, the eighth PMOS transistor, the ninth PMOS transistor, the tenth PMOS transistor, the eleventh PMOS transistor, and the twelfth PMOS transistor all have the same size.
The invention also provides a pre-charging method of the dual-rail pre-charging logic unit, which comprises the following steps: in a pre-charge phase of the dual-rail pre-charge logic unit, the first input signal, the second input signal, the third input signal, and the fourth input signal are all set to 0, such that the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor, the sixth PMOS transistor, the seventh PMOS transistor, the eighth PMOS transistor, the ninth PMOS transistor, the tenth PMOS transistor, the eleventh PMOS transistor, and the twelfth PMOS transistor are all turned on, and the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, the sixth NMOS transistor, the seventh NMOS transistor, the eighth NMOS transistor, the ninth NMOS transistor, The tenth NMOS transistor, the eleventh NMOS transistor, and the twelfth NMOS transistor are all turned off, and the first output signal and the second output signal both output 0.
In a preferred embodiment, during an evaluation phase of the dual-rail precharge logic unit, the first input signal and the second input signal are complementary, the third input signal and the fourth input signal are complementary, one of the third PMOS transistor and the fourth PMOS transistor is turned off, one of the fifth PMOS transistor and the sixth PMOS transistor is turned off, one of the ninth PMOS transistor and the tenth PMOS transistor is turned off, and one of the eleventh PMOS transistor and the twelfth PMOS transistor is turned off.
Compared with the prior art, the double-rail pre-charging logic unit respectively improves the single-rail LBDL logic AND gate and the single-rail LBDL logic NOT gate in the existing double-rail pre-charging logic unit, so that the double-rail pre-charging logic unit of the invention adopts fewer transistors, occupies less layout area, and simultaneously ensures the DPA attack resistance of the logic unit.
Drawings
FIG. 1 is a single rail LBDL logic AND gate according to the prior art;
FIG. 2 is a single rail LBDL logic NAND gate according to the prior art;
FIG. 3 is a single-rail LBDL logical AND gate according to an embodiment of the present invention;
fig. 4 is a single-rail LBDL logic nand gate in accordance with an embodiment of the present invention.
Detailed Description
The following detailed description of the present invention is provided in conjunction with the accompanying drawings, but it should be understood that the scope of the present invention is not limited to the specific embodiments.
Throughout the specification and claims, unless explicitly stated otherwise, the word "comprise", or variations such as "comprises" or "comprising", will be understood to imply the inclusion of a stated element or component but not the exclusion of any other element or component.
The invention provides a double-rail pre-charging logic unit and a pre-charging method thereof, aiming at solving the problems that the existing double-rail pre-charging logic unit based on LBDL is large in transistor quantity and large in occupied layout area.
The cell structure and the operation principle of the dual-rail precharge logic unit according to an embodiment of the present invention are described below with reference to fig. 3 and 4. Fig. 1 is a single rail LBDL logic and gate according to the prior art. Fig. 3 is a single rail LBDL logic and gate modified in accordance with the present embodiment. Fig. 2 is a single rail LBDL logic nand gate according to the prior art. Fig. 4 is a modified single-rail LBDL logic nand gate of this embodiment. Fig. 1 and 2 constitute a dual-rail precharge logic unit in the prior art, fig. 3 and 4 constitute a dual-rail precharge logic unit in this embodiment, and the basic structure of both dual-rail precharge logic units includes an LUT (Look UP Table) structure composed of NMOS transistors, and a precharge transistor composed of PMOS transistors is added on the basis of the LUT structure. The single-rail LBDL logic AND gate circuit and the single-rail LBDL logic NAND gate circuit have high symmetry, and meanwhile, internal nodes of the circuit guarantee that corresponding nodes have the same parasitic capacitance through reasonable configuration, and the constancy of power consumption is guaranteed.
As shown in fig. 3, this exampleThe single-rail LBDL logic and gate of an embodiment is composed of a PMOS transistor P1, a PMOS transistor P2, a PMOS transistor P3, a PMOS transistor P4, a PMOS transistor P5, a PMOS transistor P6, and an NMOS transistor N1, an NMOS transistor N2, an NMOS transistor N3, an NMOS transistor N4, an NMOS transistor N5, an NMOS transistor N6, and an inverter I1, a,
B，
is the input signal of the unit, Y is the output signal of the unit, and Y is the output result of the AND of the input signals A and B.
In FIG. 3, the NMOS transistor N1 has a source connected to a power supply terminal (VDD) and a gate connected to an input signal
The drain electrode of the NMOS transistor N2, the source electrode of the NMOS transistor N5 and the drain electrode of the PMOS transistor P1 are connected in common; the source electrode of the NMOS transistor N2 is connected with a power supply end, and the grid electrode of the NMOS transistor N2 is connected with an input signal B; the source of the NMOS transistor N3 is connected with a power supply terminal, and the gate is connected with an input signal
The drain electrode of the NMOS transistor N4, the source electrode of the NMOS transistor N6 and the drain electrode of the PMOS transistor P2 are connected in common; the source of the NMOS transistor N4 is Grounded (GND), and the gate is connected with an input signal B; NMOS transistor N5 having its gate connected to an input signal
The drain electrode of the PMOS transistor is commonly connected with the drain electrode of the NMOS transistor N6, the source electrode of the PMOS transistor P1, the source electrode of the PMOS transistor P2, the drain electrode of the PMOS transistor P3, the drain electrode of the PMOS transistor P5 and the input end of the inverter I1; the gate of the NMOS transistor N6 is connected with the input signal A; the grid electrode of the PMOS transistor P1 is connected with the input signal A; PMOS transistor P2 with gate connected to input signal
The grid electrode of the PMOS transistor P3 is connected with the input signal B, and the source electrode of the PMOS transistor P4 is connected with the drain electrode of the PMOS transistor P4; PM (particulate matter)The gate of the OS transistor P4 is connected to the input signal
The source electrode is connected with a power supply end; PMOS transistor P5 with gate connected to input signal
The source is connected with the drain of the PMOS transistor P6; the PMOS transistor P6 has a gate connected to the input signal B and a source connected to the power supply terminal.
The input signal has different characteristics during the precharge phase and the evaluation phase of the cell, and during the precharge phase, a,
B，
all are 0. In the evaluation phase, A and
complementary inputs (one is 0 and the other is 1), B and
and (4) complementation. That is to say only in the evaluation phase A and
b and
the opposite is true. In the evaluation phase, the input signals are complementary inputs. At the moment, the on-off of different MOS tubes is controlled according to different inputs, so that different logic values are transmitted to an output end, and the evaluation effect is achieved. For example when the input signal a is input,
B，
0, 1, 1, 0, MOS transistor N2,n5, P1 is conducted, the potential of the source electrode of N2 is transmitted to the input end of the inverter, and the output is 0 due to the action of the inverter; meanwhile, although the NMOS transistor N4 is also turned on, the potential of the source of the N4 cannot be transmitted to the output end because the PMOS transistors P2 and N6 are both turned off; p4 and P5 are also conductive, but since P3 and P6 are not conductive, the potential of the sources of P4 and P6 cannot be transmitted to the output terminal. There is only one path to the output during the evaluation phase, thus enabling the evaluation of the circuit. The outputs for other input cases are as follows:
as shown in the table above, the unit realizes the output result of AND between A and B.
As shown in fig. 4, the single-rail LBDL logic nand gate of this embodiment is composed of a PMOS transistor P7, a PMOS transistor P8, a PMOS transistor P9, a PMOS transistor P10, a PMOS transistor P11, a PMOS transistor P12 and an NMOS transistor N7, an NMOS transistor N8, an NMOS transistor N9, an NMOS transistor N10, an NMOS transistor N11, an NMOS transistor N12, and an inverter I2, a,
B，
is the input signal of the cell and is,
is the output signal of the cell, which is the output result of the nand operation on the input signals a and B.
The source of the NMOS transistor N7 is grounded, and the gate is connected with an input signal
The drain electrode of the NMOS transistor N8, the source electrode of the NMOS transistor N13 and the drain electrode of the PMOS transistor P7 are connected in common; the source of the NMOS transistor N8 is grounded, and the gate is connected with an input signal B; NMOS transistor N9 with grounded source and input signal connected to gate
The drain electrode of the NMOS transistor N10, the source electrode of the NMOS transistor N12 and the drain electrode of the PMOS transistor P8 are connected in common; the source electrode of the NMOS transistor N10 is connected with a power supply end, and the grid electrode of the NMOS transistor N10 is connected with an input signal B; NMOS transistor N11 having its gate connected to an input signal
The drain electrode of the PMOS transistor is commonly connected with the drain electrode of the NMOS transistor N12, the source electrode of the PMOS transistor P7, the source electrode of the PMOS transistor P8, the drain electrode of the PMOS transistor P9, the drain electrode of the PMOS transistor P11 and the input end of the inverter I2; the gate of the NMOS transistor N12 is connected with the input signal A; the grid electrode of the PMOS transistor P7 is connected with the input signal A; PMOS transistor P8 with gate connected to input signal
The grid electrode of the PMOS transistor P9 is connected with the input signal B, and the source electrode of the PMOS transistor P10 is connected with the drain electrode of the PMOS transistor P10; PMOS transistor P10 with gate connected to input signal
The source electrode is connected with a power supply end; PMOS transistor P11 with gate connected to input signal
The source is connected with the drain of the PMOS transistor P12; the PMOS transistor P6 has a gate connected to the input signal B and a source connected to the power supply terminal.
The single-rail LBDL logic and gate shown in fig. 3 and the single-rail LBDL logic nand gate shown in fig. 4 constitute the dual-rail precharge logic unit of the present embodiment. The double-rail pre-charging logic unit comprises 28 transistors including N1-N12, P1-P12 and I1-I2, wherein each inverter is provided with 2 transistors, and compared with the existing double-rail pre-charging logic unit, the number of the transistors is reduced, and the layout area occupied by the double-rail pre-charging logic unit is saved.
The working mode of the double-rail precharging logic unit is divided into two working phases of precharging and evaluating. The operation of the unit in the two stages is specifically analyzed below.
During the precharge phase, all differential input signals a,
B，
all of them are 0, because PMOS transistor is turned on when gate is low, NMOS transistor is turned off when gate is low, so PMOS transistors P1, P2, P3, P4, P5, P6, P7, P8, P9, P10, P11, P12 are all turned on, NMOS transistors N1, N2, N3, N4, N5, N6, N7, N8, N9, N10, N11, N12 are all turned off, so that all internal nodes N1, N2, N3, N4, N5, N1, N2, N3, N4, N5 are all charged to "1", and two output signals Y are obtained by the action of inverter I1, I2,
all are '0' and are provided to the next stage circuit as the pre-charging signal, thereby achieving the effect of pre-charging the traveling wave.
In the evaluation phase, the signals A and A are input
Complementary (i.e. when a is 1,
when A is 0, the ratio of A to A is 0,
1), input signals B and
in a complementary manner, one of the PMOS transistor P3 and the PMOS transistor P4 is turned off, and one of the PMOS transistor P5 and the PMOS transistor P6 is turned off, so that the node n1 is disconnected from the power supply end; one of the PMOS transistor P9 and the PMOS transistor P10 is turned off, and one of the PMOS transistor P11 and the PMOS transistor P12 is turned off, so that the node n × 1 is disconnected from the power source. Therefore, during the evaluation phase, the precharge circuit is turned off, the internal node is not charged, but according to the input signalThe number A is equal to the number A,
B，
and outputting the output value stored corresponding to the LUT structure.
In a preferred embodiment, in order to better balance power consumption and resist DPA attacks, all NMOS transistors and all PMOS transistors in the dual-rail precharge logic unit are the same size, so that the parasitic charges at the node n1 and the node n × 1 are equal; node n2 and node n x 2 have equal parasitic charges; node n3 and node n x 3 have equal parasitic charges; node n4, node n4, node n5 and node n5 have equal parasitic charges. During the precharge phase all internal nodes are charged to "1" and during the evaluation phase the internal nodes are discharged according to the input signal value. Analyzing the discharging condition of the node can obtain: regardless of the change in the input signal, one of the node n1 and the node n × 1 discharges to "0"; one of node n2 and node n x 2 discharges to "0"; one of the node n3 and the node n x 3 discharges to "0"; one of the nodes n4, n x 4, n5 and n x 5 is discharged to "0", so that at different input conditions, equal charge is always drained to ground, and during the precharge phase, the discharged nodes are recharged. No matter the switching process from the pre-charging stage to the evaluation stage or the switching process from the evaluation stage to the pre-charging stage, the same charge and discharge conditions can be realized under the condition of different inputs, so that the effect of balancing power consumption is achieved.
In the LBDL cell before improvement, in order to realize the charging effect on internal nodes and ensure the effect of balancing power consumption, 40 transistors are used, which not only increases the layout area but also improves the cell power consumption. To solve this problem, in the modified LBDL cell, a transmission gate composed of a PMOS transistor P1 and an NMOS transistor N5 is used instead of the NMOS transistor N5 in fig. 1; a transmission gate consisting of a PMOS transistor P2 and an NMOS transistor N6 is used to replace the NMOS transistor N6 in FIG. 1; a transmission gate consisting of a PMOS transistor P7 and an NMOS transistor N11 is used instead of the NMOS transistor N11 in FIG. 2; a transmission gate composed of a PMOS transistor P8 and an NMOS transistor N12 is used instead of the NMOS transistor N12 in fig. 2. After the above improvement, in the pre-charging stage, since all the input signals are "0", the PMOS transistors P1, P2, P7, and P8 are all turned on, the nodes n2, n3, n × 2, n × 3 can be charged through the four PMOS transistors, and no additional charging structure is needed. The transmission gate structure, in turn, transmits the output value stored by the LUT structure intact during the evaluation phase.
In summary, the dual-rail precharge logic unit of the embodiment optimizes the area of the conventional LBDL logic unit, and the improved dual-rail precharge logic unit includes N1-N12, P1-P12, I1-I2, and 28 transistors in total, and uses fewer transistors, occupies less layout area, and simultaneously ensures that the logic unit has the same DPA attack resistance.
The foregoing descriptions of specific exemplary embodiments of the present invention have been presented for purposes of illustration and description. It is not intended to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The exemplary embodiments were chosen and described in order to explain certain principles of the invention and its practical application to enable one skilled in the art to make and use various exemplary embodiments of the invention and various alternatives and modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims and their equivalents.
Claims (6)
1. A dual rail precharge logic cell, comprising: a single-rail LBDL logic and gate and a single-rail LBDL logic nand gate,
the single-rail LBDL logic AND gate comprises:
a first NMOS transistor having a source connected to a power supply terminal;
a second NMOS transistor having a source connected to a power supply terminal;
a third NMOS transistor having a source connected to a power supply terminal;
a fourth NMOS transistor having its source grounded;
a first PMOS transistor;
a fifth NMOS transistor, wherein a source electrode of the fifth NMOS transistor, a drain electrode of the first NMOS transistor, a drain electrode of the second NMOS transistor and a drain electrode of the first PMOS transistor are commonly connected;
a second PMOS transistor;
a sixth NMOS transistor, a source of the sixth NMOS transistor, a drain of the third NMOS transistor, a drain of the fourth NMOS transistor, and a drain of the second PMOS transistor being commonly connected;
a third PMOS transistor;
a fourth PMOS transistor, a drain of which is connected with a source electrode of the third PMOS transistor, and a source electrode of the fourth PMOS transistor is connected with a power supply end;
a fifth PMOS transistor;
a sixth PMOS transistor whose drain is connected to the source of the fifth PMOS transistor, and whose source is connected to a power supply terminal; and
a first inverter whose input terminal, source of the first PMOS transistor, source of the second PMOS transistor, drain of the third PMOS transistor, drain of the fifth NMOS transistor, and drain of the sixth NMOS transistor are commonly connected,
the single-rail LBDL logic nand gate comprises:
a seventh NMOS transistor having its source grounded;
an eighth NMOS transistor having a source grounded;
a ninth NMOS transistor having a source grounded;
a tenth NMOS transistor having a source connected to a power source terminal;
a seventh PMOS transistor;
an eleventh NMOS transistor, a source of the eleventh NMOS transistor, a drain of the seventh NMOS transistor, a drain of the eighth NMOS transistor, and a drain of the seventh PMOS transistor being commonly connected;
an eighth PMOS transistor;
a twelfth NMOS transistor, a source of the twelfth NMOS transistor, a drain of the ninth NMOS transistor, a drain of the tenth NMOS transistor, and a drain of the eighth PMOS transistor being commonly connected;
a ninth PMOS transistor;
a tenth PMOS transistor whose drain is connected to the source of the ninth PMOS transistor, and whose source is connected to a power supply terminal;
an eleventh PMOS transistor;
a twelfth PMOS transistor, a drain of which is connected to the source of the eleventh PMOS transistor, and a source of which is connected to a power supply terminal; and
a second inverter whose input terminal, source of the seventh PMOS transistor, source of the eighth PMOS transistor, drain of the ninth PMOS transistor, drain of the eleventh NMOS transistor, and drain of the twelfth NMOS transistor are commonly connected,
the grid electrode of the first PMOS transistor, the grid electrode of the sixth NMOS transistor, the grid electrode of the seventh PMOS transistor and the grid electrode of the twelfth NMOS transistor are all connected with a first input signal; the grid electrode of the fifth NMOS transistor, the grid electrode of the second PMOS transistor, the grid electrode of the eleventh NMOS transistor and the grid electrode of the eighth PMOS transistor are all connected with a second input signal; the gate of the second NMOS transistor, the gate of the fourth NMOS transistor, the gate of the third PMOS transistor, the gate of the sixth PMOS transistor, the gate of the eighth NMOS transistor, the gate of the tenth NMOS transistor, the gate of the ninth PMOS transistor, and the gate of the twelfth PMOS transistor are all connected to a third input signal; the gate of the first NMOS transistor, the gate of the third NMOS transistor, the gate of the fourth PMOS transistor, the gate of the fifth PMOS transistor, the gate of the seventh NMOS transistor, the gate of the ninth NMOS transistor, the gate of the tenth PMOS transistor and the gate of the eleventh PMOS transistor are all connected with a fourth input signal; the first inverter outputs a first output signal and the second inverter outputs a second output signal.
2. The dual-rail precharge logic cell of claim 1, wherein the first NMOS transistor, the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, the sixth NMOS transistor, the seventh NMOS transistor, the eighth NMOS transistor, the ninth NMOS transistor, the tenth NMOS transistor, the eleventh NMOS transistor, and the twelfth NMOS transistor are all the same size; the first PMOS transistor, the second PMOS transistor, the third PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor, the sixth PMOS transistor, the seventh PMOS transistor, the eighth PMOS transistor, the ninth PMOS transistor, the tenth PMOS transistor, the eleventh PMOS transistor, and the twelfth PMOS transistor all have the same size.
3. The dual rail precharge logic cell of claim 1, wherein the first input signal, the second input signal, the third input signal, and the fourth input signal are all 0 during a precharge phase.
4. The dual-rail precharge logic cell of claim 1, wherein, in an evaluation phase, the first input signal is complementary to the second input signal; the third input signal and the fourth input signal are complementary.
5. The dual-rail precharge logic unit of claim 1, wherein the first output signal is a result of an AND of the first input signal and the third input signal.
6. The dual-rail precharge logic unit of claim 1, wherein the second output signal is a result of a nand operation on the first input signal and the third input signal.
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