CN109656871A - A kind of four-way noise signal lossless compression device - Google Patents
A kind of four-way noise signal lossless compression device Download PDFInfo
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Abstract
The invention discloses a kind of four-way noise signal lossless compression devices, module and Flash memory module are realized including data acquisition module, fpga logic control module, data communication module, DSP algorithm, the analog signal of four road noise sonic transducer of data collecting module collected output, then fpga logic control module is inputted, the global logical sequence of fpga logic control module control, and the digital quantity after analog-to-digital conversion is passed to DSP algorithm and realizes module；DSP algorithm realizes that module operation compression algorithm compresses the digital quantity received, and Flash memory module stores compressed data, and real-time Transmission gives next stage data communication module.DSP algorithm realizes that module executes status signal inquiry, quantized data reading, data compression, read-write SDRAM and data output operation with polling mode, and DSP algorithm realizes that module uses ARC algorithm.The respective superiority of FPGA and DSP is utilized in the dual controller hardware structure of DSP+FPGA to the greatest extent, handles four tunnel telemetering noise signals in real time.
Description
Technical field
The present invention relates to lossless date-compress field, specially a kind of four-way noise signal lossless compression device is applicable in
Telemetry system is to the compression processing after data acquisition in aircraft.
Background technique
Telemetry system plays very important effect in the research process of aircraft, and main includes obtaining in flight test
The working status parameter of each system and the data of environmental parameter, so that it is determined that the quality of aircraft performance and progress dependent failure
Analysis.The performance of telemetry system and the development process of aircraft are closely bound up, aircraft performance improve also mainly according to
By the improved properties to telemetry system.
Telemetry parameter mainly includes analog quantity, digital quantity, switching value three classes parameter.That wherein arranges in telemetry system is a large amount of
Sensor can generate analog signal, this is the analog quantity parameter part in telemetry parameter.Analog quantity parameter is according to the difference of frequency
Slow varying parameter (0Hz~10Hz) and fast varying parameter (10Hz~8000Hz) can be divided into.Slow varying parameter include temperature, pressure,
The more slow signal of the variations such as hot-fluid；Fast varying parameter includes that the frequency bands such as impact, noise, vibration are wider, changes faster signal.
Telemetering noise data is exactly fast varying parameter.Fast parameter is according to having frequency variation fast, and amplitude changes feature greatly, so it was sampled
The sample frequency of journey must be sufficiently high, can reflect the integrity property of signal, can thus generate huge data volume.
During actual test, the wireless communication of telemetry system can only be passed through between all measured parameters and Land Based Test Site
Road is communicated.According to statistics, from the quantity of measured parameter, fast varying parameter only has the 10% of telemetry parameter, but from generation
Data are taken temperature, and fast varying parameter is up to 80%.But during practical flight, it is redundancy that the telemetry being transmitted back to, which has 95% or more,
's.Therefore under the premise of current telemetry mode is not changed, it is most economical effective that fast parameter evidence is handled using lossless compression
Dilatation channel scheme.Noisy data compression system is related to data acquisition and data compression two parts, to treatment process
Requirement of real-time is relatively high, and the real-time of traditional compressibility is no longer satisfied system requirements, it is therefore desirable to a kind of high reality
The lossless compression device of when property realizes the lossless compressions of data.
Summary of the invention
The present invention provides a kind of four-way noise to solve the problem of noise data lossless compression in telemetry system
Signal lossless compression set.
The present invention is achieved by the following technical solution: a kind of four-way noise signal lossless compression device, including
Data acquisition module, fpga logic control module, data communication module, DSP algorithm realize module and Flash memory module, institute
The analog signal of four road noise sonic transducer of data collecting module collected output is stated, fpga logic control module, FPGA are then inputted
The global logical sequence of Logic control module control, and the digital quantity after analog-to-digital conversion is passed to DSP algorithm and realizes module；DSP
Algorithm realizes that module operation compression algorithm compresses the digital quantity received, and Flash memory module stores compressed number
According to, and real-time Transmission gives next stage data communication module.The fpga logic control module includes AD acquisition module, quantization FIFO
Cache module, transfer FIFO cache module, serial ports receiving module, PCM data sending module and Flash storage control module,
The four road noise acoustical signals that AD acquisition module arrives system acquisition carry out analog-to-digital conversion, and corresponding sample rate is arranged, and will turn later
Data volume after changing is placed in quantization FIFO cache module, and then data enter DSP algorithm realization module, and the DSP algorithm is real
Existing module by the ACE2 space reflection of EMIFA on quantization FIFO cache module, after further through Mcbsp0 serial transmission to FPGA
Logic control module, serial ports receiving module simulative serial port receive timing and receive data, are put into transfer FIFO cache module, Flash
Storage control module controls the read-write of Flash, and PCM data sending module control chip sends the data to next stage and sets
It is standby.The DSP algorithm realizes that module acquires the digital quantity of four road noise sound, and executes status signal inquiry, quantization with polling mode
Data reading, data compression, read-write SDRAM and data output operation.
Four-way noise signal lossless compression device provided by the invention mainly includes data acquisition module, fpga logic
Control module, data communication module, DSP algorithm realize module and Flash memory module, data acquisition module are for acquiring four
The analog signal of road noise sonic transducer output, then it is input to fpga logic control module, fpga logic control module
Global logical sequence is controlled, and the digital quantity after analog-to-digital conversion is passed to DSP algorithm and realizes module；DSP algorithm realizes module
Operation compression algorithm compresses the digital quantity received, and Flash memory module stores compressed data, and real-time Transmission
Give next stage data communication module.Fpga logic control module includes AD acquisition module, quantization FIFO cache module, transfer FIFO
Cache module, serial ports receiving module, PCM data sending module and Flash storage control module, AD acquisition module adopt system
The four road noise acoustical signals collected carry out analog-to-digital conversion, and corresponding sample rate is arranged, later by the data volume amount of being placed on after conversion
Change in FIFO cache module, then data enter DSP algorithm realization module, and DSP algorithm realizes that module is the core of whole system
Part, which acquires the digital quantity of four road noise sound simultaneously, and executes status signal inquiry, quantized data reading with polling mode
Enter, data compression, read and write SDRAM and data output operation；DSP algorithm realizes that module is measuring the ACE2 space reflection of EMIFA
Change on FIFO cache module, after further through Mcbsp0 serial transmission give fpga logic control module, serial ports receiving module simulation string
Mouth receives timing and receives data, is put into transfer FIFO cache module, Flash storage control module controls the read-write of Flash
System, PCM data sending module control chip send the data to next stage equipment, which is realized by programming.
The four-way sampled data stream of AD acquisition module is as shown in Figure 3.
When DSP receives sampled data, if the data volume in DSP in 4 data receiver bufferings differs only by a sampled point, i.e.,
Each effective quantized data in channel differs a byte, and the data receiver buffering in 4 channels almost reaches in synchronization in DSP
2048 bytes, at this point, DSP needs while compressing 4 channel datas, task is heavy.But at other moment, DSP is substantially at
Idle state, such executive mode is not only unreasonable, will cause at DSP long-time moreover, four channel datas compress simultaneously
In busy state, have no time to carry out the input of sampled data and the output of compressed data, easily causes the quantization spilling of FIFO and defeated
The reading of FIFO is empty out.Compression procedure is interrupted according to interrupt mode, and reads in quantized data and output compressed data, then may
It causes data volume in DSP excessive, exceeds DSP ram in slice capacity.
DSP algorithm realizes that module uses ARC algorithm, and the compression information for decompression includes first of this compressed data
Data length, compression frame count, channel number and check code etc. after original sample, compression, specific algorithm is as follows: by four channels
Data buffering preset initial value, so that DSP algorithm is realized that module reads a quantized data and only carries out first compression, verification and defeated
Out, set the block length of data to be compressed as 2048B, the primary data amount of four-way data buffering be respectively 1536B,
1024B, 512B and 0, DSP algorithm realize that module reads 2048B data, i.e., each channel from quantization FIFO cache module every time
Data buffering value add 512, when reading quantized data for the first time, the data volume in channel 1 reaches 2048B, is compressed, is exported
Afterwards, the data buffering data volume in channel 1 is 0, and the data buffering amount in four channels is 0,1536B, 1024B and 512B at this time, the
When secondary reading quantized data, the data volume in channel 2 reaches 2048B, starts to compress the data in channel 2, four at this time
The data buffering amount in channel is 512B, 0,1536B and 1024B；When third time reads quantized data, the data volume in channel 3 reaches
2048B starts to compress the data in channel 3, and the data buffering amount in four channels is 1024B, 512B, 0 and at this time
1536B；When the 4th reading quantized data, the data volume in channel 4 reaches 2048B, starts to compress the data in channel 4,
The data buffering amount in four channels is 1024B, 512B, 0 and 1536B at this time, reads quantized data every time in this way and all guarantees only have
The data in one channel are compressed, and ensure that the continuous uniform flowing of data, and implementation process is as shown in Figure 4.This kind of algorithm is protected
Four channel datas to have been demonstrate,proved orderly to compress, each functional module of program is independent of each other, to enable compressed data correctly to be decompressed,
After data compression, data after compression are packaged framing (condensed frame) deposit SDRAM together with compression information；Noise data from
When scattered property is higher, lossless compression algorithm generates negative compression sometimes, this not only more expends space resources, also results in time wave
Take, therefore during executing compression algorithm, compares compressed data yield and original data volume, once the former is greater than or waits
In the latter, stops compression immediately, initial data is packaged and is stored in SDRAM.And during aircraft executes aerial mission,
Data compression unit is inevitably in more severe working environment (particle width penetrate with electromagnetic interference etc.), and at this moment, DSP internal program has
It may run and fly, for the reliability for increasing data compression unit, execute all export house dog prison after completing a data compression every time
Signal is controlled, the watchdog signal that FPGA detection DSP is sent resets immediately if any exception, guarantees that compression unit is promptly restored to work
Make state.DSP internal compression program flow diagram is as shown in Figure 5:
Specific steps are as follows:
1. DSP electrifying startup or reset load the program curing in Flash memory module and starting, complete the initialization of system
And the setting of parameters；
2. enter principal function main (), initialization CSL function library, MCBSP, GPIO interrupt register and EMIF interface, while just
Beginningization quantifies FIFO cache module, transfer FIFO cache module and read-write SDRAM；
3. when DSP detects that the quantization half-full signal of FIFO cache module, DSP are slow from the quantization FIFO of input by EMIF interface
The noise data after quantization is read in storing module, when sbuf mark to be handled, DSP starts ARC coding and starts data compression,
Sbuf data are compressed to dbuf, and ARC coding will return to compressed data length:
A. if compressed data length dbuf is smaller than the sbuf before compression, i.e. compression removal rate > 0, number after DSP will compress
According in dbuf write-in transfer FIFO cache module；
B. if compressed data length dbuf is bigger than the sbuf before compression, i.e., compression removal rate≤0, DSP will compress preceding number
According in sbuf write-in transfer FIFO cache module；
4. after eliminating mark to be processed, DSP constantly monitors the state and transfer FIFO caching mould of inherent quantization FIFO cache module
Data status in block:
When inherent quantization FIFO cache module data volume is greater than 4096B, while transfer FIFO cache module is not half-full, DSP from
Inherent quantization FIFO cache module takes out data starting MSBSP0 transmission；
5. the compressed data of DSP algorithm, or next stage is returned to after HDLC protocol encodes, it is real-time in the form of PCM code
Return to surface telemetry system；Another form is stored in compressed data in the included Flash memory module of system, in case of
It recycles.
Compared with prior art the invention has the following advantages: four-way noise signal provided by the present invention is lossless
Compression set, the device propose the dual controller hardware structure of DSP+FPGA a kind of, FPGA and DSP are utilized to the greatest extent
Respective superiority handles four tunnel telemetering noise signals in real time.It is wanted in addition, the structure of FPGA+DSP is able to satisfy modularized design
It asks, keeps system software design process of hardware flexible, the overall performance of system can be greatlyd improve.
Detailed description of the invention
Fig. 1 is system functional block diagram of the invention.
Fig. 2 is FPGA internal logic block diagram of the invention.
Fig. 3 is AD sampled data stream of the invention.
Fig. 4 is channel compressions data flow of the invention.
Fig. 5 is DSP program flow diagram of the invention.
Fig. 6 is the test macro schematic diagram of the embodiment of the present invention.
Fig. 7 is the compressed data source file figure of embodiment.
Fig. 8 is the channel plot that the host computer of embodiment is drawn.
It is marked in figure as follows:
1- testboard, 2- industrial personal computer, 3- display, 4- compression storage device, 5- data cable, 6-USB line, 7-VGA line,
8- power supply line, 9- power switch, 10- enabling signal.
Specific embodiment
Below in conjunction with specific embodiment, the invention will be further described.
A kind of four-way noise signal lossless compression device, as shown in Figure 1 and Figure 2: being patrolled including data acquisition module, FPGA
It collects control module, data communication module, DSP algorithm and realizes module and Flash memory module, the data collecting module collected four
The analog signal of road noise sonic transducer output, then inputs fpga logic control module, and the control of fpga logic control module is global
Logical sequence, and by after analog-to-digital conversion digital quantity be passed to DSP algorithm realize module；DSP algorithm realizes module operation compression
Algorithm compresses the digital quantity received, and Flash memory module stores compressed data, and real-time Transmission is to next stage
Data communication module.The fpga logic control module includes AD acquisition module, quantization FIFO cache module, transfer FIFO caching
Module, serial ports receiving module, PCM data sending module and Flash storage control module, AD acquisition module arrive system acquisition
Four road noise acoustical signals carry out analog-to-digital conversion, and corresponding sample rate is set, the data volume after conversion is placed on quantization later
In FIFO cache module, then data enter DSP algorithm realization module, and the DSP algorithm realizes that module is empty by the ACE2 of EMIFA
Between be mapped on quantization FIFO cache module, after further through Mcbsp0 serial transmission give fpga logic control module, serial ports receives
Module simulation serial ports receives timing and receives data, is put into transfer FIFO cache module, Flash storage control module is to Flash's
Read-write is controlled, and PCM data sending module control chip sends the data to next stage equipment.The DSP algorithm realizes mould
Block acquires the digital quantity of four road noise sound, and executes status signal inquiry, quantized data reading, data compression, reading with polling mode
Write SDRAM and data output operation.
In the present embodiment, DSP algorithm realizes that module uses ARC algorithm, and specific algorithm is as follows: the data in four channels are delayed
Rush default initial value, DSP algorithm made to realize that module reads a quantized data and only carries out first compression, verification and output, setting to
The block length of compressed data be 2048B, the primary data amount of four-way data buffering be respectively 1536B, 1024B, 512B and
0, DSP algorithm realizes that module reads 2048B data, i.e., the data buffering value in each channel from quantization FIFO cache module every time
Adding 512, when reading quantized data for the first time, the data volume in channel 1 reaches 2048B, after being compressed, being exported, the data in channel 1
Amount of buffered data is 0, and the data buffering amount in four channels is 0,1536B, 1024B and 512B, second of reading quantization number at this time
According to when, the data volume in channel 2 reaches 2048B, starts to compress the data in channel 2, at this time the data buffering in four channels
It measures as 512B, 0,1536B and 1024B；When third time reads quantized data, the data volume in channel 3 reaches 2048B, starts to logical
The data in road 3 are compressed, and the data buffering amount in four channels is 1024B, 512B, 0 and 1536B at this time；4th read volume
When changing data, the data volume in channel 4 reaches 2048B, starts to compress the data in channel 4, at this time the data in four channels
Buffering capacity is 1024B, 512B, 0 and 1536B, specific steps are as follows:
1. DSP electrifying startup or reset load the program curing in Flash memory module and starting, complete the initialization of system
And the setting of parameters；
2. enter principal function main (), initialization CSL function library, MCBSP, GPIO interrupt register and EMIF interface, while just
Beginningization quantifies FIFO cache module, transfer FIFO cache module and read-write SDRAM；
3. when DSP detects that the quantization half-full signal of FIFO cache module, DSP are slow from the quantization FIFO of input by EMIF interface
The noise data after quantization is read in storing module, when sbuf mark to be handled, DSP starts ARC coding and starts data compression,
Sbuf data are compressed to dbuf, and ARC coding will return to compressed data length:
A. if compressed data length dbuf is smaller than the sbuf before compression, i.e. compression removal rate > 0, number after DSP will compress
According in dbuf write-in transfer FIFO cache module；
B. if compressed data length dbuf is bigger than the sbuf before compression, i.e., compression removal rate≤0, DSP will compress preceding number
According in sbuf write-in transfer FIFO cache module；
4. after eliminating mark to be processed, DSP constantly monitors the state and transfer FIFO caching mould of inherent quantization FIFO cache module
Data status in block:
When inherent quantization FIFO cache module data volume is greater than 4096B, while transfer FIFO cache module is not half-full, DSP from
Inherent quantization FIFO cache module takes out data starting MSBSP0 transmission；
5. the compressed data of DSP algorithm, or next stage is returned to after HDLC protocol encodes, it is real-time in the form of PCM code
Return to surface telemetry system；Another form is stored in compressed data in the included Flash memory module of system, in case of
It recycles.
The present embodiment uses a set of testbed, which can simulate electric circumstance on arrow completely, is this implementation
Example provides authentic test simulation environment, four road noise acoustical signals and enabling signal including sensor output；Testboard passes through USB
Line is connected with industrial personal computer, industrial personal computer be equipped with the corresponding upper computer software of the device, be responsible for instruction transmission and data reception with
Analysis.The closed loop test system schematic diagram for compressing storage device is as shown in Figure 6.After test macro connection finishes, system electrification,
It carries out issuing signal source using upper computer software, read data and data analysis.In system testing, select triangular wave as
Wave data is downloaded in testboard and is generated four tunnel triangular waveforms by standard signal source, system, simulates noise signal on arrow.Figure
7 be the compressed data source file of passback back, and the frame head of compressed data is 14EB92.
It is mixed with the data file of four tunnel compressed datas, after decompression, is separated into the compressed file in each channel, on
Position machine will draw curve using the channel data received.After the data file for selecting first passage, obtained curve such as Fig. 8 institute
Show.The triangular wave signal source that the channel plot drawn out exactly is arranged at the beginning, amplitude, frequency and shape are not distorted, are seen
It is consistent to examine its excess-three paths effect.It can be seen that the verifying device lossless compression effect of the present embodiment is obvious, compression ratio is high, work done during compression
It can may be implemented.
The scope of protection of present invention is not limited to the above specific embodiment, and for those skilled in the art and
Speech, the present invention can there are many deformation and change, it is all within design and principle of the invention it is made it is any modification, improve and
Equivalent replacement should be all included within protection scope of the present invention.
Claims (2)
1. a kind of four-way noise signal lossless compression device, it is characterised in that: controlled including data acquisition module, fpga logic
Module, data communication module, DSP algorithm realize module and Flash memory module, the four road noise sound of data collecting module collected
Then the analog signal of sensor output inputs fpga logic control module, the global logic of fpga logic control module control
Timing, and the digital quantity after analog-to-digital conversion is passed to DSP algorithm and realizes module；DSP algorithm realizes that module runs compression algorithm pair
The digital quantity received is compressed, and Flash memory module stores compressed data, and real-time Transmission is logical to next stage data
Believe module；
The fpga logic control module includes AD acquisition module, quantization FIFO cache module, transfer FIFO cache module, serial ports
Receiving module, PCM data sending module and Flash storage control module, four road noises that AD acquisition module arrives system acquisition
Acoustical signal carries out analog-to-digital conversion, and corresponding sample rate is arranged, and the data volume after conversion is placed on quantization FIFO caching mould later
In block, then data enter DSP algorithm realization module, and the DSP algorithm realizes that module is measuring the ACE2 space reflection of EMIFA
Change on FIFO cache module, after further through Mcbsp0 serial transmission give fpga logic control module, serial ports receiving module simulation string
Mouth receives timing and receives data, is put into transfer FIFO cache module, Flash storage control module controls the read-write of Flash
System, PCM data sending module control chip send the data to next stage equipment；
The DSP algorithm realizes that module acquires the digital quantity of four road noise sound, and executes status signal inquiry, quantization with polling mode
Data reading, data compression, read-write SDRAM and data output operation.
2. a kind of four-way noise signal lossless compression device according to claim 1, it is characterised in that: the DSP is calculated
Method realizes that module uses ARC algorithm, and specific algorithm is as follows: the data buffering in four channels being preset initial value, realizes DSP algorithm
Module reads a quantized data and only carries out first compression, verification and output, set the block lengths of data to be compressed as
2048B, the primary data amount of four-way data buffering are respectively 1536B, 1024B, 512B and 0, and DSP algorithm realizes that module is each
2048B data are read from quantization FIFO cache module, i.e., the data buffering value in each channel adds 512, reads quantization for the first time
When data, the data volume in channel 1 reaches 2048B, and after being compressed, being exported, the data buffering data volume in channel 1 is 0, and at this time four
The data buffering amount in a channel is 0,1536B, 1024B and 512B, and when reading quantized data for the second time, the data volume in channel 2 reaches
To 2048B, start to compress the data in channel 2, at this time the data buffering amount in four channels be 512B, 0,1536B and
1024B；When third time reads quantized data, the data volume in channel 3 reaches 2048B, starts to compress the data in channel 3,
The data buffering amount in four channels is 1024B, 512B, 0 and 1536B at this time；When the 4th reading quantized data, the number in channel 4
Reach 2048B according to amount, start to compress the data in channel 4, at this time the data buffering amount in four channels be 1024B, 512B,
0 and 1536B, specific steps are as follows:
1. DSP electrifying startup or reset load the program curing in Flash memory module and starting, complete the initialization of system
And the setting of parameters；
2. enter principal function main (), initialization CSL function library, MCBSP, GPIO interrupt register and EMIF interface, while just
Beginningization quantifies FIFO cache module, transfer FIFO cache module and read-write SDRAM；
3. when DSP detects that the quantization half-full signal of FIFO cache module, DSP are slow from the quantization FIFO of input by EMIF interface
The noise data after quantization is read in storing module, when sbuf mark to be handled, DSP starts ARC coding and starts data compression,
Sbuf data are compressed to dbuf, and ARC coding will return to compressed data length:
A. if compressed data length dbuf is smaller than the sbuf before compression, i.e. compression removal rate > 0, number after DSP will compress
According in dbuf write-in transfer FIFO cache module；
B. if compressed data length dbuf is bigger than the sbuf before compression, i.e., compression removal rate≤0, DSP will compress preceding number
According in sbuf write-in transfer FIFO cache module；
4. after eliminating mark to be processed, DSP constantly monitors the state and transfer FIFO caching mould of inherent quantization FIFO cache module
Data status in block:
When inherent quantization FIFO cache module data volume is greater than 4096B, while transfer FIFO cache module is not half-full, DSP from
Inherent quantization FIFO cache module takes out data starting MSBSP0 transmission；
5. the compressed data of DSP algorithm, or next stage is returned to after HDLC protocol encodes, it is real-time in the form of PCM code
Return to surface telemetry system；Another form is stored in compressed data in the included Flash memory module of system, in case of
It recycles.
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| CN112419540A (en) * | 2020-10-30 | 2021-02-26 | 天津航空机电有限公司 | Big data storage system and method for realizing health management of airborne equipment |
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Application publication date: 20190419 |