WO2018113165A1 - Configurable device for monitoring vibration and swing states of hydraulic turbine set, and data acquisition method - Google Patents

Configurable device for monitoring vibration and swing states of hydraulic turbine set, and data acquisition method Download PDF

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WO2018113165A1
WO2018113165A1 PCT/CN2017/083533 CN2017083533W WO2018113165A1 WO 2018113165 A1 WO2018113165 A1 WO 2018113165A1 CN 2017083533 W CN2017083533 W CN 2017083533W WO 2018113165 A1 WO2018113165 A1 WO 2018113165A1
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module
sampling
data
fpga
channel
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PCT/CN2017/083533
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French (fr)
Chinese (zh)
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徐方明
夏洲
朱浩
杨烨
丁志宇
闫丽
程潇黠
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国网电力科学研究院
南京南瑞集团公司
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    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05BCONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00Programme-control systems
    • G05B19/02Programme-control systems electric
    • G05B19/04Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/042Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
    • G05B19/0423Input/output
    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05BCONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00Program-control systems
    • G05B2219/20Pc systems
    • G05B2219/21Pc I-O input output
    • G05B2219/21063Bus, I-O connected to a bus
    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05BCONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B2219/00Program-control systems
    • G05B2219/20Pc systems
    • G05B2219/21Pc I-O input output
    • G05B2219/21109Field programmable gate array, fpga as I-O module

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  • the invention belongs to the technical field of state monitoring of a water turbine unit, and particularly relates to a configurable vibration state monitoring device for a turbine unit, and to a high speed data acquisition method based on the device.
  • the turbine unit In the operation equipment of hydropower plants, the turbine unit is a very important and critical main equipment, which has a complicated structure and is composed of a plurality of complicated components such as a main shaft, a stator, a rotor, an upper frame, a lower frame and a top cover.
  • a main shaft As the turbine unit is constantly required to be driven by water and the working environment is relatively harsh, as a rotating machine, its most common and main fault is vibration failure.
  • the maintenance of the turbine unit was carried out by means of manual inspection during regular shutdown. As the turbine unit ageed, frequent shutdown inspections were required, resulting in increased operating costs of the hydropower plant and the inability to detect potential hazards or defects during operation. It is also impossible to accurately locate the location of a hidden danger or defect.
  • hydroelectric generating units such as mixed flow units, axial flow units, tubular units, impact units, etc.
  • the number of measuring points is different. Even for the same type of unit, each power plant The design of the number and location of measuring points is also different, especially for small and medium-sized turbines and large turbines.
  • General centralized hydro-generator set vibration swing data acquisition device the general number of points is relatively fixed, are designed according to the configuration requirements of large units, if you need to configure a central type of turbines with fewer points, in hardware and embedded
  • the software has to be modified greatly, and the adaptive ability is poor.
  • the high-speed acquisition module uses the software timing method to achieve the alignment of the sampling channel data.
  • the timing mode is adopted between each module, and only one internal channel of the acquisition module can realize synchronous simultaneous sampling, and data sampling moments still exist between the modules.
  • the time error of the sampling data of each measuring point depends on the timing mode and the timing accuracy inside the module.
  • the required sampling rate is 1KHz, 10KHz, or even higher.
  • the time precision is not high, and each data sampling point will be misaligned, which may not accurately reflect the actual operating state of the turbine unit when performing related operations or other analysis processing.
  • the measuring point decentralized collecting device can flexibly configure the collecting device according to different units and power plant requirements, the high-precision timing system is also expensive due to the aforementioned dispersion timing and sampling non-synchronization.
  • the number of measuring points of the device was constant. According to the maximum number of measuring points of the turbine group, the device can only be used in the large-scale turbine condition monitoring device. If it is installed in a small and medium-sized turbine group, it needs to be redesigned and modified, or the number of hardware configuration of the measuring point will be caused. waste.
  • the real-time state monitoring of the hydro-generator set vibration swing in the prior art hydropower plant has different number of measuring points, high sampling frequency requirement, large data volume and difficulty in synchronizing the sampling data of each measuring point. .
  • the object of the present invention is to overcome the deficiencies in the prior art, and to provide a configurable turbine vibration swing state monitoring device and a data acquisition method, and the number of sampling channels can be freely configured according to the type of the unit or the number of measuring points. High-speed sampling of up to 84 channels is possible, and all channel sampling data are simultaneously sampled to ensure the accuracy and validity of subsequent data analysis.
  • the present invention provides a configurable turbine vibration swing state monitoring device, which comprises a power module, a central processing module, a multi-channel high-speed analog signal acquisition module, and a module.
  • a configurable turbine vibration swing state monitoring device which comprises a power module, a central processing module, a multi-channel high-speed analog signal acquisition module, and a module.
  • the power module, the central processing module and the multi-channel high-speed analog signal acquisition module are sequentially arranged and plugged on the bottom plate of the module;
  • the output end of the power module provides a working power supply to the central processing unit module and a multi-channel high-speed analog signal acquisition module;
  • the central processing unit module includes an embedded processor module for channel configuration and an FPGA module for controlling sampling timing; the embedded processor module and the FPGA module are connected by a bus; and the transmission is received from the upper computer by the FPGA module. Channel configuration information and receiving sampling data uploaded by the FPGA module;
  • the high-speed analog signal acquisition module includes a CPLD module and an AD module for analog-to-digital conversion.
  • the input of the AD module collects analog signals output by each sensor of the turbine group; the FPGA module passes The parallel bus is connected with the CPLD module in each high-speed analog signal acquisition module; the CPLD module is connected to the AD module;
  • the FPGA module outputs sampling timing to each AD module through each CPLD module, and controls each AD module to simultaneously sample data. After the sampling data is completed, the FPGA module sequentially reads the sampling data of each AD module, and uploads the collected data to the embedded data. In the processor module.
  • each AD module includes two AD units.
  • the FPGA module opens two buffers for storing sample data in its internal storage space, and the two buffers perform ping-pong operations.
  • the number of channels of the high-speed analog signal acquisition module ranges from 1 to 84.
  • the present invention also provides a data collection method based on the above configurable monitoring device, which comprises:
  • the FPGA sends out the sampling signal SAMCLK to start sampling, and all channels AD simultaneously perform data acquisition. After the sampling ends, the AD returns to the ADBUSY signal;
  • the FPGA When the FPGA receives the ADBUSY signal of the first channel AD, it starts to read the sampling values of all the channels AD from the first channel in order to upload to the embedded processor module;
  • the next sampling clock arrives, repeating the above process and continuously sampling.
  • two data buffers are opened inside the FPGA, and the two buffers perform ping-pong operations.
  • the storage spaces of the two buffers are equally divided according to the number of channels, and the data sampled by each channel is stored in the order of the allocated address space.
  • the sampled data of one channel in the buffer is referred to as a segment, and the buffer generates a full flag signal while saving the segment sequence number information; then, when the data is read, the data is spliced according to the segment number.
  • the hardware can flexibly configure the number of high-speed sampling modules, realize the configurable hardware configuration, expand the adaptability range of the device, and facilitate the modification of the measurement and monitoring configuration on site;
  • sampling clock of AD in each channel is controlled by one signal of FPGA. All channels start sampling at the same time to ensure that all sampling data is one time, which provides more accurate original sampling data for turbine monitoring. Subsequent analysis and processing;
  • Two buffers are opened inside the FPGA, and the two buffers perform ping-pong operation to realize sampling without pause and data acquisition is not lost; and the data is saved by segments, and the sampled data is spliced to realize continuous sampling of data in the channel and in time. save.
  • Figure 1 is a schematic block diagram of a monitoring device of the present invention
  • FIG. 2 is a partial bus interface between an embedded processor and an FPGA module in a central processing unit according to an embodiment of the present invention
  • FIG. 3 is a custom high speed parallel bus interface between an FPGA and a high speed acquisition module according to an embodiment of the present invention
  • FIG. 4 is a schematic block diagram of a data collection method according to the present invention.
  • FIG. 5 is a schematic block diagram of two internal data buffers in an FPGA according to the present invention.
  • FIG. 6 is a block diagram of a format for saving data in an FPGA internal buffer according to an embodiment of the present invention.
  • Configuration means “configuration”, “setting”, “setting”, etc., meaning that the user completes the functions he needs in a simple way like “building blocks” instead of Need Rewrite the computer program, the so-called “configuration”.
  • a configurable turbine vibration swing state monitoring device of the present invention includes a power module, a central processing module, a multi-channel high-speed analog signal acquisition module, and a module bottom plate.
  • the power module, the central processing module and the plurality of high-speed analog signal acquisition modules are sequentially arranged and plugged and disposed on the bottom plate of the module;
  • the output of the power module provides a working power supply to the central processing unit module and a plurality of high speed analog signal acquisition modules;
  • the central processing unit module includes an embedded processor module for channel configuration and an FPGA module for controlling sampling timing; the embedded processor module and the FPGA module are connected by a bus; and the channel configuration received from the upper computer is transmitted to the FPGA module. Information and receiving sampling data uploaded by the FPGA module;
  • the high-speed analog signal acquisition module includes a CPLD module and an analog-to-digital conversion AD module.
  • the input of the AD module collects the analog signals output by the sensors of the turbine group; the FPGA module passes through the parallel bus and each high-speed analog signal acquisition module.
  • the CPLD module is connected; the sampling timing is transmitted to the CPLD module and the sampling data uploaded by the CPLD is received; the CPLD module is connected to the AD module; the sampling timing sent by the CPLD module is received, and the sampling data is uploaded to the CPLD module;
  • the FPGA module outputs sampling timing to each AD module through each CPLD module, and controls each AD module to simultaneously sample data. After the sampling data is completed, the FPGA module sequentially reads the sampling data of each AD module, and uploads the collected data to the embedded data. In the processor module.
  • each module is a separate casing module, wherein the power module and the central processing module are mandatory, and the high-speed analog signal acquisition module can be based on the unit size and measuring point.
  • the number of simple and flexible options for high-speed analog signal acquisition module can be one channel including high-speed analog signal acquisition module 1 shown in Figure 1, or high-speed analog signal acquisition module 1.
  • the central processing module includes the prior art PowerPC embedded processor module and the Xilinx field programmable gate array module (referred to as FPGA in this paper); wherein the FPGA is responsible for managing the sampling timing of all channels, completing data acquisition, buffering, Pre-processing and computing, etc., the embedded processor is mainly responsible for channel configuration, parameter loading, and at the same time sorting the data acquired by the FPGA and external communication.
  • FPGA field programmable gate array module
  • the upper computer when the upper computer configures the configurable monitoring device of the present invention, the upper computer (PC) is connected through the Ethernet and the configurable monitoring device. After the corresponding communication parameters are set, the required control function of the configurable monitoring device is configured in the upper computer (PC) environment, and after being compiled and processed successfully, the downloaded to the
  • the embedded processor of the monitoring device is configured to complete the configuration configuration of the plurality of configurable monitoring devices.
  • the embedded processor sets the number of channels and the sampling frequency according to the hardware information configured by the number of measuring points, and downloads them to the FPGA.
  • the embedded processor module of the central processing unit module and the FPGA module use the local bus (Local Bus) provided by the embedded processor for data interaction, and the interface signal definition between the FPGA and the FPGA module is as shown in FIG. 2 .
  • the communication rate can reach 66MHz.
  • the channel configuration information received by the embedded processor is transmitted to the FPGA through the bus, and the FPGA also transmits the sampled data data result to the embedded processor through the bus.
  • the high-speed analog signal acquisition module uses the prior art Complex Programmable Logic Device (CPLD) and 2 A high-speed multi-channel analog-to-digital converter module (referred to as AD), which realizes high-speed sampling, timing control, simple data processing of the sensor signal and interface function with the high-speed control bus of the FPGA.
  • the input of the multi-channel AD module collects the analog signals output by the sensors of the turbine group, and the AD module converts the analog signals into digital signals for output to the CPLD.
  • the AD module includes AD1 and AD2, and each AD is 8 bits, and each sample data is 2 bytes and 16 bits.
  • the FPGA module of the central processing unit module and the CPLD module of the plurality of high-speed analog signal acquisition modules are connected by a custom high-speed parallel bus.
  • the bus is shown in FIG. 3, wherein EXA is an address bus, EXD is a data bus, and EXWR_n is Write enable valid signal, EXRD_n is the read enable valid signal, EXRST is the reset signal, SAMCLK is the sampling timing, and ADBUSY is the sampling completion signal.
  • the sampling clock signal SAMCLK outputted by the FPGA is directly connected to the sampling clock of the AD module in all high-speed analog signal acquisition modules, so that all AD simultaneous sampling can be realized, and data acquisition is performed on the AD edge of the SAMCLK rising edge (acquisition of the turbine set vibration swing)
  • the analog signal output by the sensor after the sampling is finished, the sampled data is stored in the internal register of the AD, and the ADBUSY low level is output, indicating that the sampling is finished, and the data in the AD can be read; after the FPGA receives the signal, the FPGA starts.
  • Read the sampling data first make the read enable signal EXRD_n active low, sequentially strobe the CPLD of each channel through the EXA address bus, and then read the two AD internals through the EXD data bus and the AD_CS1 and AD_CS2 chip select signals. Sampling data.
  • the invention can simultaneously start sampling of all measuring points, ensure that sampling data of all measuring points are one time, and provide more accurate original sampling data for state monitoring of the turbine group, which is convenient for subsequent analysis and processing.
  • the FPGA sends out the sampling signal SAMCLK to start sampling, and all channels AD simultaneously perform data acquisition. After the sampling ends, the AD returns to the ADBUSY signal;
  • the FPGA When the FPGA receives the ADBUSY signal of the first channel AD, it starts to read the sampling values of all the channels AD from the first channel in order to upload to the embedded processor module;
  • the next sampling clock arrives, repeating the above process and continuously sampling.
  • AD Due to the high sampling speed of AD, the data bus throughput between the embedded processor and the FPGA is limited. After each sampling, the embedded processor cannot read the sampling data of the FPGA in time, resulting in the loss of sampling data. Embedded processors are overburdened and cannot perform other tasks such as communication and computing.
  • two data buffers are designed inside the FPGA, as shown in Figure 5, respectively, buf1 buffer and buf2 buffer, ping-pong operation That is, when the buf1 buffer is used to save the AD data, the buf2 buffer data is read by the embedded processor, and the buf2 buffer is used to store the AD data, and the buf1 buffer data is read by the embedded processor, so that it alternates.
  • the specific operation and data saving mode of the ping-pong buffer are as follows.
  • the storage space of the buf1 buffer and the buf2 buffer are equally divided according to the number of channels n, and the data of each channel AD is sampled according to the allocated address space. Sequential storage.
  • 84 high-speed sampling channels are taken as an example, and the format of the data saved in the FPGA internal buffer is as shown in FIG. 6.
  • the buf1 buffer size in the FPGA is 42K (bytes), and the buf2 buffer size is 42K (bytes).
  • the number of channels is 84, and each buffer is divided into 84 channel intervals, the first one.
  • the channel interval address is 0x00000 ⁇ 0x001FE
  • the second channel interval address is 0x00200 ⁇ 0x003FE
  • ... the 84th channel interval is 0x0A600 ⁇ 0x0A7FE; after reading the first sample data of all channels AD, it is put into the buf1 buffer first.
  • each channel interval address is offset by 256 samples until all channels The sampled values of the first point are saved to the buffer. Then continue the second sampled data. At the end of the second sample, since each sampled value is two bytes, all data is stored in 0+2 address, 0x00200+2 address, 0x00400+2 address, 0x00600+2 address, 0x00800. +2 address... 0x0A600+2 address.
  • the FPGA is a parallelizable processor, the sampling data is sent to the buf2 without affecting the data acquisition in the buf1, so that the sampling does not stop and the data acquisition is not lost.
  • the sampled data of 256 points in one channel in the buffer is called a segment.
  • a full flag signal is generated, and another register is designed inside the FPGA.
  • the embedded processor reads the data in the buffer, and also knows that the data is the first segment of the channel, and then performs data splicing according to the data sequence when reading the data, thereby realizing the Channels are continuously sampled and saved in time.
  • each buffer size is 84K (bytes)
  • each The channel storage space is 1K, and each channel can store 512 sample values.
  • the data acquisition method of the invention realizes synchronous sampling and data storage mode for all channels, and provides more accurate original sampling data for subsequent analysis, thereby more accurately monitoring the running state of the turbine unit.

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Abstract

Disclosed are a configurable device for monitoring vibration and swing states of a hydraulic turbine set, and a data acquisition method. In the monitoring device, a power supply module, a central processing unit module and a plurality of high-speed analogue signal acquisition modules (1, 2,,, n) are successively arranged on a module bottom board in a pluggable manner. The high-speed analogue signal acquisition modules can be freely configured according to the difference of unit types or numbers of measuring points. The data acquisition method comprises: when a sampling clock arrives, an FPGA sending out a sampling signal SAMCLK to start sampling, ADs of all the channels simultaneously carrying out data acquisition, and the ADs returning, after sampling is completed, ADBUSY signals ; when receiving the ADBUSY signals of the ADs of the first channel, the FPGA beginning to successively read, from the first channel, sampling values of the ADs of all the channels so as to upload same to an embedded processor module; and when the next sampling clock arrives, repeating the above processes and continuously carrying out sampling. Sampled data of all the channels are all sampled at the same moment, thereby ensuring the accuracy and effectiveness of subsequent data analysis.

Description

可组态的水轮机组振动摆度状态监测装置及数据采集方法Configurable turbine unit vibration swing state monitoring device and data acquisition method 技术领域Technical field
本发明属于水轮机组状态监测技术领域,具体涉及一种可组态的水轮机组振动摆度状态监测装置,还涉及一种基于此装置的高速数据采集方法。The invention belongs to the technical field of state monitoring of a water turbine unit, and particularly relates to a configurable vibration state monitoring device for a turbine unit, and to a high speed data acquisition method based on the device.
背景技术Background technique
在水电厂的运行设备中,水轮机组是非常重要且关键的主设备,其结构复杂,由主轴、定子、转子、上机架、下机架、顶盖等多个复杂部件组成。由于水轮机组不断需要受水力推动,工作环境较为恶劣,作为一种旋转机械,其最常见、最主要的故障是振动故障。早期对水轮机组的检修是定期停机时通过进行人工检查的方式进行,随着水轮机组老化,就需要经常停机检查,造成水电厂运行成本增加,同时也无法及时发现机组运行时的隐患或缺陷,也无法准确定位出隐患或缺陷的位置。后来随着技术手段的不断发展,通过在水轮机组各部件上安装振动、摆度等各种测量传感器,通过采集并计算这些传感器的振动、摆度、轴向位移、压力脉动、气隙等数据,就可以在线监测水轮机组主轴及相关零部件的运行状态。国家标准也要求,在大型水轮机组上必须设计振动摆度在线监测装置,中小型水轮机组也可参照进行。In the operation equipment of hydropower plants, the turbine unit is a very important and critical main equipment, which has a complicated structure and is composed of a plurality of complicated components such as a main shaft, a stator, a rotor, an upper frame, a lower frame and a top cover. As the turbine unit is constantly required to be driven by water and the working environment is relatively harsh, as a rotating machine, its most common and main fault is vibration failure. In the early stage, the maintenance of the turbine unit was carried out by means of manual inspection during regular shutdown. As the turbine unit ageed, frequent shutdown inspections were required, resulting in increased operating costs of the hydropower plant and the inability to detect potential hazards or defects during operation. It is also impossible to accurately locate the location of a hidden danger or defect. Later, with the continuous development of technical means, by installing various measuring sensors such as vibration and swing on the components of the turbine, the vibration, swing, axial displacement, pressure pulsation, air gap and other data of these sensors were collected and calculated. The operating status of the turbine head and related components can be monitored online. National standards also require that vibration swing on-line monitoring devices must be designed on large turbines, and small and medium-sized turbines can also be referenced.
由于水轮发电机组种类也较多,如混流式机组、轴流式机组、贯流式机组、冲击式机组等,其测点配置数量也不一样,即使是同一种类型机组,各个发电厂对测点数量和位置的设计也不尽相同,特别是中小型水轮机组和大型水轮机组,其测点数量差别更大。Because there are many types of hydroelectric generating units, such as mixed flow units, axial flow units, tubular units, impact units, etc., the number of measuring points is different. Even for the same type of unit, each power plant The design of the number and location of measuring points is also different, especially for small and medium-sized turbines and large turbines.
现有对水轮机组振动摆度等传感器的数据采集方法,一种是在各传感器测点位置分散设计单独采集装置,然后通过通讯的方式汇集所有测点数据,在后 台进行分析和处理。后来由于这种方法对采样数据处理的不及时,无法及时进行故障或隐患判断,后来发展成一种集中式采集方式,即把各种测点数据采集模块放在同一个装置类,在现地就可以进行数据采集、分析很判断。There are existing data acquisition methods for sensors such as the vibration swing of a turbine unit. One is to design a separate acquisition device at each sensor measurement point position, and then collect all the measurement point data by means of communication. The station analyzes and processes it. Later, due to the untimely processing of the sampled data by this method, it was impossible to judge faults or hidden dangers in time, and later developed into a centralized collection method, that is, the various data acquisition modules of the measurement points were placed in the same device class, Data collection and analysis can be judged.
一般集中式水轮发电机组振动摆度数据采集装置,一般测点数比较固定,都是按照大型机组的配置要求设计的,如果需要配置成测点少的中心型水轮机组,在硬件上和嵌入式软件都要做较大的修改,自适应能力较差,另外其高速采集模块之间采用软件对时方式实现采样通道数据的对齐。General centralized hydro-generator set vibration swing data acquisition device, the general number of points is relatively fixed, are designed according to the configuration requirements of large units, if you need to configure a central type of turbines with fewer points, in hardware and embedded The software has to be modified greatly, and the adaptive ability is poor. In addition, the high-speed acquisition module uses the software timing method to achieve the alignment of the sampling channel data.
不管是在各测点分散采集,还是集中在一个装置内进行数据采集,在后来对水轮机组振动、摆度、轴向位移、压力脉动、气隙等采样数据的分析并进行故障判断时,发现水轮机组不稳定或故障时,这些部件数据具有时间上的相关性,某些测点间需要进行相关性计算和分析,即要求最好在同时刻对水轮机组的各位置传感器的数据进行采集,才能对设备的运行状态进行准确的分析和判断。而分散采集的装置,虽然各独立装置进行了一定的对时处理,也只是精确到毫秒级,甚至秒级。而原来的集中式采样装置,虽然可采集模块放在同一装置内部,各模块之间也是采取对时方式,仅一个采集模块内部通道才能实现同步同时刻采样,而模块之间依然存在数据采样时刻不一致的情况,各测点的采样数据时间误差取决于对时方式和和模块内部的定时精度,对于振动摆度等这些高频信号,需要的采样率达到1KHz、10KHz,甚至更高,如果对时精度不高,各数据采样点会错位严重,造成进行相关运算或其他分析处理时不能准确反映水轮机组真实的运行状态。Whether it is scattered acquisition at each measuring point or centralized in one device for data acquisition, after analyzing the sampling data of turbine turbine vibration, swing, axial displacement, pressure pulsation, air gap and other faults, it is found that When the turbine unit is unstable or faulty, the data of these components have temporal correlation, and some correlation calculations and analysis are required between the measurement points, that is, it is required to collect data of each position sensor of the turbine unit at the same time. In order to accurately analyze and judge the operating status of the equipment. The decentralized acquisition device, although each independent device performs a certain timing processing, is only accurate to the millisecond level, or even the second level. In the original centralized sampling device, although the acquisition module is placed inside the same device, the timing mode is adopted between each module, and only one internal channel of the acquisition module can realize synchronous simultaneous sampling, and data sampling moments still exist between the modules. Inconsistent, the time error of the sampling data of each measuring point depends on the timing mode and the timing accuracy inside the module. For the high-frequency signals such as the vibration swing, the required sampling rate is 1KHz, 10KHz, or even higher. The time precision is not high, and each data sampling point will be misaligned, which may not accurately reflect the actual operating state of the turbine unit when performing related operations or other analysis processing.
另外,测点分散采集装置虽然可以根据机组不同、电厂要求不同灵活配置采集装置,但是由于前述分散对时、采样非同步等原因,为其配置高精度对时***,也带了成本过高。而早期的集中式采集装置,装置的测点数量一定,需 要按照水轮机组最大测点数量进行配置,造成该装置只能用在大型水轮机状态监测装置中,如果安装在中小型水轮机组,要么需要重新设计、修改估计,要么会造成测点硬件配置数量的浪费。In addition, although the measuring point decentralized collecting device can flexibly configure the collecting device according to different units and power plant requirements, the high-precision timing system is also expensive due to the aforementioned dispersion timing and sampling non-synchronization. In the early centralized collection device, the number of measuring points of the device was constant. According to the maximum number of measuring points of the turbine group, the device can only be used in the large-scale turbine condition monitoring device. If it is installed in a small and medium-sized turbine group, it needs to be redesigned and modified, or the number of hardware configuration of the measuring point will be caused. waste.
综上所述,现有技术中水力发电厂中的水轮发电机组振动摆度实时状态监测,存在测点布置数量不同、采样频率要求高、数据量大及各测点采样数据难以同步性问题。In summary, the real-time state monitoring of the hydro-generator set vibration swing in the prior art hydropower plant has different number of measuring points, high sampling frequency requirement, large data volume and difficulty in synchronizing the sampling data of each measuring point. .
发明内容Summary of the invention
本发明的目的在于克服现有技术中的不足,提供了一种可组态的水轮机组振动摆度状态监测装置及数据采集方法,采样通道数量可以根据机组类型或测点数量的不同自由配置,可实现多达84个通道的高速采样,所有通道采样数据均为同时刻采样,保证后续数据分析的准确性和有效性。The object of the present invention is to overcome the deficiencies in the prior art, and to provide a configurable turbine vibration swing state monitoring device and a data acquisition method, and the number of sampling channels can be freely configured according to the type of the unit or the number of measuring points. High-speed sampling of up to 84 channels is possible, and all channel sampling data are simultaneously sampled to ensure the accuracy and validity of subsequent data analysis.
为解决上述技术问题,本发明提供了一种可组态的水轮机组振动摆度状态监测装置,其特征是,包括电源模件、中央处理器模件、多路高速模拟信号采集模件以及模件底板;In order to solve the above technical problem, the present invention provides a configurable turbine vibration swing state monitoring device, which comprises a power module, a central processing module, a multi-channel high-speed analog signal acquisition module, and a module. Bottom plate
其中电源模件、中央处理器模件以及多路高速模拟信号采集模件依次排序可插拔地设置在模件底板上;The power module, the central processing module and the multi-channel high-speed analog signal acquisition module are sequentially arranged and plugged on the bottom plate of the module;
电源模件的输出端提供工作电源至中央处理器模件及多路高速模拟信号采集模件;The output end of the power module provides a working power supply to the central processing unit module and a multi-channel high-speed analog signal acquisition module;
中央处理器模件包括用于通道配置的嵌入式处理器模块和用于控制采样时序的FPGA模块;嵌入式处理器模块和FPGA模块之间通过总线连接;以向FPGA模块传输接收自上位机的通道配置信息以及接收FPGA模块上传的采样数据;The central processing unit module includes an embedded processor module for channel configuration and an FPGA module for controlling sampling timing; the embedded processor module and the FPGA module are connected by a bus; and the transmission is received from the upper computer by the FPGA module. Channel configuration information and receiving sampling data uploaded by the FPGA module;
高速模拟信号采集模件包括CPLD模块和用于模数转换的AD模块,AD模块的输入端采集部署在水轮机组的各传感器输出的模拟信号;FPGA模块通过 并行总线与各路高速模拟信号采集模件中的CPLD模块连接;CPLD模块连接AD模块;The high-speed analog signal acquisition module includes a CPLD module and an AD module for analog-to-digital conversion. The input of the AD module collects analog signals output by each sensor of the turbine group; the FPGA module passes The parallel bus is connected with the CPLD module in each high-speed analog signal acquisition module; the CPLD module is connected to the AD module;
FPGA模块通过各路CPLD模块同时向各AD模块输出采样时序,控制各路AD模块同时采样数据,采样数据完成后,FPGA模块依次读取各路AD模块的采样数据,并将采集数据上传至嵌入式处理器模块中。The FPGA module outputs sampling timing to each AD module through each CPLD module, and controls each AD module to simultaneously sample data. After the sampling data is completed, the FPGA module sequentially reads the sampling data of each AD module, and uploads the collected data to the embedded data. In the processor module.
进一步的,每路AD模块中包括两个AD单元。Further, each AD module includes two AD units.
进一步的,FPGA模块在其内部存储空间开辟两个用于存储采样数据的缓冲区,两个缓冲区进行乒乓操作。Further, the FPGA module opens two buffers for storing sample data in its internal storage space, and the two buffers perform ping-pong operations.
进一步的,高速模拟信号采集模件的通道数量范围为1~84。Further, the number of channels of the high-speed analog signal acquisition module ranges from 1 to 84.
相应的,本发明还提供了一种基于上述可组态的监测装置的数据采集方法,其特征是,包括:Correspondingly, the present invention also provides a data collection method based on the above configurable monitoring device, which comprises:
采样时钟到来,FPGA发出采样信号SAMCLK启动采样,所有通道AD同时进行数据采集,采样结束后AD返回ADBUSY信号;When the sampling clock arrives, the FPGA sends out the sampling signal SAMCLK to start sampling, and all channels AD simultaneously perform data acquisition. After the sampling ends, the AD returns to the ADBUSY signal;
FPGA接收到第一个通道AD的ADBUSY信号时,开始从第一个通道依次读取所有通道AD的采样值,以上传至嵌入式处理器模块;When the FPGA receives the ADBUSY signal of the first channel AD, it starts to read the sampling values of all the channels AD from the first channel in order to upload to the embedded processor module;
下一个采样时钟到来,重复以上过程,不断进行采样。The next sampling clock arrives, repeating the above process and continuously sampling.
进一步的,在FPGA内部开辟两个数据缓冲区,两个缓冲区进行乒乓操作。Further, two data buffers are opened inside the FPGA, and the two buffers perform ping-pong operations.
进一步的,两个缓冲区的存储空间均按照通道数量均分,各通道每次采样的数据按照分配的地址空间顺序存储。Further, the storage spaces of the two buffers are equally divided according to the number of channels, and the data sampled by each channel is stored in the order of the allocated address space.
进一步的,将缓冲区内一个通道的采样数据称为一个片段,缓冲区产生满标志信号的同时,保存片段序号信息;然后在读取数据时按照片段序号进行数据拼接。Further, the sampled data of one channel in the buffer is referred to as a segment, and the buffer generates a full flag signal while saving the segment sequence number information; then, when the data is read, the data is spliced according to the segment number.
与现有技术相比,本发明所达到的有益效果是: Compared with the prior art, the beneficial effects achieved by the present invention are:
1)可以根据水轮机组不同及测点数量不同,硬件可灵活配置高速采样模件数量,实现可组态硬件配置,扩大了装置的适应范围,方便现场对测量和监测的配置进行修改;1) According to the different turbines and the number of measuring points, the hardware can flexibly configure the number of high-speed sampling modules, realize the configurable hardware configuration, expand the adaptability range of the device, and facilitate the modification of the measurement and monitoring configuration on site;
2)各通道AD的采样时钟均由FPGA一个信号进行控制,所有通道同时刻启动采样,保证所有测点采样数据均为一个时刻的,为水轮机组状态监测提供更为准确的原始采样数据,便于后续分析和处理;2) The sampling clock of AD in each channel is controlled by one signal of FPGA. All channels start sampling at the same time to ensure that all sampling data is one time, which provides more accurate original sampling data for turbine monitoring. Subsequent analysis and processing;
3)FPGA内部开辟两个缓冲区,两个缓冲区进行乒乓操作从而实现采样不停顿与数据获取不丢失;并且数据按片段保存、拼接采样数据,实现该通道在时间上连续不断的数据采样和保存。3) Two buffers are opened inside the FPGA, and the two buffers perform ping-pong operation to realize sampling without pause and data acquisition is not lost; and the data is saved by segments, and the sampled data is spliced to realize continuous sampling of data in the channel and in time. save.
附图说明DRAWINGS
图1为本发明监测装置的原理框图;Figure 1 is a schematic block diagram of a monitoring device of the present invention;
图2为本发明实施例中中央处理器内部嵌入式处理器和FPGA模块之间的局部总线接口;2 is a partial bus interface between an embedded processor and an FPGA module in a central processing unit according to an embodiment of the present invention;
图3为本发明实施例中FPGA和高速采集模件之间的自定义高速并行总线接口;3 is a custom high speed parallel bus interface between an FPGA and a high speed acquisition module according to an embodiment of the present invention;
图4为本发明数据采集方法的原理框图;4 is a schematic block diagram of a data collection method according to the present invention;
图5为本发明中FPGA内部两个数据缓冲区的原理框图;FIG. 5 is a schematic block diagram of two internal data buffers in an FPGA according to the present invention; FIG.
图6为本发明实施例中FPGA内部缓冲区保存数据的格式框图。FIG. 6 is a block diagram of a format for saving data in an FPGA internal buffer according to an embodiment of the present invention.
具体实施方式detailed description
下面结合附图对本发明作进一步描述。以下实施例仅用于更加清楚地说明本发明的技术方案,而不能以此来限制本发明的保护范围。The invention is further described below in conjunction with the drawings. The following examples are only intended to more clearly illustrate the technical solutions of the present invention, and are not intended to limit the scope of the present invention.
组态:“组态(Configure)”的含义是“配置”、“设定”、“设置”等意思,是指用户通过类似“搭积木”的简单方式来完成自己所需要的功能,而不需要 重新编写计算机程序,也就是所谓的“组态”。Configuration: "Configure" means "configuration", "setting", "setting", etc., meaning that the user completes the functions he needs in a simple way like "building blocks" instead of Need Rewrite the computer program, the so-called "configuration".
本发明的一种可组态的水轮机组振动摆度状态监测装置,如图1所示,包括电源模件、中央处理器模件、多路高速模拟信号采集模件以及模件底板,A configurable turbine vibration swing state monitoring device of the present invention, as shown in FIG. 1, includes a power module, a central processing module, a multi-channel high-speed analog signal acquisition module, and a module bottom plate.
其中电源模件、中央处理器模件以及多个高速模拟信号采集模件依次排序可插拔地设置在模件底板上;The power module, the central processing module and the plurality of high-speed analog signal acquisition modules are sequentially arranged and plugged and disposed on the bottom plate of the module;
电源模件的输出端提供工作电源至中央处理器模件及多个高速模拟信号采集模件;The output of the power module provides a working power supply to the central processing unit module and a plurality of high speed analog signal acquisition modules;
中央处理器模件包括用于通道配置的嵌入式处理器模块和控制采样时序的FPGA模块;嵌入式处理器模块和FPGA模块之间通过总线连接;以向FPGA模块传输接收自上位机的通道配置信息以及接收FPGA模块上传的采样数据;The central processing unit module includes an embedded processor module for channel configuration and an FPGA module for controlling sampling timing; the embedded processor module and the FPGA module are connected by a bus; and the channel configuration received from the upper computer is transmitted to the FPGA module. Information and receiving sampling data uploaded by the FPGA module;
高速模拟信号采集模件包括CPLD模块和模数转换的AD模块,AD模块的输入端采集部署在水轮机组的各传感器输出的模拟信号;FPGA模块通过并行总线与各路高速模拟信号采集模件中的CPLD模块连接;以向CPLD模块传输采样时序以及接收CPLD上传的采样数据;CPLD模块连接AD模块;以接收CPLD模块发出的采样时序以及向CPLD模块上传采样数据;The high-speed analog signal acquisition module includes a CPLD module and an analog-to-digital conversion AD module. The input of the AD module collects the analog signals output by the sensors of the turbine group; the FPGA module passes through the parallel bus and each high-speed analog signal acquisition module. The CPLD module is connected; the sampling timing is transmitted to the CPLD module and the sampling data uploaded by the CPLD is received; the CPLD module is connected to the AD module; the sampling timing sent by the CPLD module is received, and the sampling data is uploaded to the CPLD module;
FPGA模块通过各路CPLD模块同时向各AD模块输出采样时序,控制各路AD模块同时采样数据,采样数据完成后,FPGA模块依次读取各路AD模块的采样数据,并将采集数据上传至嵌入式处理器模块中。The FPGA module outputs sampling timing to each AD module through each CPLD module, and controls each AD module to simultaneously sample data. After the sampling data is completed, the FPGA module sequentially reads the sampling data of each AD module, and uploads the collected data to the embedded data. In the processor module.
本发明实施例中,除模件底板外,各个模件均为独立外壳模件,其中电源模件和中央处理器模件为必配,而高速模拟信号采集模件可以根据机组大小、测点数量进行简单灵活选配高速模拟信号采集模件数量,可以是图1所示的包括高速模拟信号采集模件1的1路通道,也可以是包含高速模拟信号采集模件1、高速模拟信号采集模件2以及高速模拟信号采集模件3构成的3路通道;还可 以包含高速模拟信号采集模件1、高速模拟信号采集模件2……高速模拟信号采集模件n构成的n路通道,本实施例中最多可以配置84个通道。只需要把需求特定数量的高速模拟信号采集模件***模件底板,上位机(PC机)进行简单设置中央处理器模件,即可完成现场配置的修改。扩大了装置的适应范围,方便现场对测量和监测的配置进行修改。In the embodiment of the present invention, except for the bottom plate of the module, each module is a separate casing module, wherein the power module and the central processing module are mandatory, and the high-speed analog signal acquisition module can be based on the unit size and measuring point. The number of simple and flexible options for high-speed analog signal acquisition module can be one channel including high-speed analog signal acquisition module 1 shown in Figure 1, or high-speed analog signal acquisition module 1. High-speed analog signal acquisition 3 channels formed by the module 2 and the high-speed analog signal acquisition module 3; In the embodiment, up to 84 channels can be configured in the embodiment, including the high-speed analog signal acquisition module 1, the high-speed analog signal acquisition module 2, and the high-speed analog signal acquisition module n. Only need to insert a certain number of high-speed analog signal acquisition modules into the module backplane, and the host computer (PC) can simply set the central processor module to complete the modification of the field configuration. The range of adaptation of the device has been expanded to facilitate the modification of the measurement and monitoring configuration on site.
中央处理器模件包括现有技术中的PowerPC嵌入式处理器模块和Xilinx现场可编程门阵列模块(本文中简称FPGA);其中FPGA负责对所有通道的采样时序进行管理,完成数据获取、缓存、预处理和运算等,嵌入式处理器主要负责通道配置、参数加载,同时对FPGA获取的数据进行整理以及对外通讯等功能。The central processing module includes the prior art PowerPC embedded processor module and the Xilinx field programmable gate array module (referred to as FPGA in this paper); wherein the FPGA is responsible for managing the sampling timing of all channels, completing data acquisition, buffering, Pre-processing and computing, etc., the embedded processor is mainly responsible for channel configuration, parameter loading, and at the same time sorting the data acquired by the FPGA and external communication.
本发明实施例中,上位机对本发明可组态监测装置进行组态时,由上位机(PC机)通过以太网和可组态监测装置相连。在相应的通讯参数设置完毕后,在上位机(PC机)环境中对所需的所述可组态监测装置的控制功能进行软件组态,经编译处理成功后通过以太网下载到所述可组态监测装置的嵌入式处理器中,从而完成多所述可组态监测装置的组态配置。嵌入式处理器根据测点数量所配置的硬件信息,设置通道数量和采样频率,并下载至FPGA中。In the embodiment of the present invention, when the upper computer configures the configurable monitoring device of the present invention, the upper computer (PC) is connected through the Ethernet and the configurable monitoring device. After the corresponding communication parameters are set, the required control function of the configurable monitoring device is configured in the upper computer (PC) environment, and after being compiled and processed successfully, the downloaded to the The embedded processor of the monitoring device is configured to complete the configuration configuration of the plurality of configurable monitoring devices. The embedded processor sets the number of channels and the sampling frequency according to the hardware information configured by the number of measuring points, and downloads them to the FPGA.
中央处理器模件的嵌入式处理器模块与FPGA模块之间采用嵌入式处理器自带的局部总线(Local Bus)进行数据交互,其与FPGA模块之间的接口信号定义如图2所示,包括Addr地址线、Data数据线以及片选CS、写使能WE和数据输出使能OE信号等,通讯速率可达66MHz。嵌入式处理器接收到的通道配置信息通过该总线传输至FPGA中,FPGA也是通过该总线把采样数据数据结果传输至嵌入式处理器中。The embedded processor module of the central processing unit module and the FPGA module use the local bus (Local Bus) provided by the embedded processor for data interaction, and the interface signal definition between the FPGA and the FPGA module is as shown in FIG. 2 . Including Addr address line, Data data line and chip select CS, write enable WE and data output enable OE signal, etc., the communication rate can reach 66MHz. The channel configuration information received by the embedded processor is transmitted to the FPGA through the bus, and the FPGA also transmits the sampled data data result to the embedded processor through the bus.
高速模拟信号采集模件采用现有技术中复杂可编程逻辑器件(CPLD)和2 个高速多通道模数转换器模块(简称AD)组成,实现对传感器信号进行高速采样、时序控制、简单的数据处理以及与FPGA的高速控制总线的接口功能。多通道AD模块的输入端采集部署在水轮机组的各传感器输出的模拟信号,AD模块将模拟信号转换为数字信号输出至CPLD。本实施例中AD模块包括AD1和AD2,每个AD为8位,则每个采样数据为2字节16位。The high-speed analog signal acquisition module uses the prior art Complex Programmable Logic Device (CPLD) and 2 A high-speed multi-channel analog-to-digital converter module (referred to as AD), which realizes high-speed sampling, timing control, simple data processing of the sensor signal and interface function with the high-speed control bus of the FPGA. The input of the multi-channel AD module collects the analog signals output by the sensors of the turbine group, and the AD module converts the analog signals into digital signals for output to the CPLD. In this embodiment, the AD module includes AD1 and AD2, and each AD is 8 bits, and each sample data is 2 bytes and 16 bits.
中央处理器模件的FPGA模块与多个高速模拟信号采集模件中的CPLD模块通过自定义高速并行总线连接,该总线如图3所示,其中EXA为地址总线,EXD为数据总线,EXWR_n为写使能有效信号,EXRD_n为读使能有效信号,EXRST为复位信号,SAMCLK为采样时序,ADBUSY为采样完成信号。把FPGA输出的采样时钟信号SAMCLK直接和所有高速模拟信号采集模件中的AD模块的采样时钟相连,可以实现所有AD同时采样,在该时钟SAMCLK上升沿AD进行数据采集(采集水轮机组振动摆度传感器输出的模拟信号),采样结束后采样数据保存在AD的内部寄存器中,并输出ADBUSY低电平,表示本次采样结束,AD内有数据可以读取;FPGA收到该信号之后,FPGA开始读取采样数据,先使读使能信号EXRD_n低电平有效,通过EXA地址总线依次选通各通道的CPLD,就可以通过EXD数据总线以及AD_CS1和AD_CS2片选信号,先后读取两个AD内部的采样数据。The FPGA module of the central processing unit module and the CPLD module of the plurality of high-speed analog signal acquisition modules are connected by a custom high-speed parallel bus. The bus is shown in FIG. 3, wherein EXA is an address bus, EXD is a data bus, and EXWR_n is Write enable valid signal, EXRD_n is the read enable valid signal, EXRST is the reset signal, SAMCLK is the sampling timing, and ADBUSY is the sampling completion signal. The sampling clock signal SAMCLK outputted by the FPGA is directly connected to the sampling clock of the AD module in all high-speed analog signal acquisition modules, so that all AD simultaneous sampling can be realized, and data acquisition is performed on the AD edge of the SAMCLK rising edge (acquisition of the turbine set vibration swing) The analog signal output by the sensor), after the sampling is finished, the sampled data is stored in the internal register of the AD, and the ADBUSY low level is output, indicating that the sampling is finished, and the data in the AD can be read; after the FPGA receives the signal, the FPGA starts. Read the sampling data, first make the read enable signal EXRD_n active low, sequentially strobe the CPLD of each channel through the EXA address bus, and then read the two AD internals through the EXD data bus and the AD_CS1 and AD_CS2 chip select signals. Sampling data.
因此,本发明可以同时启动所有测点的采样,保证所有测点采样数据均为一个时刻的,为水轮机组状态监测提供更为准确的原始采样数据,便于后续分析和处理。Therefore, the invention can simultaneously start sampling of all measuring points, ensure that sampling data of all measuring points are one time, and provide more accurate original sampling data for state monitoring of the turbine group, which is convenient for subsequent analysis and processing.
相应的,本发明的基于上述可组态的监测装置的数据采集方法,包括:Correspondingly, the data collection method of the present invention based on the above configurable monitoring device comprises:
采样时钟到来,FPGA发出采样信号SAMCLK启动采样,所有通道AD同时进行数据采集,采样结束后AD返回ADBUSY信号; When the sampling clock arrives, the FPGA sends out the sampling signal SAMCLK to start sampling, and all channels AD simultaneously perform data acquisition. After the sampling ends, the AD returns to the ADBUSY signal;
FPGA接收到第一个通道AD的ADBUSY信号时,开始从第一个通道依次读取所有通道AD的采样值,以上传至嵌入式处理器模块;When the FPGA receives the ADBUSY signal of the first channel AD, it starts to read the sampling values of all the channels AD from the first channel in order to upload to the embedded processor module;
下一个采样时钟到来,重复以上过程,不断进行采样。The next sampling clock arrives, repeating the above process and continuously sampling.
FPGA与多个高速模拟信号采集模件之间接口如图4所示,所有AD采样的时钟信号SAMCLK,均通过CPLD电路直接连接在一起,受中央处理器模件上的FPGA控制,一旦FPGA启动采样,SAMCLK上升沿时,所有AD同时进行数据采集,采样结束后AD的ADBUSY信号由高变低,表示第一次采样结束,FPGA以第一个通道AD的ADBUSY信号低为标志,在第二个采样时钟SAMCLK上升沿到来之前,通过高速并行总线从第一个通道至最后一个通道,依次读取所有通道的AD采样值,并保存至FPGA内部的数据缓冲区中,以备后续嵌入式处理器来读取。第二个采样时钟来之后,又同时启动所有AD采样,采样结束后按照ADBUSY信号标志读取所有通道的采样数据,如此不断进行启动采样、数据获取和数据缓冲,确保高速连续不断采样。The interface between FPGA and multiple high-speed analog signal acquisition modules is shown in Figure 4. All AD sampled clock signals, SAMCLK, are directly connected together through the CPLD circuit, controlled by the FPGA on the central processor module, once the FPGA is started. When sampling, on the rising edge of SAMCLK, all ADs simultaneously acquire data. After the sampling ends, the ADBUSY signal of AD changes from high to low, indicating that the first sampling ends, and the FPGA uses the ADBUSY signal of the first channel AD as the low flag. Before the rising edge of the sampling clock SAMCLK, the AD sample value of all channels is read sequentially from the first channel to the last channel through the high-speed parallel bus, and saved to the data buffer inside the FPGA for subsequent embedded processing. Read to read. After the second sampling clock comes, all AD samples are started at the same time. After the sampling is finished, the sampling data of all channels is read according to the ADBUSY signal flag, so that the sampling, data acquisition and data buffering are continuously performed to ensure high-speed continuous sampling.
由于AD采样速度很高,嵌入式处理器和FPGA之间的数据总线吞吐率有限,每次采样结束之后,嵌入式处理器是无法及时来读取FPGA的采样数据,造成采样数据丢失,也造成嵌入式处理器负担过重,无法完成其他如通讯及计算等任务。为了保证高速AD不间断采样和采样数据能完整地被嵌入式处理器读取,在FPGA内部设计两个数据缓冲区,如图5所示,分别为buf1缓冲区和buf2缓冲区,进行乒乓操作,即buf1缓冲区为保存AD数据时候,buf2缓冲区数据供嵌入式处理器读取,buf2缓冲区为保存AD数据时候,buf1缓冲区数据供嵌入式处理器读取,如此交替工作。Due to the high sampling speed of AD, the data bus throughput between the embedded processor and the FPGA is limited. After each sampling, the embedded processor cannot read the sampling data of the FPGA in time, resulting in the loss of sampling data. Embedded processors are overburdened and cannot perform other tasks such as communication and computing. In order to ensure high-speed AD uninterrupted sampling and sampling data can be completely read by the embedded processor, two data buffers are designed inside the FPGA, as shown in Figure 5, respectively, buf1 buffer and buf2 buffer, ping-pong operation That is, when the buf1 buffer is used to save the AD data, the buf2 buffer data is read by the embedded processor, and the buf2 buffer is used to store the AD data, and the buf1 buffer data is read by the embedded processor, so that it alternates.
乒乓缓冲区具体操作及数据保存方式如下,buf1缓冲区和buf2缓冲区的存储空间按照通道数量n均分,各通道AD每次采样的数据按照分配的地址空间 顺序存储。The specific operation and data saving mode of the ping-pong buffer are as follows. The storage space of the buf1 buffer and the buf2 buffer are equally divided according to the number of channels n, and the data of each channel AD is sampled according to the allocated address space. Sequential storage.
本实施例以84个高速采样通道为例,FPGA内部缓冲区保存数据的格式如图6所示。FPGA内buf1缓冲区大小为42K(字节),buf2缓冲区大小为42K(字节),按照本实施例中通道数为84,将每个缓冲区均分为84个通道区间,第一个通道区间地址为0x00000~0x001FE,第二个通道区间地址为0x00200~0x003FE,……第84个通道区间为0x0A600~0x0A7FE;读取所有通道AD第一个采样数据之后,先放入到buf1缓冲区的0地址、0x00200地址、0x00400地址、0x00600地址、0x00800地址……0x0A600,由于本实施例中一个采样数据占两个字节,因此各通道区间地址之间偏移256个采样,直到所有通道的第一个点的采样值都被保存至缓冲区中。然后继续第二个采样数据,第二个采样结束时,由于每个采样值为两个字节所有数据保存在0+2地址、0x00200+2地址、0x00400+2地址、0x00600+2地址、0x00800+2地址……0x0A600+2地址中。如此不断进行采样和保存,直到buf1缓冲区保存满,产生满标志,通知嵌入式处理器读取缓冲区buf1内的数据,后续的AD采样数据则开始存入buf2缓冲区,buf2缓冲区的划分和数据保存方式参见buf1缓冲区,在此不再赘述。由于FPGA为可并行处理器,采样数据送至buf2时完全不影响buf1内的数据获取,从而实现采样不停顿与数据获取不丢失。In this embodiment, 84 high-speed sampling channels are taken as an example, and the format of the data saved in the FPGA internal buffer is as shown in FIG. 6. The buf1 buffer size in the FPGA is 42K (bytes), and the buf2 buffer size is 42K (bytes). According to this embodiment, the number of channels is 84, and each buffer is divided into 84 channel intervals, the first one. The channel interval address is 0x00000~0x001FE, the second channel interval address is 0x00200~0x003FE, ... the 84th channel interval is 0x0A600~0x0A7FE; after reading the first sample data of all channels AD, it is put into the buf1 buffer first. 0 address, 0x00200 address, 0x00400 address, 0x00600 address, 0x00800 address... 0x0A600, since one sampled data occupies two bytes in this embodiment, each channel interval address is offset by 256 samples until all channels The sampled values of the first point are saved to the buffer. Then continue the second sampled data. At the end of the second sample, since each sampled value is two bytes, all data is stored in 0+2 address, 0x00200+2 address, 0x00400+2 address, 0x00600+2 address, 0x00800. +2 address... 0x0A600+2 address. So continue to sample and save until the buf1 buffer is full, generate a full flag, notify the embedded processor to read the data in the buffer buf1, the subsequent AD sample data is stored in the buf2 buffer, the division of the buf2 buffer For details about how to save data, see the buf1 buffer, which is not mentioned here. Since the FPGA is a parallelizable processor, the sampling data is sent to the buf2 without affecting the data acquisition in the buf1, so that the sampling does not stop and the data acquisition is not lost.
为了便于嵌入式处理器辨认数据并进行处理,把缓冲区内的一个通道256点的采样数据称为一个片段,第一次buf1满时,产生满标志信号的同时,另外在FPGA内部设计一个寄存器来保存片段序号信息,嵌入式处理器在读取缓冲区内数据的同时,也同时知道该数据是该通道的第几个片段,然后在读取数据时按照数据序号进行数据拼接,从而实现该通道在时间上连续不断的数据采样和保存。 In order to facilitate the embedded processor to recognize the data and process it, the sampled data of 256 points in one channel in the buffer is called a segment. When the first buf1 is full, a full flag signal is generated, and another register is designed inside the FPGA. To save the segment serial number information, the embedded processor reads the data in the buffer, and also knows that the data is the first segment of the channel, and then performs data splicing according to the data sequence when reading the data, thereby realizing the Channels are continuously sampled and saved in time.
如果FPGA内置的RAM容量够大,可以不按照256个点作为片段,而是可以按照512点、1024点、2048点作为片段进行处理,例如各缓冲区大小为84K(字节),则每个通道存储空间为1K,各通道可以存储512个采样值。If the built-in RAM of the FPGA is large enough, it can be processed as 256 points, 1024 points, and 2048 points instead of 256 points. For example, each buffer size is 84K (bytes), then each The channel storage space is 1K, and each channel can store 512 sample values.
本发明数据采集方法实现对于所有通道同步采样和数据保存方式,提供更加准确的原始采样数据供后续分析,从而更加准确的监测水轮机组的运行状态。The data acquisition method of the invention realizes synchronous sampling and data storage mode for all channels, and provides more accurate original sampling data for subsequent analysis, thereby more accurately monitoring the running state of the turbine unit.
以上所述仅是本发明的优选实施方式,应当指出,对于本技术领域的普通技术人员来说,在不脱离本发明技术原理的前提下,还可以做出若干改进和变型,这些改进和变型也应视为本发明的保护范围。 The above is only a preferred embodiment of the present invention, and it should be noted that those skilled in the art can make several improvements and modifications without departing from the technical principles of the present invention. It should also be considered as the scope of protection of the present invention.

Claims (8)

  1. 可组态的水轮机组振动摆度状态监测装置,其特征是,包括电源模件、中央处理器模件、多路高速模拟信号采集模件以及模件底板;The configurable turbine vibration swing state monitoring device comprises a power module, a central processing module, a multi-channel high-speed analog signal acquisition module and a module bottom plate;
    其中电源模件、中央处理器模件以及多路高速模拟信号采集模件依次排序可插拔地设置在模件底板上;The power module, the central processing module and the multi-channel high-speed analog signal acquisition module are sequentially arranged and plugged on the bottom plate of the module;
    电源模件的输出端提供工作电源至中央处理器模件及多路高速模拟信号采集模件;The output end of the power module provides a working power supply to the central processing unit module and a multi-channel high-speed analog signal acquisition module;
    中央处理器模件包括用于通道配置的嵌入式处理器模块和用于控制采样时序的FPGA模块;嵌入式处理器模块和FPGA模块之间通过总线连接;以向FPGA模块传输接收自上位机的通道配置信息以及接收FPGA模块上传的采样数据;The central processing unit module includes an embedded processor module for channel configuration and an FPGA module for controlling sampling timing; the embedded processor module and the FPGA module are connected by a bus; and the transmission is received from the upper computer by the FPGA module. Channel configuration information and receiving sampling data uploaded by the FPGA module;
    高速模拟信号采集模件包括CPLD模块和用于模数转换的AD模块,AD模块的输入端采集部署在水轮机组的各传感器输出的模拟信号;FPGA模块通过并行总线与各路高速模拟信号采集模件中的CPLD模块连接;CPLD模块连接AD模块;The high-speed analog signal acquisition module includes a CPLD module and an AD module for analog-to-digital conversion. The input of the AD module collects the analog signals output by the sensors of the turbine group; the FPGA module passes the parallel bus and each high-speed analog signal acquisition mode. The CPLD module in the piece is connected; the CPLD module is connected to the AD module;
    FPGA模块通过各路CPLD模块同时向各AD模块输出采样时序,控制各路AD模块同时采样数据,采样数据完成后,FPGA模块依次读取各路AD模块的采样数据,并将采集数据上传至嵌入式处理器模块中。The FPGA module outputs sampling timing to each AD module through each CPLD module, and controls each AD module to simultaneously sample data. After the sampling data is completed, the FPGA module sequentially reads the sampling data of each AD module, and uploads the collected data to the embedded data. In the processor module.
  2. 根据权利要求1所述的可组态的水轮机组振动摆度状态监测装置,其特征是,每路AD模块中包括两个AD单元。The configurable turbine group vibration swing state monitoring device according to claim 1, wherein each AD module comprises two AD units.
  3. 根据权利要求1所述的可组态的水轮机组振动摆度状态监测装置,其特征是,FPGA模块在其内部存储空间开辟两个用于存储采样数据的缓冲区,两个缓冲区进行乒乓操作。The configurable turbine vibration swing state monitoring device according to claim 1, wherein the FPGA module opens two buffers for storing sampling data in the internal storage space, and the two buffers perform ping-pong operation. .
  4. 根据权利要求1所述的可组态的水轮机组振动摆度状态监测装置,其特 征是,高速模拟信号采集模件的通道数量范围为1~84。The configurable turbine vibration swing state monitoring device according to claim 1, wherein The sign is that the number of channels of the high-speed analog signal acquisition module ranges from 1 to 84.
  5. 基于权利要求1至4任一项所述的监测装置的数据采集方法,其特征是,包括:The data collection method of the monitoring device according to any one of claims 1 to 4, characterized in that it comprises:
    采样时钟到来,FPGA发出采样信号SAMCLK启动采样,所有通道AD同时进行数据采集,采样结束后AD返回ADBUSY信号;When the sampling clock arrives, the FPGA sends out the sampling signal SAMCLK to start sampling, and all channels AD simultaneously perform data acquisition. After the sampling ends, the AD returns to the ADBUSY signal;
    FPGA接收到第一个通道AD的ADBUSY信号时,开始从第一个通道依次读取所有通道AD的采样值,以上传至嵌入式处理器模块;When the FPGA receives the ADBUSY signal of the first channel AD, it starts to read the sampling values of all the channels AD from the first channel in order to upload to the embedded processor module;
    下一个采样时钟到来,重复以上过程,不断进行采样。The next sampling clock arrives, repeating the above process and continuously sampling.
  6. 根据权利要求5所述的数据采集方法,其特征是,在FPGA内部开辟两个数据缓冲区,两个缓冲区进行乒乓操作。The data collection method according to claim 5, wherein two data buffers are opened inside the FPGA, and the two buffers perform ping-pong operations.
  7. 根据权利要求6所述的数据采集方法,其特征是,两个缓冲区的存储空间均按照通道数量均分,各通道每次采样的数据按照分配的地址空间顺序存储。The data collection method according to claim 6, wherein the storage spaces of the two buffers are equally divided according to the number of channels, and the data sampled by each channel is stored in the order of the allocated address space.
  8. 根据权利要求7所述的数据采集方法,其特征是,将缓冲区内一个通道的采样数据称为一个片段,缓冲区产生满标志信号的同时,保存片段序号信息;然后在读取数据时按照片段序号进行数据拼接。 The data collecting method according to claim 7, wherein the sampling data of one channel in the buffer is referred to as a segment, and the buffer generates a full flag signal while saving the segment serial number information; and then, when reading the data, The segment number is used for data splicing.
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