CN206728165U - A kind of general embedded video cap ture system - Google Patents
A kind of general embedded video cap ture system Download PDFInfo
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- CN206728165U CN206728165U CN201720570002.3U CN201720570002U CN206728165U CN 206728165 U CN206728165 U CN 206728165U CN 201720570002 U CN201720570002 U CN 201720570002U CN 206728165 U CN206728165 U CN 206728165U
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Abstract
The utility model is applied to communication technique field, there is provided a kind of general embedded video cap ture system, the system include：Video sampling module, DSP Processor, fpga logic controller and signal conversion module, video sampling module receives any one standard analog video signal in NTSC, PAL and SECAM, detect the standard of analog video signal, analog video signal is converted into yuv data, trip, field sync signal and system clock are separated simultaneously, yuv data is compressed；DSP Processor carries out image procossing by the image processing algorithm obtained in advance at computer to YUV compressed datas；Fpga logic controller synchronizes clock control according to row, field sync signal and system clock to video sampling module, DSP Processor and signal conversion module；The data that signal conversion module exports to DSP Processor carry out decompression, digital-to-analogue conversion and the output display of vision signal.The utility model has stronger versatility in the selection of analog video signal standard and image processing algorithm.
Description
Technical field
The utility model belongs to video communication technical field, more particularly to a kind of general embedded video cap ture system.
Background technology
With the high speed development of 4G, 5G technology, the video communication such as video conference, online teaching, tele-medicine, video monitoring
Increasingly extensive, in video communication system, the collection of vision signal is most important.
Time earlier, video acquisition use pure hardware design, are mainly made up of video camera, analyzer, magnetic tape station etc..It is this
Input and output of the pure hardware design to multi-channel video signal, are switched over using analog matrix, complex operation and are not easy and video
Communication system linkage, application difficult, system cost are high.
With the development of computer technology and image processing techniques, video acquisition realizes digitlization, by the video screen module of wideband
Intend signal and be converted to data signal to carry out various processing, switch to analog signal again during output.Digitized video acquisition, its
Hardware system realizes that simple, integrated level is high, and digital data transmission is reliable, processing computing is flexible.But existing various insertions
The video communication system of formula according to all kinds of video formats and encoding and decoding standard, it is necessary to specially be designed, versatility is poor.
Utility model content
The utility model embodiment provides a kind of general embedded video cap ture system, it is intended to solves existing various embedding
Enter the video communication system of formula, it is necessary to specially be designed according to all kinds of video formats and encoding and decoding standard, versatility is poor
The problem of.
The utility model is achieved in that a kind of general embedded video cap ture system, and the system includes：The system
System includes:Video sampling module, DSP Processor, fpga logic controller and signal conversion module, the DSP Processor difference
Be connected with the video sampling module and the signal conversion module, the fpga logic controller respectively with the video sampling
Module, the DSP Processor and signal conversion module connection；Wherein,
The video sampling module, for receiving luminance signal Y, the color of any one standard in NTSC, PAL and SECAM
Signal C and synchronized compound signal CVBS analog video signals are spent, the standard of analog video signal is detected, by analog video signal
The yuv data of 16 CCIR656 forms of standard is converted into, while separates trip, field sync signal and system clock, and it is right
The yuv data is compressed；
The DSP Processor, by advance at computer obtain image processing algorithm to the defeated of video sampling module
Go out YUV compressed datas and carry out image procossing, described image Processing Algorithm is general image processing algorithm or the spy voluntarily worked out
Determine image processing algorithm；
Fpga logic controller, for sent according to the video acquisition module row, field sync signal and system when
Clock synchronizes clock control to the video sampling module, the DSP Processor and the signal conversion module；
Signal conversion module, the data for being exported to the DSP Processor carry out decompression and the number of vision signal
Mould is changed, and the vision signal after logarithmic mode conversion is exported to show.
Further, the video sampling module is made up of SAA7120 chips and ADV601LC encoders, and the signal turns
Mold changing block is made up of ADV601LC decoders and ADV7175 chips.
Further, the ADV601LC encoders and the ADV601LC decoders are connected with SDRAM frame buffers,
Video data after the ADV601LC encoder compresses or ADV601LC decoders decompression is cached to the SDRAM frame buffers
In.
Further, the SDRAM frame buffers are that capacity is 8M.
Further, the DSP Processor is TMS320C6711 chips.
Further, the fpga logic controller is EP2S180 chips.
Further, the system also includes：Memory, the EMIF interfaces of the memory and the DSP Processor connect
Connect, for storing the data after the DSP Processor image procossing.
The utility model can receive any one standard simulation in NTSC, PAL and SECAM by video sampling module and regard
Frequency signal, there is versatility in the selection to analog video signal standard, will simulation letter by the detection to analog video signal
Number yuv data is converted into, while separates trip, field sync signal and system clock, and yuv data is compressed, sent
To DSP Processor, DSP Processor can pass through general image processing algorithm or the specific image voluntarily worked out Processing Algorithm pair
Data are handled, and compared to the specificity video signal image processing of solidification establishment, present processor is in image processing algorithm
There is stronger versatility, the video data after the image procossing that communicates is decompressed by signal conversion module and digital-to-analogue in selection
Conversion, with output display.
Brief description of the drawings
Fig. 1 is the structural representation for the general embedded video cap ture system that the utility model embodiment provides；
Fig. 2 is the hardware frame figure for the general embedded video cap ture system that the utility model embodiment provides；
1. video sampling module；2.DSP processors；3.FPGA logic controllers；4. signal conversion module；11.SAA7120
Chip；12.ADV601LC encoders；13.SDRAM frame buffers；21.TMS320C6711 chips；31.EP2S180 chips；
41.ADV601LC decoders；42.ADV7175 chips.
Embodiment
In order that the purpose of this utility model, technical scheme and advantage are more clearly understood, below in conjunction with accompanying drawing and implementation
Example, the utility model is further elaborated.It should be appreciated that specific embodiment described herein is only explaining
The utility model, it is not used to limit the utility model.
Fig. 1 is the structural representation for the general embedded video cap ture system that the utility model embodiment provides, in order to
It is easy to illustrate, the part related to the utility model embodiment is only shown.
The system includes：Video sampling module 1, DSP Processor 2, fpga logic controller 3 and signal conversion module 4,
DSP Processor 2 is connected with video sampling module 1, signal conversion module 4 respectively, the fpga logic controller 3 respectively with video
Sampling module 1, DSP Processor 2 and signal conversion module 4 connect；Wherein,
Video sampling module 1 receive NTSC, PAL and SECAM in any one standard luminance signal Y, carrier chrominance signal C with
And synchronized compound signal CVBS analog video signals, the standard of vision signal is detected, Y/C the and CVBS signals of simulation are changed
Into the yuv data of 16 CCIR656 forms of standard, while trip, field sync signal and system clock are separated, to YUV numbers
According to being compressed.
Fig. 2 is the hardware frame figure for the general embedded video cap ture system that the utility model embodiment provides；With reference to
Shown in Fig. 1 and Fig. 2, in preferred embodiment of the present utility model, video acquisition module 1 is by SAA7120 chips 11 and ADV601LC
Encoder 12 forms, and SAA7120 chips 11 detect the standard for completing video input signals first, then according to analog system pair
The analog-to-digital conversion mode answered carries out A/D conversions, and generates the yuv data of 16 CCIR656 forms, while it is same to separate trip, field
Signal and system clock are walked, yuv data is input to ADV601LC encoders 12, ADV601LC encoders 12 will be according to
MPEG-4 standards, using wavelet compression techniques, up to 350 are carried out to CCIR656 digital video signals:1 virtually lossless is real-time
Compression, and give the data after processing to DSP Processor 2.
In the utility model, ADV601LC encoders 12 are connected with SDRAM frame buffers 13, by ADV601LC encoders
Video data after 12 compressions is cached to SDRAM frame buffers 13, quickly, in high volume passes video data then in conjunction with passage technology
Give DSP Processor 2.For different video formats, frame buffer SDRAM size is different, for example, pal mode
Frame per second is higher, is calculated according to resolution ratio 720 × 576, image rgb format, needs the storage of 1.24M bytes empty per frame figure
Between, consider each side factors such as computational complexity, the picture format of required conversion and frame per second, we select 8MSDRAM numbers
According to frame buffer 12 of the memory 13 as ADV601LC；
In addition, SAA7120 chips 11 include 4 road analog video input channels, can be selected between analog channel, and
Anti-aliasing filter is carried out to input video, therefore the system can be equipped with 4 road cameras while work.When camera works,
SAA7120 chips 11 carry out A/D conversions to the vision signal received, Y/C the and CVBS signals of simulation are converted into standard
16 CCIR656 forms yuv data.
SAA7120 chips 11 provide I2C EBIs, main frame pass through I2C buses can initialize to the chip, with
And obtain further data processing of its working condition in order to main frame.In addition, SAA7120 chips 11 can realize the automatic of standard
Detection, selects different sample frequency and data output format, as the sample frequency of pal mode is according to different standards
13.5MHz, table 1 are sample frequency, line frequency, resolution ratio and the frame per second figure under different systems, in addition, it is important,
SAA7120 chips 11 possess copy protection function, can preferably protect the ownership copyright of the system.
Table 1 is sample frequency, line frequency, resolution ratio and the frame per second figure under different systems
| Video formats | Line frequency/kHz | Resolution ratio/pixel | Frame per second/Hz | Sample frequency/MHz |
| NTSC(SMPTE 244M) | 15.734 | 640 | 25 | 12.272 |
| NTSC(ITU-R BT.601) | 15.734 | 720 | 25 | 13.5 |
| PAL(SMPTE 244M) | 15.625 | 768 | 30 | 14.75 |
| PAL(ITU-R BT.601) | 15.625 | 720 | 30 | 13.5 |
| SECAM(SMPTE 244M) | 15.625 | 768 | 30 | 14.75 |
| SECAM(ITU-R BT.601) | 15.625 | 726 | 30 | 13.5 |
DSP Processor 2, pass through output number of the image processing algorithm of acquisition to video sampling module at computer in advance
According to image procossing is carried out, the image processing algorithm is that general image processing algorithm or the specific image voluntarily worked out processing are calculated
Method；
DSP Processor 2 can by downloading image processing algorithm from computer, such as H.26L, MPEG-4 scheduling algorithms；
Different image processing algorithms can voluntarily be worked out according to the particular application of video communication system, therefore, be compiled compared to solidification
The specificity video signal image processing of system, present processor have stronger flexibility and led in the selection of image processing algorithm
The property used；
In addition, the Mc BSP Serial Peripheral Interface (SPI)s of dsp chip 2, it is only necessary to 4 line cans complete master and slave equipment with it is each
The full duplex synchronous communication of kind peripheral components.
As preferred embodiment of the present utility model, the DSP Processor 2 is TMS320C6711 chips 21,
TMS320C6711 chips 21 coordinate the FIFO of 5120 bytes and special EDMA passages, realize that the video data of high speed is moved；Separately
Outside, display screen is easily connected to based on USB2.0 technologies using special video interface, for monitoring system or video communication
System；In addition, TMS320C6711 chips 21 have powerful disposal ability, the fortune of large amount of complex in image procossing disclosure satisfy that
Calculate and require, also meet the needs of this video acquisition system is to processor high speed performance well.
Fpga logic controller 3, for row, field sync signal and the system clock sent according to video acquisition module 1
Clock control is synchronized to video sampling module 1, DSP Processor 2 and signal conversion module 4；
Fpga logic controls 3 devices to use EP2S180 chips 31, using TSMC 90nm, low k insulation technology, than same
Class FPGA has more 82% logic unit (LE), powerful；3.3V power supplies are can be applied to, clock highest frequency is reachable
227.3M, low in energy consumption, stable performance, the speed of service are fast；In addition, using adaptive logic module (ALM), enable designer
For its products perfection performance, reduce cost.
EP2S180 chips 31 implement in the present system reset management, management of software ic, Clock management, interrupt management,
The functions such as EDMA space managements, complete the initialization of each peripheral chip, the row of SECO and completion various parts, field synchronization
Control of signal etc., in addition, in the present system, input and output I/O pins sum is probably in 45 pin or so, it is necessary to 32 grand lists
Member, EP2S180 chips 31 include 32 macroelements, conform exactly to the demand of the design.
Signal conversion module 4, the decompression of the data progress vision signal exported for DSP Processor 2, digital-to-analogue conversion,
And the video data after logarithmic mode conversion is exported to show.
Signal conversion module 4 is made up of ADV601LC encoders 41 and ADV7175 chips 42, and ADV601LC encoders 41 solve
Data after compression are sent into ADV7175 chips 42, and the composite video signal that S terminals can be directly provided by it exports, ADV601LC
Encoder 41 uses wavelet compression techniques, there is provided the process performance per component 8, CCIR656 digital video signals can be entered
Row up to 1:350 virtually lossless real-time decompression, picture quality are high, and cost is few, small volume, low in energy consumption.
In the utility model, ADV601LC encoders 41 are connected with SDRAM frame buffers 13, by ADV601LC encoders
Video data after 41 decompressions is cached to SDRAM frame buffers 13, therefore by video data is quick, high-volume transmission ADV7175 cores
Piece 42,
The utility model can receive any one standard in NTSC, PAL and SECAM by video sampling module 1 and simulate
Vision signal, there is versatility in the selection to analog video signal standard, by the detection to analog video signal, will simulate
Signal is converted into yuv data, while separates trip, field sync signal and system clock, and yuv data is compressed, hair
DSP Processor 2 is delivered to, DSP handles 2 devices and can calculated by general image processing algorithm or the specific image voluntarily worked out processing
Method is handled data, and compared to the specificity video signal image processing of solidification establishment, present processor is calculated in image procossing
There is stronger versatility, the video data after the image procossing that communicates carries out decompression number by signal conversion module in the selection of method
Mould is changed with output display.
The system has the characteristics of low-power consumption, and video acquisition system is typical embedded device, therefore the need of low-power consumption
Ask of crucial importance.The chip used in the present system is all the low-power consumption product in homologous series, such as FPGA-EP2S180 chips 31
Powered applied to 3.3V, low-voltage system make it that power dissipation ratio is relatively low, and 360mW is typically smaller than in the case of dominant frequency 100MHz；
SAA7120 chips 11 have extra small encapsulation, are typical small size, low-power consumption product under PHILIPS, work(during normal work
Consumption only has 115m W.In addition, we are designed using microminiature system, power consumption can be further reduced.For example, in order to fully press
Compression system volume, Main Processing Unit are designed using 6 laminates；Mc BSP are integrated in the interior customization of TMS320C6711 chips 21, so as to save
Save space.
The system has the characteristics of processing speed is fast, and video information process is harsher to the demand of delay, for example, ITU-
Y.1541 the time delay limit of video conference is 50ms to T in standard, and therefore, the data processing speed of video acquisition system must be sufficient
It is enough fast.Therefore, in system structure design, we use Harvard bus structures, separable programming memory and data storage, use
Special addressing unit, to accelerate execution efficiency, reduce processing delay；Secondly, ADV601LC encoders 12 can be provided per component 8
The compression disposal ability of position, the data of compression can greatly accelerate video processing speed；The clock of FPGA-EP2S180 chips 31
Frequency includes 64 macroelements, data processing speed is very fast up to 227.3M；4K words are integrated in TMS320C6711 chips 21
The level cache of section and the L2 cache of 64K bytes, are zero-waiting cycle memory, can deposit the data or fortune frequently read
The exigent program of line efficiency, greatly to play high speed performance.In addition, the system uses the sdram interface of 64, and
Coordinate the FIFO of 5120 bytes and special EDMA passages, the data exchange of high speed can be achieved and move.
The system also has copyright protection function, embedding for realizing using the memory access control apparatus with cryptoguard
Enter the cryptographic acess mechanism of formula acquisition system, the control circuit includes unified sequential logic generation and control unit, temporal aspect
Code memory, it can configure register.Be possible to sequential is brought into unified design structure by the form of condition code,
Cryptographic acess can not only be realized, and virus attack can be prevented.In addition, the SAA7120 chips 11 that we use possess counter copy
Shellfish function, it can preferably protect the ownership copyright of the system.
The system also includes：Memory 5, the memory 5 is connected with the EMIF interfaces of DSP Processor 2, for storing DSP
The data of the processing of processor 2,
In the utility model, the EMIF interfaces of DSP Processor 2 can realize DSP and different kinds of memory 5 connection,
Such as SRAM, Flash RAM, DDR-RAM etc., there is stronger versatility in hardware connection.
Preferred embodiment of the present utility model is above are only, it is all in this practicality not to limit the utility model
All any modification, equivalent and improvement made within new spirit and principle etc., should be included in guarantor of the present utility model
Within the scope of shield.
Claims (7)
1. a kind of general embedded video cap ture system, it is characterised in that the system includes:At video sampling module, DSP
Manage device, fpga logic controller and signal conversion module, the DSP Processor respectively with the video sampling module and the letter
The connection of number modular converter, the fpga logic controller respectively with the video sampling module, the DSP Processor and the letter
The connection of number modular converter；Wherein,
The video sampling module, for receiving luminance signal Y, the colourity letter of any one standard in NTSC, PAL and SECAM
Number C and synchronized compound signal CVBS analog video signals, detect the standard of analog video signal, analog video signal are changed
Into the yuv data of 16 CCIR656 forms of standard, while trip, field sync signal and system clock are separated, and to described
Yuv data is compressed；
The DSP Processor, by advance at computer obtain image processing algorithm to the defeated of the video sampling module
Go out YUV compressed datas and carry out image procossing, described image Processing Algorithm is general image processing algorithm or the spy voluntarily worked out
Determine image processing algorithm；
The fpga logic controller, for sent according to the video sampling module row, field sync signal and system when
Clock synchronizes clock control to the video sampling module, the DSP Processor and the signal conversion module；
The signal conversion module, the data for being exported to the DSP Processor carry out the decompression of vision signal, digital-to-analogue turns
Change, and the vision signal after logarithmic mode conversion is exported to show.
2. general embedded video cap ture system as claimed in claim 1, it is characterised in that the video sampling module by
SAA7120 chips and ADV601LC encoders composition, the signal conversion module is by ADV601LC decoders and ADV7175 chips
Composition.
3. general embedded video cap ture system as claimed in claim 2, it is characterised in that the ADV601LC encoders
It is after the ADV601LC encoder compresses or described and the ADV601LC decoders are connected with SDRAM frame buffers
Video data after ADV601LC decoders decompression is cached in the SDRAM frame buffers.
4. general embedded video cap ture system as claimed in claim 3, it is characterised in that the SDRAM frame buffers
It is 8M for capacity.
5. general embedded video cap ture system as claimed in claim 1, it is characterised in that the DSP Processor is
TMS320C6711 chips.
6. general embedded video cap ture system as claimed in claim 1, it is characterised in that the fpga logic controller
For EP2S180 chips.
7. general embedded video cap ture system as claimed in claim 1, it is characterised in that the system also includes：Deposit
Reservoir, the memory are connected with the EMIF interfaces of the DSP Processor, after storing the DSP Processor image procossing
Data.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109656871A (en) * | 2018-12-11 | 2019-04-19 | 中北大学 | A kind of four-way noise signal lossless compression device |
| CN112351153A (en) * | 2020-09-30 | 2021-02-09 | 济南浪潮高新科技投资发展有限公司 | Analog camera system, processing method and processing equipment |
| CN112584092A (en) * | 2019-09-30 | 2021-03-30 | 广州汽车集团股份有限公司 | Data acquisition device and data acquisition system |
| CN116506560A (en) * | 2023-06-27 | 2023-07-28 | 天津开发区中环***电子工程股份有限公司 | Video image real-time acquisition system and acquisition method |
-
2017
- 2017-05-22 CN CN201720570002.3U patent/CN206728165U/en not_active Expired - Fee Related
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109656871A (en) * | 2018-12-11 | 2019-04-19 | 中北大学 | A kind of four-way noise signal lossless compression device |
| CN112584092A (en) * | 2019-09-30 | 2021-03-30 | 广州汽车集团股份有限公司 | Data acquisition device and data acquisition system |
| CN112584092B (en) * | 2019-09-30 | 2024-05-03 | 广州汽车集团股份有限公司 | Data acquisition device and data acquisition system |
| CN112351153A (en) * | 2020-09-30 | 2021-02-09 | 济南浪潮高新科技投资发展有限公司 | Analog camera system, processing method and processing equipment |
| CN116506560A (en) * | 2023-06-27 | 2023-07-28 | 天津开发区中环***电子工程股份有限公司 | Video image real-time acquisition system and acquisition method |
| CN116506560B (en) * | 2023-06-27 | 2023-09-29 | 天津开发区中环***电子工程股份有限公司 | Video image real-time acquisition system and acquisition method |
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