CN109638069B - 半导体装置 - Google Patents

半导体装置 Download PDF

Info

Publication number
CN109638069B
CN109638069B CN201811009205.0A CN201811009205A CN109638069B CN 109638069 B CN109638069 B CN 109638069B CN 201811009205 A CN201811009205 A CN 201811009205A CN 109638069 B CN109638069 B CN 109638069B
Authority
CN
China
Prior art keywords
semiconductor
trench
layer
region
gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201811009205.0A
Other languages
English (en)
Other versions
CN109638069A (zh
Inventor
小林勇介
原田信介
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Publication of CN109638069A publication Critical patent/CN109638069A/zh
Application granted granted Critical
Publication of CN109638069B publication Critical patent/CN109638069B/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7803—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device
    • H01L29/7806—Vertical DMOS transistors, i.e. VDMOS transistors structurally associated with at least one other device the other device being a Schottky barrier diode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic Table
    • H01L29/1608—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02378—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02529—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02634—Homoepitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/0455—Making n or p doped regions or layers, e.g. using diffusion
    • H01L21/046—Making n or p doped regions or layers, e.g. using diffusion using ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/0475—Changing the shape of the semiconductor body, e.g. forming recesses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/0445—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising crystalline silicon carbide
    • H01L21/048—Making electrodes
    • H01L21/049—Conductor-insulator-semiconductor electrodes, e.g. MIS contacts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0882—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42356—Disposition, e.g. buried gate electrode
    • H01L29/4236—Disposition, e.g. buried gate electrode within a trench, e.g. trench gate electrode, groove gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4916—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66053—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide
    • H01L29/66068—Multistep manufacturing processes of devices having a semiconductor body comprising crystalline silicon carbide the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0856—Source regions
    • H01L29/0865—Disposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0856—Source regions
    • H01L29/0869—Shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

本发明提供能够降低导通电阻的半导体装置。在栅极沟槽(7)的底面设有导电层(22)。由该导电层(22)和n型电流扩散区(3)沿栅极沟槽(7)的侧壁形成肖特基结(23)，并由该肖特基结(23)构成沟槽型SBD(42)的1个单位单元。在栅极沟槽(7)的内部，在导电层(22)上隔着绝缘层(8a)设有构成沟槽栅型的纵向型MOSFET(41)的1个单位单元的栅电极(9)。即，沟槽栅型MOSFET(41)的1个单位单元和沟槽型SBD(42)的1个单位单元被配置在1个栅极沟槽(7)的内部并且在深度方向上对置。

Description

半导体装置
技术领域
本发明涉及半导体装置。
背景技术
以往，在使用带隙比硅宽的半导体(以下，记作宽带隙半导体)的功率半导体装置中，谋求低导通电阻化。例如，在纵向型MOSFET(Metal Oxide Semiconductor FieldEffect Transistor：绝缘栅型场效应晶体管)中，采用与在半导体芯片的正面上以平板状设置MOS栅的平面栅结构相比，在结构上容易获得低导通电阻特性的沟槽栅结构。沟槽栅结构是在形成于半导体芯片的正面的沟槽内埋入MOS栅的MOS栅结构，可以通过单元间距的缩短来进行低导通电阻化。
关于现有的沟槽栅型MOSFET，以使用碳化硅(SiC)作为宽带隙半导体的情况为例进行说明。图12是表示现有的半导体装置的结构的截面图。图12所示的沟槽栅型MOSFET是使用在由碳化硅构成的n+型支撑基板(以下，记作n+型碳化硅基板)101上按顺序外延生长成为n-型漂移区102和p型基区104的各碳化硅层而成的由碳化硅构成的半导体基板(以下，记作碳化硅基板)110而制成。在从碳化硅基板110的正面起算在漏极侧比沟槽(以下，记作栅极沟槽)107的底面更深的位置选择性地设置有第一p+型区121、第二p+型区122。
第一p+型区121包覆栅极沟槽107的底面。第二p+型区122在相邻的栅极沟槽107之间(台面区)以与栅极沟槽107分开的方式选择性地设置。通过设置这些第一p+型区121、第二p+型区122，从而抑制在关断时施加到栅极绝缘膜的电场。因此，能够在维持耐压(耐电压)的状态下，缩短单元间距而进行低导通电阻化。由1个栅极沟槽107内的MOS栅和隔着该MOS栅而相邻的台面区构成1个单位单元(元件的构成单位)。符号103、105、106、108、109、111～113分别表示n型电流扩散区、n+型源区、p++型接触区、栅极绝缘膜、栅电极、层间绝缘膜、源电极和漏电极。
以往，已知为了减少部件个数而实现降低成本，使用形成于沟槽栅型MOSFET的内部的寄生二极管(体二极管)来代替外部的肖特基势垒二极管(SBD：Schottky BarrierDiode)。但是，在使用沟槽栅型MOSFET的体二极管来代替外部的SBD的情况下，会产生体二极管的劣化、导通损耗增加。为了避免该问题，提出了在制作有沟槽栅型MOSFET的同一半导体芯片内置沟槽型SBD的方案。
对在同一半导体芯片内置了沟槽型SBD的现有的沟槽栅型MOSFET进行说明。图13是表示现有的半导体装置的结构的另一例的截面图。图13所示的现有的半导体装置与图12所示的现有的半导体装置的不同之处在于，在沟槽栅型MOSFET131的相邻的栅极沟槽107间内置有沟槽型SBD132。
沟槽型SBD132具备栅极沟槽107之间的沟槽141和埋入到该沟槽141的内部的导电层142，并由沿沟槽141的侧壁形成的导电层142与n型电流扩散区103的肖特基结143构成。沟槽141的底面被第一p+型区121包覆。不设置第二p+型区。
作为在同一半导体芯片内置了沟槽型SBD的沟槽栅型MOSFET，提出了在用于源接触的沟槽的底面形成了势垒金属与p-型基区的肖特基结的装置(例如，参照下述专利文献1(第0031～0032段、图1)。)。在下述专利文献1中，将从源电极起经由势垒金属、p-型基区、n-型沟道区、n型漂移区、n+型基板而到达漏电极的路径设为肖特基势垒二极管，改善内置二极管的反向恢复特性。
另外，作为在同一半导体芯片内置了沟槽型SBD的另一沟槽栅型MOSFET，提出了在比栅极沟槽深的沟槽埋入肖特基电极而在与半导体基板之间形成肖特基结的装置(参照下述专利文献2(第0070～0071段，图9)。)。在下述专利文献2中，将埋入了肖特基电极的沟槽之间的半导体部设计成因从肖特基电极延伸的耗尽层而以低的施加电压夹断的区域，防止显著超过夹断时的电场的电场施加于栅极沟槽底面。
现有技术文献
专利文献
专利文献1：日本特开2011-009387号公报
专利文献2：日本特开2010-259278号公报
发明内容
技术问题
但是，如上所述，在内置了沟槽型SBD132的现有的沟槽栅型MOSFET131(参照图13)中，在相邻的栅极沟槽107之间配置沟槽型SBD132。因此，存在难以缩短单元间距(相邻的栅极沟槽107之间的距离)，无法实现低导通电阻化的问题。
为了消除上述的现有技术的问题，本发明的目的在于提供能够降低导通电阻的半导体装置。
技术方案
为了解决上述课题，实现本发明的目的，本发明的半导体装置具有如下特征。在由带隙比硅宽的半导体构成的半导体基板的正面设有由带隙比硅宽的半导体构成的第一导电型的第一半导体层。在所述第一半导体层的、相对于所述半导体基板侧为相反的一侧设有由带隙比硅宽的半导体构成的第二导电型的第二半导体层。在所述第二半导体层的内部选择性地设有第一导电型的第一半导体区。沟槽贯通所述第一半导体区和所述第二半导体层而到达所述第一半导体层。在所述第一半导体层的内部以与所述第二半导体层分开的方式选择性地设有第二半导体区。所述第二半导体区包覆所述沟槽的底面。导电层设置在所述沟槽的内部。绝缘层在所述沟槽的内部设置在所述导电层上。绝缘膜沿所述沟槽的侧壁设置，且与所述绝缘层接触而与该绝缘层连续。栅电极在所述沟槽的内部设置在所述绝缘层和所述绝缘膜之上。第一电极与所述第二半导体层和所述第一半导体区接触。第二电极设置在所述半导体基板的背面。肖特基势垒二极管由所述导电层与所述第一半导体层的肖特基结构成。
另外，本发明的半导体装置的特征在于，在上述发明中，所述导电层和所述绝缘层之间的界面位于比所述第二半导体层和所述第一半导体层之间的界面更靠所述半导体基板侧的位置。
另外，本发明的半导体装置的特征在于，在上述发明中，从所述导电层和所述绝缘层之间的界面起到所述第二半导体层和所述第一半导体层之间的界面为止的距离为0.3μm以上且0.6μm以下。
另外，本发明的半导体装置的特征在于，在上述发明中，所述沟槽的深度为1.1μm以上且3.2μm以下，所述导电层的厚度为0.1μm以上且0.6μm以下。
另外，本发明的半导体装置的特征在于，在上述发明中，所述半导体装置还具备第一导电型的第三半导体区，该第一导电型的第三半导体区与所述第二半导体层接触，并且以从所述第一半导体层和所述第二半导体层之间的界面起到达在所述第二电极侧比所述沟槽的底面更深的位置的方式设置在所述第一半导体层的内部，所述第三半导体区的杂质浓度比所述第一半导体层的杂质浓度高。所述肖特基势垒二极管由所述导电层与所述第三半导体区的肖特基结构成。
另外，本发明的半导体装置的特征在于，在上述发明中，所述沟槽被配置为沿与所述半导体基板的正面平行的方向延伸的条纹状的布局。
根据上述发明，无需像现有结构(参照图13)那样在相邻的栅极沟槽间设置沟槽型SBD。因此，即使将沟槽型SBD与沟槽栅型的MOS型半导体装置内置在同一半导体芯片，也能够缩短单元间距(相邻的栅极沟槽间的距离)。
发明效果
根据本发明的半导体装置，具有能够通过缩短单元间距来降低导通电阻的效果。
附图说明
图1是表示实施方式的半导体装置的结构的截面图。
图2是表示实施方式的半导体装置的制造过程中的状态的截面图。
图3是表示实施方式的半导体装置的制造过程中的状态的截面图。
图4是表示实施方式的半导体装置的制造过程中的状态的截面图。
图5是表示实施方式的半导体装置的制造过程中的状态的截面图。
图6是表示实施方式的半导体装置的制造过程中的状态的截面图。
图7是表示实施方式的半导体装置的制造过程中的状态的截面图。
图8是表示实施方式的半导体装置的制造过程中的状态的截面图。
图9是表示实施方式的半导体装置的制造过程中的状态的截面图。
图10是表示实施方式的半导体装置的制造过程中的状态的截面图。
图11是表示实施方式的半导体装置的制造过程中的状态的截面图。
图12是表示现有的半导体装置的结构的截面图。
图13是表示现有的半导体装置的结构的另一例的截面图。
符号说明
1：n+型碳化硅基板
2：n-型漂移区
3：n型电流扩散区
3a、3b：n型部分区域
4：p型基区
5：n+型源区
5a、5b：n+型区
6：p++型接触区
7：栅极沟槽
8：栅极绝缘膜
8a：绝缘层
8b：绝缘膜
9：栅电极
10：半导体基板(半导体芯片)
11：层间绝缘膜
11a：接触孔
12a：源电极
12b：源电极焊盘
13：漏电极
21：p+型区
22：导电层
23：肖特基结
31：n-型碳化硅层
31a：增加n-型碳化硅层的厚度的部分
32：p型碳化硅层
41：沟槽栅型MOSFET
42：沟槽型SBD
d：栅极沟槽的深度
t1：绝缘层的厚度
t2：绝缘膜的厚度
t11：导电层的厚度
x1：从导电层和绝缘层之间的界面起到栅极沟槽的底面为止的距离
x2：从p型基区和n型电流扩散区之间的界面起到导电层和绝缘层之间的界面为止的距离
x3：从第二n+型区的漏极侧端部起到p型基区和n型电流扩散区之间的界面为止的距离
x4：从栅电极的源极侧端部起到第二n+型区的漏极侧端部为止的距离
x5：从层间绝缘膜的源极侧端部起到栅电极的源极侧端部为止的距离
具体实施方式
以下参照附图，对本发明的半导体装置的优选实施方式进行详细地说明。在本说明书和附图中，在前缀有n或p的层和区域中，分别表示电子或者空穴为多数载流子。另外，标记于n或p的+和-分别表示杂质浓度比未标记+和-的层或区域的杂质浓度高和低。应予说明，在以下的实施方式的说明和附图中，对同样的结构标记相同的符号，并省略重复的说明。
(实施方式)
实施方式所涉及的半导体装置使用带隙比硅宽的半导体(记为宽带隙半导体)而构成。对于该实施方式的半导体装置的结构，以使用例如碳化硅(SiC)作为宽带隙半导体的情况为例进行说明。图1是表示实施方式的半导体装置的结构的截面图。在图1中，表示沟槽栅型MOSFET41的1个单位单元(元件的构成单位)和在该单位单元的两侧邻接的单位单元的1/2。另外，图1中仅图示配置在有源区的一部分单位单元，并省略图示包围有源区的周围的边缘终止区(在图2～图11中也同样)。
有源区是指在半导体装置为导通状态时有电流流通的区域。边缘终止区是有源区与半导体基板(半导体芯片)10的侧面之间的区域，是缓和n-型漂移区2的基板正面(半导体基板10的正面)侧的电场而保持耐压(耐电压)的区域。在边缘终止区配置例如构成保护环、结终止(JTE：Junction Termination Extension)结构的p型区、场板、和/或降低表面电场等的耐压结构。耐压是指不引起半导体装置的误动作或损坏的极限电压。
图1所示的实施方式的半导体装置是在由碳化硅构成的同一半导体基板(碳化硅基板)10内置了沟槽型SBD42的沟槽栅型MOSFET41。半导体基板10是在由碳化硅构成的n+型支撑基板(n+型碳化硅基板)1上按顺序外延生长成为n-型漂移区2和p型基区4的各碳化硅层(第一半导体层、第二半导体层)31、32而成的外延基板。沟槽栅型MOSFET的MOS栅由设置在基板正面侧的p型基区4、n+型源区(第一半导体区)5、p++型接触区6、栅极沟槽7、栅极绝缘膜8和栅电极9构成。
具体地，在n-型碳化硅层31的源极侧(源电极12a侧)的表面层以与p型碳化硅层32(p型基区4)接触的方式设有n型区(以下，记作n型电流扩散区(第三半导体区))3。n型电流扩散区3是使载流子的扩散电阻降低的所谓的电流扩散层(Current Spreading Layer：CSL)。该n型电流扩散区3例如以包覆栅极沟槽7的内壁的方式在平行于基板正面的方向上均匀地设置。n型电流扩散区3从n型电流扩散区3与p型基区4的界面起到达在漏极侧(漏电极13侧)比栅极沟槽7的底面更深的位置。
n-型碳化硅层31的、除n型电流扩散区3以外的部分为n-型漂移区2。即，n型电流扩散区3在n-型漂移区2和p型基区4之间，以与栅极沟槽7的内壁、n-型漂移区2和p型基区4接触的方式设置。在n型电流扩散区3的内部以包覆栅极沟槽7的底面的方式选择性地设有p+型区(第二半导体区)21。
p+型区21以与p型基区4分开的方式配置在漏极侧比p型基区4和n型电流扩散区3之间的界面更深的位置。p+型区21具有在沟槽栅型MOSFET41关断时进行耗尽化，缓和施加到后述的导电层22的沿栅极沟槽7的内壁的部分的电场的功能。p+型区21可以从栅极沟槽7的底面遍及底面角部而包覆栅极沟槽7的底面和底面角部整体。栅极沟槽7的底面角部是指栅极沟槽7的底面与侧壁之间的边界。
p+型区21的漏极侧端部可以在n型电流扩散区3的内部终止，也可以到达n型电流扩散区3与n-型漂移区2之间的界面，还可以在n-型漂移区2的内部终止。即，只要将p+型区21与n型电流扩散区3(或者n-型漂移区2)的pn结设于漏极侧比栅极沟槽7的底面更深的位置即可，第一p+型区21的深度可以进行各种变更。
在p型碳化硅层32的内部，在相邻的栅极沟槽7之间(台面区)分别选择性地设置有n+型源区5和p++型接触区6。n+型源区5例如由第一n+型区5a和设置于从基板正面起算比该第一n+型区5a更深的位置的第二n+型区5b构成。第一n+型区5a和第二n+型区5b彼此接触。第一n+型区5a的杂质浓度可以比第二n+型区5b的杂质浓度高。也可以不设置第二n+型区5b。p++型接触区6与第一n+型区5a接触。p++型接触区6的深度例如比第一n+型区5a深。
栅极沟槽7从半导体基板10的正面(p型碳化硅层32的表面)起在深度方向上贯通n+型源区5(第一n+型区5a、第二n+型区5b)和p型基区4而到达n型电流扩散区3，并在p+型区21的内部终止。深度方向是指从半导体基板10的正面朝向背面的方向。栅极沟槽7的深度d例如可以是1.1μm以上且3.2μm以下左右。另外，栅极沟槽7从半导体基板10的正面侧观察，例如被配置为沿与半导体基板10的正面平行的方向(图1的进深方向)延伸的条纹状的布局。
在栅极沟槽7的内部，在栅极沟槽7的最靠底面侧埋入有例如金属层和/或多晶硅(poly-Si)层等导电层22。导电层22在省略图示的部分中被引出到半导体基板10的正面，与后述的源电极焊盘12b电连接。导电层22和绝缘层8a之间的界面位于在漏极侧比p型基区4和n型电流扩散区3之间的界面更深的位置，导电层22在栅极沟槽7的侧壁与n型电流扩散区3接触。由该导电层22和n型电流扩散区3沿栅极沟槽7的侧壁形成肖特基结23。
即，由沿1个栅极沟槽7的侧壁形成的肖特基结23构成沟槽型SBD42的1个单位单元。沟槽型SBD42的各单位单元沿栅极沟槽7以条纹状延伸的方向延伸。沟槽型SBD42的单位单元的面积(肖特基结23的表面积)能够通过栅极沟槽7的深度d和栅极沟槽7以条纹状延伸的长度(从半导体基板10的正面侧观察为栅极沟槽7的长边方向的长度)进行调整。沟槽型SBD42具有防止形成于沟槽栅型MOSFET41的内部的寄生二极管(体二极管)的劣化的功能。
另外，在栅极沟槽7的内部，在导电层22上设有绝缘层8a，在该绝缘层8a上埋入有沟槽栅型MOSFET41的1个单位单元的MOS栅。即，在1个栅极沟槽7的内部配置有沟槽栅型MOSFET41的1个单位单元和沟槽型SBD42的1个单位单元，且隔着绝缘层8a在深度方向上对置。在1个栅极沟槽7内实现MOSFET的功能和SBD的功能。
沟槽栅型MOSFET的MOS栅由栅极绝缘膜8和栅电极9构成。栅极绝缘膜8由导电层22上的绝缘层8a和绝缘膜8b构成，该绝缘膜8b沿栅极沟槽7的侧壁设置且与绝缘层8a接触而与该绝缘层8a连续。绝缘层8a的厚度t1大于绝缘膜8b的厚度t2。栅电极9在栅极沟槽7的内部设置在栅极绝缘膜8(绝缘层8a和绝缘膜8b)上。栅电极9利用绝缘层8a和绝缘膜8b与导电层22电绝缘。
另外，栅电极9在栅极沟槽7的侧壁隔着绝缘膜8b与第二n+型区5b(或者第一n+型区5a和第二n+型区5b)对置。栅电极9的漏极侧端部达到在漏极侧比p型基区4和n型电流扩散区3之间的界面更深的位置。层间绝缘膜11覆盖埋入到栅极沟槽7的栅电极9。层间绝缘膜11在栅极沟槽7的内部可以设置在栅电极9上。
栅电极9在省略图示的部分中被引出到半导体基板10的正面，与栅电极焊盘(未图示)电连接。源电极12a通过在层间绝缘膜11开口而成的接触孔与n+型源区5(第一n+型区5a)和p++型接触区6接触，并与这些区域电连接。
另外，源电极12a通过层间绝缘膜11与栅电极9电绝缘。源电极12a与设置在源电极12a和层间绝缘膜11上的源电极焊盘12b电连接。在半导体基板10的背面(成为n+型漏区的n+型碳化硅基板1的背面)设有漏电极13。
虽然不特别地限定，但例如实施方式的半导体装置的各部分的尺寸取如下值。从导电层22和绝缘层8a之间的界面起到栅极沟槽7的底面为止的距离(导电层22的厚度)x1为0.1μm以上且0.6μm以下左右。从p型基区4和n型电流扩散区3之间的界面起到导电层22和绝缘层8a之间的界面为止的距离x2为0.3μm以上且0.6μm以下左右。从第二n+型区5b的漏极侧端部起到p型基区4和n型电流扩散区3之间的界面为止的距离x3为0.1μm以上且1.0μm以下左右。从栅电极9的源极侧端部起到第二n+型区5b的漏极侧端部为止的距离x4为0.3μm以上且0.5μm以下左右。从层间绝缘膜11的源极侧端部起到栅电极9的源极侧端部为止的距离x5为0.3μm以上且0.6μm以下左右。
接着，对实施方式的半导体装置的动作进行说明。构成沟槽型SBD42的导电层22在栅极沟槽7的底面和底面角部被p+型区21包覆。因此，在沟槽栅型MOSFET41关断时，耗尽层从p+型区21与n型电流扩散区3(或者根据n型电流扩散区3的深度为n-型漂移区2)的pn结扩展到p+型区21的内部。由此，使施加到导电层22的、沿栅极沟槽7的内壁的部分的电场缓和，因此能够降低泄漏电流。即，由p+型区21与n型电流扩散区3的pn结的深度位置和/或p+型区21和n型电流扩散区3的杂质浓度来确定耐压。
另外，在沟槽栅型MOSFET41的p型基区4与n型电流扩散区3的pn结处形成的寄生pn二极管正向偏压时，沟槽型SBD42以比沟槽栅型MOSFET41的上述寄生pn二极管低的电压，比该寄生pn二极管提前导通。因此，在由沟槽栅型MOSFET41的n型电流扩散区3、p型基区4和n+型源区5构成的纵向型的寄生npn双极型晶体管(体二极管)中不流通基极电流，该寄生npn双极型晶体管不动作。因此，不会产生因该寄生npn双极型晶体管引起的正向劣化。并且，能够降低因该寄生npn双极型晶体管引起的导通损耗。
接着，对实施方式的半导体装置的制造方法进行说明。图2～图11是表示实施方式的半导体装置的制造过程中的状态的截面图。首先，如图2所示，准备成为n+型漏区的n+型碳化硅基板1。接着，在n+型碳化硅基板1的正面外延生长n-型碳化硅层31。接着，通过光刻和p型杂质的离子注入，在n-型碳化硅层31的表面层选择性地形成p+型区21。
接着，通过光刻和n型杂质的离子注入，例如遍及整个有源区，在n-型碳化硅层31的表面层形成n型区(以下，记作n型部分区域)3a。该n型部分区域3a是n型电流扩散区3的一部分。n型部分区域3a的深度可以进行各种变更。在图2中表示将n型部分区域3a的深度设置得比p+型区21深并且利用n型部分区域3a包覆p+型区21的整个漏极侧(n+型碳化硅基板1侧)的情况(在图3～图11中也同样)。n-型碳化硅层31的、比n型部分区域3a更靠近漏极侧的部分成为n-型漂移区2。也可以更换n型部分区域3a和p+型区21的形成顺序。
接着，如图3所示，在n-型碳化硅层31上进一步外延生长n-型碳化硅层，增加n-型碳化硅层31的厚度。接着，通过光刻和n型杂质的离子注入，例如遍及整个有源区，在增加n-型碳化硅层31的厚度的部分31a以到达n型部分区域3a的深度形成n型部分区域3b。n型部分区域3b的杂质浓度与n型部分区域3a的杂质浓度大致相同。n型部分区域3a、3b在深度方向上连结，由此形成n型电流扩散区3。在增加n-型碳化硅层31的厚度时，可以使与n型电流扩散区3相同杂质浓度的n型碳化硅层外延生长来作为n型部分区域3b。
接着，如图4所示，在n-型碳化硅层31上外延生长p型碳化硅层32。由此，形成在n+型碳化硅基板1上按顺序沉积有n-型碳化硅层31和p型碳化硅层32的碳化硅基板(半导体晶片)10。接着，如图5所示，在不同的条件下反复进行将光刻和离子注入作为一组的工序，在p型碳化硅层32的表面层分别选择性地形成第一n+型区5a、第二n+型区5b(n+型源区5)和p++型接触区6。并且，对通过离子注入形成的全部区域进行用于使杂质活化的热处理(活化退火)。
在用于形成第一n+型区5a的离子注入中，作为掺杂剂使用例如磷(P)或者砷(As)，形成杂质浓度比第二n+型区5b高的第一n+型区5a。在用于形成第二n+型区5b的离子注入中，作为掺杂剂使用例如氮(N)，形成比第一n+型区5a深的第二n+型区5b。可以对第一n+型区5a、第二n+型区5b和p++型接触区6的形成顺序进行各种更换。p型碳化硅层32的、除第一n+型区5a、第二n+型区5b和p++型接触区6以外的部分成为p型基区4。
接着，如图6所示，形成贯通第一n+型区5a、第二n+型区5b和p型基区4而到达n型电流扩散区3的内部的第一p+型区21的栅极沟槽7。接着，如图7所示，利用例如沉积法，以埋入到栅极沟槽7的内部的方式在半导体基板10的正面沉积例如金属层、多晶硅(poly-Si)层等导电层22。接着，如图8所示，对导电层22进行蚀刻，仅在栅极沟槽7的内部的底面侧以规定的厚度t11保留导电层22。导电层22的厚度t11设为与上述的从导电层22和绝缘层8a之间的界面起到栅极沟槽7的底面为止的距离x1相同的尺寸。
接着，如图9所示，利用例如沉积法，以埋入到栅极沟槽7的内部的方式，在半导体基板10的正面沉积绝缘层8a。接着，对绝缘层8a进行蚀刻，仅在栅极沟槽7的内部以规定的厚度t1保留绝缘层8a。接着，如图10所示，对半导体基板10的正面和栅极沟槽7的侧壁进行热氧化，形成沿着半导体基板10的正面和栅极沟槽7的侧壁并且与绝缘层8a接触而连续的绝缘膜8b。由此，在栅极沟槽7的内部形成由绝缘层8a和绝缘膜8b构成的栅极绝缘膜8。
接着，利用例如沉积法，以埋入到栅极沟槽7的内部的方式在半导体基板10的正面沉积例如多晶硅层。接着，对该多晶硅层进行蚀刻，仅在栅极沟槽7的内部保留成为栅电极9的多晶硅层。接着，如图11所示，利用例如沉积法，以埋入到栅极沟槽7的内部的方式，在半导体基板10的正面形成层间绝缘膜11。接着，对层间绝缘膜11和绝缘膜8b进行蚀刻，仅在栅极沟槽7的内部保留层间绝缘膜11和绝缘膜8b。由此，在相邻的栅极沟槽7之间，使半导体基板10的正面露出。
半导体基板10的正面的、未被层间绝缘膜11覆盖的部分为用于形成源电极12a与硅部(第一n+型区5a和p++型接触区6)的电接触部的接触孔11a。接着，利用通常的方法，形成与第一n+型区5a和p++型接触区6进行欧姆接触的源电极12a。形成与源电极12a接触的源电极焊盘12b。在半导体基板10的背面形成漏电极13。之后，对半导体晶片进行切割(切断)而分割成一个一个的芯片状，由此完成图1所示的MOSFET。
如上所述，根据实施方式，在1个沟槽的内部配置沟槽栅型MOSFET的1个单位单元和沟槽型SBD的1个单位单元，在1个栅极沟槽内实现MOSFET的功能和SBD的功能。即，无需像现有结构(参照图13)那样在相邻的栅极沟槽间设置沟槽型SBD。因此，即使将沟槽型SBD与沟槽栅型MOSFET内置在同一半导体芯片，也能够缩短单元间距(相邻的栅极沟槽间的距离)。因此，能够通过缩短单元间距来降低导通电阻。
另外，根据实施方式，由于将沟槽型SBD与沟槽栅型MOSFET内置在同一半导体芯片，因此能够避免形成于沟槽栅型MOSFET的内部的寄生二极管(体二极管)的劣化和/或导通损耗增加。
以上，本发明能够在不脱离本发明的主旨的范围内进行各种变更，在上述的各实施方式中，例如各部分的尺寸和/或杂质浓度等可根据要求的规格等进行各种设定。另外，在上述的实施方式中，以使用在碳化硅基板外延生长碳化硅层而成的外延基板的情况为例进行了说明，但也可以利用例如离子注入等在碳化硅基板形成构成本发明的半导体装置的各区域。另外，本发明也能够适用于碳化硅以外的宽带隙半导体(例如镓(Ga)等)。另外，本发明即使使导电型(n型、p型)反转也同样成立。
工业上的利用可能性
如上所述，本发明的半导体装置对沟槽栅结构的MOS型半导体装置有用。

Claims (5)

1.一种半导体装置，其特征在于，具备：
半导体基板，其由带隙比硅宽的半导体构成；
第一导电型的第一半导体层，其设置在所述半导体基板的正面，且由带隙比硅宽的半导体构成；
第二导电型的第二半导体层，其设置在所述第一半导体层的、相对于所述半导体基板侧为相反的一侧，且由带隙比硅宽的半导体构成；
第一导电型的第一半导体区，其选择性地设置在所述第二半导体层的内部；
沟槽，其贯通所述第一半导体区和所述第二半导体层而到达所述第一半导体层；
第二半导体区，其以与所述第二半导体层分开的方式选择性地设置在所述第一半导体层的内部，并包覆所述沟槽的底面；
导电层，其设置在所述沟槽的内部；
绝缘层，其在所述沟槽的内部，设置在所述导电层上；
绝缘膜，其沿所述沟槽的侧壁设置，且与所述绝缘层接触而与该绝缘层连续；
栅电极，其在所述沟槽的内部，设置在所述绝缘层和所述绝缘膜之上；
第一电极，其与所述第二半导体层和所述第一半导体区接触；
第二电极，其设置在所述半导体基板的背面；以及
肖特基势垒二极管，其由所述导电层与所述第一半导体层的肖特基结构成，
所述绝缘层的厚度比所述绝缘膜的厚度厚，
从所述导电层和所述绝缘层之间的界面起到所述第二半导体层和所述第一半导体层之间的界面为止的距离为0.3μm以上且0.6μm以下。
2.根据权利要求1记载的半导体装置，其特征在于，所述导电层和所述绝缘层之间的界面位于比所述第二半导体层和所述第一半导体层之间的界面更靠所述半导体基板侧的位置。
3.根据权利要求1或2记载的半导体装置，其特征在于，所述沟槽的深度为1.1μm以上且3.2μm以下，
所述导电层的厚度为0.1μm以上且0.6μm以下。
4.根据权利要求1～3中任意一项记载的半导体装置，其特征在于，所述半导体装置还具备第一导电型的第三半导体区，该第一导电型的第三半导体区与所述第二半导体层接触，并且以从所述第一半导体层和所述第二半导体层之间的界面起到达在所述第二电极侧比所述沟槽的底面更深的位置的方式设置在所述第一半导体层的内部，所述第三半导体区的杂质浓度比所述第一半导体层的杂质浓度高，
所述肖特基势垒二极管由所述导电层与所述第三半导体区的肖特基结构成。
5.根据权利要求1～4中任意一项记载的半导体装置，其特征在于，所述沟槽被配置为沿与所述半导体基板的正面平行的方向延伸的条纹状的布局。
CN201811009205.0A 2017-10-05 2018-08-31 半导体装置 Active CN109638069B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2017-195480 2017-10-05
JP2017195480A JP7059555B2 (ja) 2017-10-05 2017-10-05 半導体装置

Publications (2)

Publication Number Publication Date
CN109638069A CN109638069A (zh) 2019-04-16
CN109638069B true CN109638069B (zh) 2023-10-24

Family

ID=65817128

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201811009205.0A Active CN109638069B (zh) 2017-10-05 2018-08-31 半导体装置

Country Status (4)

Country Link
US (1) US10546950B2 (zh)
JP (1) JP7059555B2 (zh)
CN (1) CN109638069B (zh)
DE (1) DE102018214901A1 (zh)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102014117780B4 (de) 2014-12-03 2018-06-21 Infineon Technologies Ag Halbleiterbauelement mit einer Grabenelektrode und Verfahren zur Herstellung
DE102014119465B3 (de) 2014-12-22 2016-05-25 Infineon Technologies Ag Halbleitervorrichtung mit streifenförmigen trenchgatestrukturen, transistormesas und diodenmesas
JP6950290B2 (ja) * 2017-06-09 2021-10-13 富士電機株式会社 半導体装置および半導体装置の製造方法
DE102018103973B4 (de) 2018-02-22 2020-12-03 Infineon Technologies Ag Siliziumcarbid-halbleiterbauelement
DE102019111308A1 (de) 2018-05-07 2019-11-07 Infineon Technologies Ag Siliziumcarbid halbleiterbauelement
DE102018124740A1 (de) * 2018-10-08 2020-04-09 Infineon Technologies Ag Halbleiterbauelement mit einem sic halbleiterkörper und verfahren zur herstellung eines halbleiterbauelements
US10586845B1 (en) 2018-11-16 2020-03-10 Infineon Technologies Ag SiC trench transistor device and methods of manufacturing thereof
US10985248B2 (en) * 2018-11-16 2021-04-20 Infineon Technologies Ag SiC power semiconductor device with integrated Schottky junction
US10903322B2 (en) * 2018-11-16 2021-01-26 Infineon Technologies Ag SiC power semiconductor device with integrated body diode
CN113614924A (zh) * 2019-03-29 2021-11-05 京瓷株式会社 半导体装置以及半导体装置的制造方法
US11004945B2 (en) * 2019-05-21 2021-05-11 Infineon Technologies Austria Ag Semiconductor device with spicular-shaped field plate structures and a current spread region
CN113690301B (zh) * 2020-05-18 2024-01-26 华润微电子（重庆）有限公司 半导体器件及其制备方法
CN113838909B (zh) * 2021-08-19 2022-10-14 深圳深爱半导体股份有限公司 沟槽型原胞结构及制备方法
CN113690234A (zh) * 2021-08-25 2021-11-23 威星国际半导体(深圳)有限公司 电力电子半导体器件
CN115188803B (zh) * 2022-09-09 2022-12-13 深圳芯能半导体技术有限公司 一种沟槽侧壁栅碳化硅mosfet及其制备方法

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010109221A (ja) * 2008-10-31 2010-05-13 Rohm Co Ltd 半導体装置
JP2010225615A (ja) * 2009-03-19 2010-10-07 Denso Corp 炭化珪素半導体装置およびその製造方法
JP2011009387A (ja) * 2009-06-24 2011-01-13 Renesas Electronics Corp 半導体装置およびその製造方法ならびにそれを用いたｄｃ−ｄｃコンバータ
JP2017079251A (ja) * 2015-10-20 2017-04-27 富士電機株式会社 半導体装置および半導体装置の製造方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3502371B2 (ja) 2000-10-23 2004-03-02 松下電器産業株式会社 半導体素子
US7126169B2 (en) 2000-10-23 2006-10-24 Matsushita Electric Industrial Co., Ltd. Semiconductor element
JP5304416B2 (ja) 2009-04-28 2013-10-02 富士電機株式会社 電力変換回路
DE102011003456A1 (de) 2011-02-01 2012-08-02 Robert Bosch Gmbh Halbleiteranordnung mit reduziertem Einschaltwiderstand
JP5865016B2 (ja) * 2011-10-31 2016-02-17 株式会社 日立パワーデバイス トレンチ型ショットキー接合型半導体装置及びその製造方法
CN104106142B (zh) * 2012-02-10 2016-03-09 松下知识产权经营株式会社 半导体装置及其制造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2010109221A (ja) * 2008-10-31 2010-05-13 Rohm Co Ltd 半導体装置
JP2010225615A (ja) * 2009-03-19 2010-10-07 Denso Corp 炭化珪素半導体装置およびその製造方法
JP2011009387A (ja) * 2009-06-24 2011-01-13 Renesas Electronics Corp 半導体装置およびその製造方法ならびにそれを用いたｄｃ−ｄｃコンバータ
JP2017079251A (ja) * 2015-10-20 2017-04-27 富士電機株式会社 半導体装置および半導体装置の製造方法

Also Published As

Publication number Publication date
JP2019071313A (ja) 2019-05-09
DE102018214901A1 (de) 2019-04-11
CN109638069A (zh) 2019-04-16
JP7059555B2 (ja) 2022-04-26
US10546950B2 (en) 2020-01-28
US20190109227A1 (en) 2019-04-11

Similar Documents

Publication Publication Date Title
CN109638069B (zh) 半导体装置
US11430784B2 (en) Semiconductor device
US9059284B2 (en) Semiconductor device
US10217858B2 (en) Semiconductor device and method of manufacturing semiconductor device
JP7471267B2 (ja) 半導体装置
US8269272B2 (en) Semiconductor device and method for manufacturing the same
US20140264433A1 (en) Dual-gate trench igbt with buried floating p-type shield
US9825164B2 (en) Silicon carbide semiconductor device and manufacturing method for same
CN108604598B (zh) 半导体装置
US20150380542A1 (en) Charge Compensation Structure and Manufacturing Therefor
EP3005419A1 (en) Trench shield connected jfet
KR20140097975A (ko) 반도체장치 및 그 제조방법
JP2010147405A (ja) 半導体装置およびその製造方法
JP2004319732A (ja) 半導体装置
US11552173B2 (en) Silicon carbide device with trench gate
JP5646044B2 (ja) 炭化珪素半導体装置およびその製造方法
JP2019003967A (ja) 半導体装置および半導体装置の製造方法
JP7029711B2 (ja) 半導体装置
JP7155641B2 (ja) 半導体装置
JP2024511552A (ja) 信頼性及び導通が向上したトレンチ型パワー・デバイス
JP2019096794A (ja) 半導体装置
CN112466922A (zh) 半导体装置
US11004839B1 (en) Trench power MOSFET with integrated-schottky in non-active area
CN112466923A (zh) 半导体装置
WO2023112547A1 (ja) 半導体装置

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant