CN109617540A - A kind of signal time-delay mechanism - Google Patents
A kind of signal time-delay mechanism Download PDFInfo
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- CN109617540A CN109617540A CN201811431343.8A CN201811431343A CN109617540A CN 109617540 A CN109617540 A CN 109617540A CN 201811431343 A CN201811431343 A CN 201811431343A CN 109617540 A CN109617540 A CN 109617540A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/135—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals by the use of time reference signals, e.g. clock signals
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
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Abstract
The invention discloses a kind of signal time-delay mechanism, including times frequency module, clock distribution block, D/A converter module, analog filter block, waveform-shaping module and the control module that is connected with the clock distribution block and D/A converter module respectively being sequentially connected；It is sent into times frequency module to time delayed signal, waveform-shaping module exports time delayed signal.The present invention is able to solve the problem of traditional delay line chip cannot take into account thin stepping delay and Larger Dynamic amount of delay, while can realize excellent delay precision index and randomized jitter index, and circuit complexity is low, engineering practical value with higher.
Description
Technical field
The present invention relates to signal processing technology field, in particular to a kind of high-precision of cyclical signal, is moved greatly thin stepping
State time-delay mechanism.
Background technique
With the development of electronic technology, electronic system proposes higher technical requirements to signal delay circuit.Especially
The requirement of the indexs such as precision, stepping and reference time delay to signal delay is higher and higher, some systems also need to apply signal
Dynamic delay is regular and delay rule is controllable in real time.If step-by-step movement time delayed signal is widely used in equivalent sampling system, use
To obtain higher equivalent sampling rate by lower sampling rate.
Currently, realizing that the main stream approach of signal delay is delay line technology, that is, use digital programmable delay line chip.It is small
Stepping delay line chip is delayed stepping up to 10ps magnitude, but reference time delay is generally in 10ns magnitude, it is difficult to adapt to Larger Dynamic
Reference time delay demand.The reference time delay of Larger Dynamic delay line chip is delayed step generally in tens nanoseconds to several musec orders
Into generally in nanosecond order, and delay precision is poor, and the response time is long.
Existing several technical solutions, improve the application circuit of delay line chip, overcome prolong to a certain extent
When the thin stepping of core piece and Larger Dynamic index the problem of cannot taking into account, but also have certain limitation.Such as application No. is
The 200910214528.8 patent application high-precision step delay production method of dynamic calibration " can ", is utilized 5 thin steppings
Delay chip MC100EPT195 is cascaded, to achieve the purpose that expand maximum delay range the delay stepping, it can be achieved that 10ps
And the maximum delay range of 50ns.Its problem is multi-disc cascade, increases the complexity and power consumption of circuit, and wants to realize bigger
The amount of delay of range, the complexity of circuit also need to further increase.Such as application No. is 201410001964.8 patent applications
" sequential sampling circuit and the method for sampling based on time delayed signal " is utilized thin stepping delay chip MC100EPT195 and moves greatly
State delay chip DS1123L is cascaded, to take into account the latency requirement of thin stepping and Larger Dynamic.Its problem is prolonging for DS1123L
When the response time it is longer, can time delayed signal pulse recurrence frequency (PRF) it is too small, limit its application, and circuit complexity compared with
It is high.Such as application No. is 201610160711.4 patent application " a kind of equivalent sampling circuit of programmable delay chip and samplings
Method " uses thin stepping delay chip MC100EPT195, cooperates the counter inside fpga chip and trigger realization pair
The big stepping of signal is delayed, and can also take into account the latency requirement of thin stepping and Larger Dynamic.Its problem is that FPGA carries out pulse signal
Delay, can introduce biggish randomized jitter (Random Jitter).
Summary of the invention
It theoretically can be with object of the present invention is to provide a kind of high-precision, thin stepping, reference time delay for cyclic pulse signal
Infinitely great signal time-delay mechanism, while may be implemented to the real-time controllable of amount of delay.The device can be applied in equivalent sampling
In system, the cumulative amount of delay of stepping is applied to the pulse in each period, generates high-accuracy sampling pulse signal.It is also applicable in
In time hopping communication system, different delayed time amount is applied by the pulse signal to each period, generates random time-hopping sequence.The present invention
It is able to solve the problem of traditional delay line chip cannot take into account thin stepping delay and Larger Dynamic amount of delay, while can be realized excellent
Delay precision index and randomized jitter index, and circuit complexity is low, engineering practical value with higher.
To achieve the above object, the thin stepping Larger Dynamic signal time-delay mechanism of a kind of high-precision provided by the invention, including according to
Secondary connected times frequency module, clock distribution block, D/A converter module, analog filter block, waveform-shaping module and respectively with
The control module that the clock distribution block is connected with D/A converter module；Described times of frequency module is received to time delayed signal, is generated
The frequency-doubled signal of presupposition multiple to time delayed signal；The clock distribution block is used to believe the frequency multiplication of described times of frequency module output
Number it is divided into two-way, obtains the work clock of the control module and the sampling clock of the D/A converter module；The control mould
Block is stored with the sine wave digital signal of a cycle；When the control module is according to the clock distribution block assignment
Clock obtains the index address of waveform, and obtains corresponding wave signal data by the index address；The digital-to-analogue conversion mould
Under the synchronization for the sampling clock that the clock distribution block distributes, the wave signal data that the control module is obtained turns block
It is changed to the sine wave analog signal with amount of delay information；The analog filter block is adopted what the D/A converter module exported
The image signal in sample leakage signal and second, third Nyquist area is inhibited, and filtered sine wave analog signal is exported；
The waveform-shaping module is converted into the delay letter to time delayed signal to the sine wave analog signal that the analog filter exports
Number.
Further, the control module obtains the index of waveform according to the clock distribution block assignment clock
Address specifically includes: the control module generates frequency control under the synchronization of the clock distribution block assignment clock
Word processed, phase control words, and the index address of waveform is obtained by phase accumulator.
Further, the control module is provided with processor, phase register and memory；On the phase register
Zeros data after electricity；The memory is stored with the sine wave signal waveform of computer program and a cycle；The processor
It executes computer program and realizes following step: with obtaining the index of waveform according to the clock distribution block assignment clock
Location, and corresponding wave signal data is obtained by the index address；Above-mentioned steps specifically include:
S1: according to the frequency f to time delayed signal1, work clock frequency fs, frequency control word digit M, calculate frequency control
Word FTW processed, calculation formula are as follows:
S2: according to amount of delay tDL, to the frequency f of time delayed signal1, phase controlling word bit number M, calculate phase control words POW,
Calculation formula are as follows:
POW=f1×tDL×2M；
S3: according to frequency control word digit, a Waveform storage table is established in memory, storage table address range is 0
~2M- 1, the data bits of storage table is equal with the digital analog converter digit, storage table data calculation formula are as follows:
Wherein data (m) is the wave signal data that address is m in storage table；
S4: clock synchronizes down at work, and the control module takes out the data in phase register, with frequency control word
It is added, obtained data are re-fed into phase register, and phase register output data is added with phase control words, obtain wave
The index address of shape storage table；
S5: corresponding wave signal data is read from the Waveform storage table according to the index address.
Further, the control module is FPGA.
Further, the memory is the read-only memory inside FPGA.
Further, the waveform-shaping module includes operational amplifier and voltage comparator；The operational amplifier will
The bias voltage and peak value of the sine wave analog signal of the analog filter output are adjusted to the input of the voltage comparator
Range；The voltage comparator converts operational amplifier sine wave analog signal adjusted to the delay of square
Signal.
Further, the minimum value of the presupposition multiple determines that maximum value is according to according to nyquist sampling theorem
The maximum sample clock frequency of D/A converter module and the maximum functional clock frequency of the control module determine.
Further, described times of frequency module is simulation frequency multiplier or is realized using phase-locked loop circuit.
Compared with prior art, the present invention has the advantage that:
1, the signal delay technique that the present invention uses, without using traditional delay line chip, therefore the stepping that is delayed is no longer restricted
In chip itself, but guarantee to prolong by the digit of frequency control word, phase control words in flexible configuration delay algorithm A1
Shi Bujin, for example pulse repetition to time delayed signal S1 is 10MHz, phase controlling word bit number takes 16, then the stepping that is delayed is
The existing thin stepping delay line chip delay minimum 10ps of stepping.Index achieved by the present invention is than tradition delay
Core piece improves nearly 7 times, and by increasing phase controlling word bit number, there are also the spaces further promoted.
2, the signal delay technique that the present invention uses, without using traditional delay line chip, therefore reference time delay is no longer restricted
In chip itself, does not need to cascade by multistage delay chip to expand reference time delay yet, but pass through flexible configuration algorithm journey
Sequence is realized.For example the pulse to time delayed signal S1 is 10MHz, the sampling signal frequency of digital analog converter is 100MHz, if
Amount of delay is less than 10ns, then is realized by the value of configuration phase control word, such as when phase control words are 6553, amount of delay
For
If amount of delay is greater than 10ns, operating clock signals can be prolonged by increasing level-one d type flip flop inside FPGA
When one pulse period and realize.Increase the number of cascaded D-flip-flops, then the amount of delay of 10ns integral multiple can be achieved.Therefore, it manages
It is infinity by the upper achievable reference time delay of the present invention.
3, the circuit selected by the present invention, is widely used low noise audio technology, such as the simulation times in times frequency module U1
Frequency device or phase-locked loop circuit, the clock distribution chip in the clock frequency division module U2, the high resolution digital-to-analogue conversion mould
Digital analog converter etc. in block reduces circuit noise, reduces signal cross-talk, and pass through the mould by rationally designing power supply
The signal that quasi- filter U5 inhibits output factors signal, therefore obtains has the purity of frequency spectrum up to 70dBc, from time domain wave
It is seen in shape, randomized jitter index is picosecond magnitude, has extremely low additional random amount of jitter, there is very high delay precision,
It is calibrated without the later period.
4, the signal delay technique that uses of the present invention, circuit complexity is low, and is conventional device, FPGA used can be
The master control FPGA that unites is shared, and delay algorithm design is convenient, parameter configuration is flexible, versatile, in military project electronics, Industry Control, the people
Very strong practical value is all had with product scope.
Detailed description of the invention
Fig. 1 is a kind of composed structure schematic diagram of signal time-delay mechanism embodiment of the present invention；
Fig. 2 is the logic diagram of the signal delay algorithm in the embodiment of the present invention.
Specific embodiment
The present invention is done with reference to the accompanying drawing and is further described in detail.
Referring to Fig.1, the signal time-delay mechanism for showing the thin stepping Larger Dynamic signal delay of the achievable high-precision of the present invention is real
The composed structure for applying example, including times frequency module U1, the clock distribution block U2, high resolution D/A converter module being sequentially connected
U4, analog filter block U5, waveform-shaping module U6 and respectively with the clock distribution block U2 and high resolution digital-to-analogue conversion
Module U4 connected control module U3.It is sent into times frequency module U1 to time delayed signal S1, waveform-shaping module U6 exports time delayed signal
S2。
When it is implemented, frequency module U1 can choose simulation harmonic multipliers, phase-locked loop circuit etc. again, for will be wait be delayed
The pulse recurrence frequency f of signal S11Improve N times, output signal is used as the sampled signal of the D/A converter module U4 and described
The work clock of control module U3.The minimum value of N is determined that the maximum value of N is according to the control mould by nyquist sampling theorem
The maximum operating frequency of block U3 and the maximum sample frequency of the high resolution D/A converter module U4 determine.
The Low phase noise clock distribution chip that clock distribution block U2 can choose TI ADT company (reduces draw as far as possible
The phase difference and randomized jitter entered), for the signal of described times of frequency module U1 output to be carried out power distribution.Its output signal one
Road is exported to the control module U3, in addition the work clock as control module is exported all the way to the high resolution digital-to-analogue
Conversion module U4, the sampling clock as D/A converter module.Have signal inclined when it is implemented, clock distribution block U2 is selected
The product of conversion function is set, with the input signal of the output signal level of the compatible times frequency module U1, the control module U3
Input signal (sampling clock) level of (work clock) level, the high resolution D/A converter module U4.
Control module U3 can be made of high speed FPGA, and Load Signal delays time to control and algorithm journey in program memory
Sequence A1 and Wave data table.Following steps can be achieved in the control and the execution of algorithm routine A1: according to the clock distribution
The work clock of module assignment obtains the index address of waveform, and obtains the correspondence in Wave data table by the index address
Wave signal data (or wave-shape amplitude data).
The wave signal data that high resolution D/A converter module U4 is used to export the control module U3 is in sampling
Analog signal is converted under the synchronization of clock.When it is implemented, high resolution D/A converter module U4 should have 12 bits or more
Data bit, while need logarithmic mode conversion module power supply and circuit placement-and-routing carry out careful design, export without miscellaneous
Scattered dynamic range reaches 70dBc.When the spurious-free dynamic-range specifications are tested before the analog filter block U5, need
The test of one Nyquist area, is not counted in the image signal of sampled signal leakage and second, third Nyquist area.
Analog filter block U5 forms simulation low-pass filter by the cascade of the separating components such as capacitor and inductance, lets out to sampling
Dew signal (i.e. parasitic sampled signal), the second Nyquist area, third Nyquist area image signal sufficiently inhibited.
Waveform-shaping module U6 can be made of operational amplifier, wideband voltage comparator etc., be used for digital-to-analogue conversion mould
The differential signal of block (DAC, Digital to Analog Converter) output is converted into single-ended signal, provides altogether to signal
Mould bias, the peak value of adjustment signal, and by wideband voltage comparator sine wave signal is converted to precipitous rising edge and
The square-wave signal of failing edge.If the analog signal that high resolution D/A converter module U4 is exported is difference form, the operation
Amplifier is needed using difference amplifier.Operational amplifier should have the function of bias voltage adjustment, the voltage bias of output signal
It is adjusted on the threshold voltage of wideband voltage comparator.Operational amplifier should have the function of gain adjustment.
Main idea is that: by frequency module U1 again, to time delayed signal S1 (assuming that pulse recurrence frequency by described in
For f1) it is multiplied to higher frequency, obtain the work clock of the control module and the sampling clock of the D/A converter module
fs, pass through design frequency control word (FTW, Frenquency Tuning Word) and phase control words (POW, Phase
Offset Word), under the synchronization of external work clock, obtain the output valve of phase accumulator.The output valve of phase accumulator
As the address in Wave data table, it is addressed to obtain the wave-shape amplitude data being pre-stored in Waveform storage table, in the number
Synthesizing frequency on mould conversion module is f1, and have the sine wave signal of delayed data.The sine wave signal is by simulation filter
Involve shaping pulse, obtains time delayed signal S2.Wherein the core of algorithm be frequency control word, phase control words calculation,
The design etc. of Waveform storage table.
Fig. 2 is the control and the logic diagram of algorithm routine A1, including a phase accumulator P1, a phase controlling
A word adder P4 and phase width converter P5.
Phase accumulator P1 therein includes an a frequency control word adder P2 and phase register P3.The phase
Output valve is 0 to bit register P3 after initialization.The frequency control word adder, will frequency under the synchronization of external work clock
The phase data deposited in rate control word FTW and current phase register P3 adds up, and stores into phase register P3.
Wherein the calculation method of frequency control word FTW is as follows:
In above-mentioned formula, M is the digit of frequency control word, f1It is the frequency to time delayed signal, fsIt is the frequency of work clock
Rate.
The output of the phase accumulator P1 is added under the synchronization of external work clock with phase control words POW.Phase
Control word, which plays the role of applying signal, to be delayed.The amount of delay in each period can be according to list index, can also be according to one
Set pattern rule carries out real-time resolving.By amount of delay tDLCalculation method to phase control words POW is as follows:
POW=f1×tDL×2M
In above-mentioned formula, M is the digit (identical as the digit of frequency control word) of phase control words, f1It is to time delayed signal
Frequency, tDLIt is amount of delay.
Index address of the output of the adder P4 as the phase width converter P5, obtains amplitude data.Phase width turns
Parallel operation is exactly a Wave data table stored in ROM, which is 2M(such as address can be 0
~2M-1), data bits is consistent with the digit of high resolution D/A converter module U4 in Wave data table.Wave data table according to
Sequence of addresses successively houses the quantized data of a complete sine wave period.Under the synchronization of external work clock, adder
The output of P4 indexes out Wave data as address, and output amplitude control word can be obtained to high resolution D/A converter module
The sine waveform of delay.
It should be understood that the part that this specification does not elaborate, belongs to the prior art.
Although specific embodiments of the present invention have been described above, it should be appreciated to those skilled in the art that these are only
Be for example, can to these embodiments many modifications may be made or deformation, without departing from the principle and substance of the present invention.
The scope of the present invention is only limited by the claims that follow.
Claims (8)
1. a kind of signal time-delay mechanism, which is characterized in that times frequency module, clock distribution block, digital-to-analogue including being sequentially connected turn
Mold changing block, analog filter block, waveform-shaping module and respectively it is connected with the clock distribution block and D/A converter module
Control module；
Described times of frequency module is received to time delayed signal, generates the frequency-doubled signal of the presupposition multiple to time delayed signal；
The clock distribution block is used to the frequency-doubled signal that described times of frequency module exports being divided into two-way, obtains the control module
Work clock and the D/A converter module sampling clock；
The control module is stored with the sine wave digital signal of a cycle；The control module is according to the clock distribution mould
Block assignment clock obtains the index address of waveform, and obtains corresponding wave signal data by the index address；
The D/A converter module obtains the control module under the synchronization for the sampling clock that the clock distribution block distributes
To wave signal data be converted to the sine wave analog signal with amount of delay information；
The sampling leakage signal and second, third Nyquist area that the analog filter block exports the D/A converter module
Image signal inhibited, export filtered sine wave analog signal；
The waveform-shaping module is converted into prolonging to time delayed signal to the sine wave analog signal that the analog filter exports
When signal.
2. a kind of signal time-delay mechanism according to claim 1, which is characterized in that the control module is according to the clock
Distribution module assignment clock obtains the index address of waveform, specifically includes:
The control module generates frequency control word, phase under the synchronization of the clock distribution block assignment clock
Control word, and the index address of waveform is obtained by phase accumulator.
3. a kind of signal time-delay mechanism according to claim 1, which is characterized in that the control module is provided with processing
Device, phase register and memory；The phase register powers on rear zeros data；The memory is stored with computer program
With the sine wave signal waveform of a cycle；The processor executes computer program and realizes following step: according to the clock
Distribution module assignment clock obtains the index address of waveform, and obtains corresponding waveform signal by the index address
Data；
Above-mentioned steps specifically include:
S1: according to the frequency f to time delayed signal1, work clock frequency fs, frequency control word digit M, calculate frequency control word
FTW, calculation formula are as follows:
S2: according to amount of delay tDL, to the frequency f of time delayed signal1, phase controlling word bit number M, calculate phase control words POW, calculate
Formula are as follows:
POW=f1×tDL×2M；
S3: according to frequency control word digit, a Waveform storage table is established in memory, storage table address range is 0~2M-
1, the data bits of storage table is equal with the digital analog converter digit, storage table data calculation formula are as follows:
Wherein data (m) is the wave signal data that address is m in storage table；
S4: clock synchronizes down at work, and the control module takes out the data in phase register, with frequency control word phase
Add, obtained data are re-fed into phase register, and phase register output data is added with phase control words, obtain waveform
The index address of storage table；
S5: corresponding wave signal data is read from the Waveform storage table according to the index address.
4. a kind of signal time-delay mechanism according to claim 1, which is characterized in that the control module is FPGA.
5. a kind of signal time-delay mechanism according to claim 4, which is characterized in that the memory is inside FPGA
Read memory.
6. a kind of signal time-delay mechanism according to claim 1, which is characterized in that the waveform-shaping module includes operation
Amplifier and voltage comparator；
The operational amplifier by the bias voltage for the sine wave analog signal that the analog filter exports and peak value adjust to
The input range of the voltage comparator；
The voltage comparator converts operational amplifier sine wave analog signal adjusted to the delay of square
Signal.
7. a kind of signal time-delay mechanism according to claim 1, which is characterized in that the minimum value of the presupposition multiple according to
Nyquist sampling theorem determines that maximum value is according to the maximum sample clock frequency and the control mould of the D/A converter module
The maximum functional clock frequency of block determines.
8. a kind of signal time-delay mechanism according to claim 1, which is characterized in that described times of frequency module is simulation frequency multiplier
Or it is realized using phase-locked loop circuit.
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| CN110058100A (en) * | 2019-05-08 | 2019-07-26 | 南京南瑞继保电气有限公司 | A kind of the Time delay measurement method, apparatus and system of DC transmission system |
| CN110764492A (en) * | 2019-11-15 | 2020-02-07 | 北京广利核***工程有限公司 | Multichannel switching value signal generating device and SOE event simulator |
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| CN110764492B (en) * | 2019-11-15 | 2021-06-29 | 北京广利核***工程有限公司 | Multichannel switching value signal generating device and SOE event simulator |
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