CN109559988A - The preparation method and device of silicon wafer - Google Patents
The preparation method and device of silicon wafer Download PDFInfo
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- CN109559988A CN109559988A CN201811454355.2A CN201811454355A CN109559988A CN 109559988 A CN109559988 A CN 109559988A CN 201811454355 A CN201811454355 A CN 201811454355A CN 109559988 A CN109559988 A CN 109559988A
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 135
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 134
- 239000010703 silicon Substances 0.000 title claims abstract description 134
- 238000002360 preparation method Methods 0.000 title claims abstract description 38
- 238000000137 annealing Methods 0.000 claims abstract description 189
- 239000007789 gas Substances 0.000 claims description 107
- 239000011261 inert gas Substances 0.000 claims description 37
- 238000010438 heat treatment Methods 0.000 claims description 23
- 238000000034 method Methods 0.000 claims description 16
- 230000008569 process Effects 0.000 claims description 7
- 238000010792 warming Methods 0.000 claims description 7
- 239000000203 mixture Substances 0.000 claims description 6
- 239000001257 hydrogen Substances 0.000 claims description 5
- 229910052739 hydrogen Inorganic materials 0.000 claims description 5
- 150000002500 ions Chemical class 0.000 claims description 5
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 abstract description 25
- 238000006722 reduction reaction Methods 0.000 description 29
- 230000009467 reduction Effects 0.000 description 21
- 230000007547 defect Effects 0.000 description 10
- 230000000694 effects Effects 0.000 description 10
- 239000013078 crystal Substances 0.000 description 9
- 239000002245 particle Substances 0.000 description 6
- 239000003595 mist Substances 0.000 description 5
- 239000000126 substance Substances 0.000 description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 235000013399 edible fruits Nutrition 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 239000004065 semiconductor Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- UGFAIRIUMAVXCW-UHFFFAOYSA-N Carbon monoxide Chemical compound [O+]#[C-] UGFAIRIUMAVXCW-UHFFFAOYSA-N 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 229910002091 carbon monoxide Inorganic materials 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 239000000356 contaminant Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 150000003254 radicals Chemical class 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- 238000004220 aggregation Methods 0.000 description 1
- 230000002776 aggregation Effects 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 239000006227 byproduct Substances 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000004880 explosion Methods 0.000 description 1
- 239000003574 free electron Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 150000002431 hydrogen Chemical class 0.000 description 1
- 229910052743 krypton Inorganic materials 0.000 description 1
- DNNSSWSSYDEUBZ-UHFFFAOYSA-N krypton atom Chemical compound [Kr] DNNSSWSSYDEUBZ-UHFFFAOYSA-N 0.000 description 1
- 238000011031 large-scale manufacturing process Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052754 neon Inorganic materials 0.000 description 1
- GKAOGPIIYCISHV-UHFFFAOYSA-N neon atom Chemical compound [Ne] GKAOGPIIYCISHV-UHFFFAOYSA-N 0.000 description 1
- 230000007935 neutral effect Effects 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 229910052724 xenon Inorganic materials 0.000 description 1
- FHNFHKCVQCLJFQ-UHFFFAOYSA-N xenon atom Chemical compound [Xe] FHNFHKCVQCLJFQ-UHFFFAOYSA-N 0.000 description 1
- 238000004857 zone melting Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01J—ELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
- H01J37/00—Discharge tubes with provision for introducing objects or material to be exposed to the discharge, e.g. for the purpose of examination or processing thereof
- H01J37/32—Gas-filled discharge tubes
- H01J37/32009—Arrangements for generation of plasma specially adapted for examination or treatment of objects, e.g. plasma sources
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67098—Apparatus for thermal treatment
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Plasma & Fusion (AREA)
- Chemical & Material Sciences (AREA)
- Analytical Chemistry (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
Abstract
A kind of preparation method and device of silicon wafer, which comprises under the plasma state atmosphere of reducibility gas, the first step annealing is carried out to silicon wafer, during first step annealing, annealing temperature rises to the first preset temperature from initial temperature；Under the plasma state atmosphere of reducibility gas, the second step annealing is carried out to the silicon wafer, during second step annealing, annealing temperature remains first preset temperature；Wherein, the plasma state atmosphere of the reducibility gas is the atmosphere for including the plasma generated based on reducibility gas.The present invention program can be improved the quality of silicon wafer, reduce production cost, improve production efficiency.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to the preparation methods and device of a kind of silicon wafer.
Background technique
In prior art, silicon single crystal ingot usually is obtained using vertical pulling method or zone-melting process, then to the silicon single crystal ingot
The techniques such as wire cutting, grinding, polishing, cleaning are carried out, to obtain silicon wafer.
However during growing crystal, since the aggregation in vacancy will form empty type microdefect, i.e. crystal primary sound grain
Sub- defect is easily reduced the integrality (Gate Oxide Integrity, GOI) of MOS device gate oxide, is furthermore easy changing
Learn the mist degree for leading to silicon chip surface in mechanical polishing (Chemical Mechanical Polishing, CMP) technical process
(Haze) value is higher.
In the prior art, it generallys use extension (Epitaxy, EPI) layer process and grows one layer on the surface of the silicon wafer
The epitaxial film of identical crystal orientation, to reduce the empty type microdefect and reduce the haze value of silicon chip surface, however EPI technique volume
A large amount of processing steps are increased outside, reduce production efficiency and seriously increase cost.
Summary of the invention
The technical problem to be solved by the present invention is to provide a kind of preparation method of silicon wafer and devices, and the product of silicon wafer can be improved
Matter reduces production cost, improves production efficiency.
In order to solve the above technical problems, the embodiment of the present invention provides a kind of preparation method of silicon wafer, comprising: in reproducibility gas
Under the plasma state atmosphere of body, the first step annealing is carried out to silicon wafer, during first step annealing, annealing temperature is from starting
Temperature rises to the first preset temperature；Under the plasma state atmosphere of reducibility gas, the second step annealing is carried out to the silicon wafer,
During second step annealing, annealing temperature remains first preset temperature；Wherein, the reducibility gas etc.
Ionic state atmosphere is the atmosphere for including the plasma generated based on reducibility gas.
Optionally, first step annealing and the second step annealing are carried out in annealing device, the first step annealing it
Before, the preparation method of the silicon wafer further include: inert gas is passed through in Xiang Suoshu annealing device to form inert atmosphere, and right
The annealing device carries out being warming up to the initial temperature；Atmosphere processing is carried out to the annealing device, with from the indifferent gas
Atmosphere is changed into the plasma state atmosphere of the reducibility gas.
Optionally, after second step annealing, the preparation method of the silicon wafer further include: the silicon wafer is carried out
Third step annealing, in the third step annealing process, annealing temperature drops to the second default temperature from first preset temperature
Degree.
Optionally, second preset temperature is 400 DEG C to 700 DEG C.First step annealing, the second step annealing and third
Step annealing is carried out in annealing device, is being carried out second step annealing and is being carried out between the third step annealing, described
Silicon wafer preparation method further include: be passed through inert gas in Xiang Suoshu annealing device, and the institute in the annealing device be discharged
Plasma is stated, to form inert atmosphere.
Optionally, first step annealing and the second step annealing are carried out in annealing device, the reducibility gas
Plasma state atmosphere forming step include: based on the reducibility gas generate plasma, then to it is described annealing set
It is passed through inert gas and the plasma in standby, to form the plasma state atmosphere of the reducibility gas, wherein described
The plasma state atmosphere of reducibility gas is the atmosphere for including inert gas with the mixture of the plasma；Alternatively, base
Plasma is generated in the reducibility gas, the plasma is then passed through into the annealing device, and be discharged
Inert gas in the annealing device, to form the plasma state atmosphere of the reducibility gas, wherein the reproducibility gas
The plasma state atmosphere of body is the atmosphere for only including the plasma.
Optionally, the reducibility gas is hydrogen.
Optionally, first preset temperature is 850 DEG C to 1200 DEG C.
Optionally, the initial temperature is 400 DEG C to 700 DEG C.
Optionally, first step annealing includes multiple annealing stages, and the heating rate of posterior annealing stage is less than
The heating rate of first annealing stage.
Optionally, the anneal duration of second step annealing is 20 minutes to 90 minutes.
In order to solve the above technical problems, the embodiment of the present invention provides a kind of preparation facilities of silicon wafer, comprising:
Optionally, plasma generating apparatus, for generating plasma based on reducibility gas；Annealing device, it is described
Annealing device includes: annealing chamber；Wafer susceptor, the wafer susceptor are located in the anneal chamber room, and for placing wafer；
Plasma intake line, for inputting the plasma into the anneal chamber room.
Optionally, the preparation facilities of the silicon wafer further include: inert gas input pipe road is used for the annealing chamber
Interior input inert gas；Gas export line, for exporting the plasma and/or the inertia out of described anneal chamber room
Gas；The pump housing, the pump housing are connect with the gas export line, for extracting the plasma out of described anneal chamber room
Body and/or the inert gas.
Compared with prior art, the technical solution of the embodiment of the present invention has the advantages that
In embodiments of the present invention, by carrying out second to the silicon wafer under the plasma state atmosphere of reducibility gas
Step annealing, during second step annealing, annealing temperature remains first preset temperature, not only can be to silicon wafer table
The oxide layer in face carries out reduction reaction, can also the oxide film in the cavity to silicon wafer inside certain depth restore it is anti-
It answers, so as to efficiently reduce the empty type microdefect in the silicon wafer, and is more had to the lattice defect in silicon wafer
The reparation of effect improves the quality of silicon wafer so that the mist for reducing silicon chip surface is all worth.Further, compared to only include reduction
Property gas reducing atmosphere, due to include based on reducibility gas generate plasma reducibility gas plasma state
Atmosphere has stronger reproducibility, helps to realize preferably reduction effect under lower reduction temperature, shorter reduction duration
Fruit improves production efficiency to help to reduce production cost.
Further, before carrying out third step annealing to the silicon wafer, further include the steps that forming inert atmosphere, can keep away
Exempt from influence of the reducing atmosphere to operator, improves production security.
Further, first step annealing includes multiple annealing stages, and the heating rate of posterior annealing stage is less than
The heating rate of first annealing stage, can be by improving heating rate in low-temperature space, to reach preset temperature as early as possible, in high temperature
Area reduces heating rate, to improve the temperature consistency of silicon chip edge Yu silicon wafer center, to improve in silicon chip edge and silicon wafer
The consistency of the reduction reaction at center.
Detailed description of the invention
Fig. 1 be in the prior art a kind of silicon wafer from a surface to the corresponding resistivity curve figure of internal different depth；
Fig. 2 is a kind of flow chart of the preparation method of silicon wafer in the embodiment of the present invention；
Fig. 3 is a kind of curve graph that annealing temperature changes with anneal duration in the embodiment of the present invention；
Fig. 4 is the curve graph that another annealing temperature changes with anneal duration in the embodiment of the present invention；
Fig. 5 be in the embodiment of the present invention a kind of silicon wafer from a surface to the corresponding resistivity curve figure of internal different depth；
Fig. 6 is a kind of structural schematic diagram of the preparation facilities of silicon wafer in the embodiment of the present invention.
Specific embodiment
In the technology of existing growth crystal, the haze value of oxide layer easy to form and silicon chip surface is higher.
Specifically, silicon wafer cleaning storing process in, surface oxide layer easy to form, so in annealing oxide layer hold
It easily adsorbs annealing device (such as furnace body) or closes on the impurity (such as boron atom) of silicon wafer.And then the impurity (such as boron is former
Son) it penetrates readily through oxide layer and then is diffused into silicon chip surface region, lead to the reduction of silicon chip surface resistance value.
Fig. 1 be in the prior art a kind of silicon wafer from a surface to the corresponding resistivity curve figure of internal different depth.
As shown in Figure 1, the distance away from silicon chip surface is closer, being influenced by the impurity that oxide layer is adsorbed, resistivity is lower,
Resistivity is inconsistent in from silicon chip surface to the preset range of inside, and lower resistivity causes insulating properties to reduce, and easy pair
The source and drain doping area being subsequently formed has an impact.
The present inventor has found after study, in the prior art, is not only easy to form oxide layer in silicon chip surface,
And then adsorbing contaminant, further also it is micro- scarce to form a large amount of empty types inside a certain range of silicon wafer apart from silicon chip surface
It falls into, i.e. Crystal Originated Particle defect, is also oxidized easily in the cavity type microdefect, and then form very thin oxide film
And adsorbing contaminant further results in silicon chip surface resistance value since the oxide film in empty type microdefect is difficult to remove
Reduction and the higher problem of haze value.
In embodiments of the present invention, by carrying out second to the silicon wafer under the plasma state atmosphere of reducibility gas
Step annealing, during second step annealing, annealing temperature remains first preset temperature, not only can be to silicon wafer table
The oxide layer in face carries out reduction reaction, can also the oxide film in the cavity to silicon wafer inside certain depth restore it is anti-
It answers, so as to efficiently reduce the empty type microdefect in the silicon wafer, and is more had to the lattice defect in silicon wafer
The reparation of effect improves the quality of silicon wafer so that the mist for reducing silicon chip surface is all worth.Further, compared to only include reduction
Property gas reducing atmosphere, due to include based on reducibility gas generate plasma reducibility gas plasma state
Atmosphere has stronger reproducibility, helps to realize preferably reduction effect under lower reduction temperature, shorter reduction duration
Fruit improves production efficiency to help to reduce production cost.
It is understandable to enable above-mentioned purpose of the invention, feature and beneficial effect to become apparent, with reference to the accompanying drawing to this
The specific embodiment of invention is described in detail.
Referring to Fig. 2, Fig. 2 is a kind of flow chart of the preparation method of silicon wafer in the embodiment of the present invention.The preparation of the silicon wafer
Method may include step S21 and step S22:
Step S21: under the plasma state atmosphere of reducibility gas, the first step annealing, the first step are carried out to silicon wafer
During annealing, annealing temperature rises to the first preset temperature from initial temperature；
Step S22: under the plasma state atmosphere of reducibility gas, carrying out the second step annealing to the silicon wafer, and described the
During two-step annealing, annealing temperature remains first preset temperature.
Wherein, the plasma state atmosphere of the reducibility gas be include based on reducibility gas generate plasma
Atmosphere.
Specifically, plasma is one kind by free electron and charged ion physical form as main component, is deposited extensively
It is in universe, is often considered to be the 4th state for removing the outer substance of solid, liquid, gas, referred to as plasma state, or " super gaseous state ",
Also referred to as " plasma-based body ".More specifically, plasma is the gas of partial ionization, by electronics, ion, free radical, neutral particle
And photon composition, it is the electroneutral mixture containing physics and the active particle of chemistry in itself.
In specific implementation, these Active Radicals Produced particles can do chemical function, by be passed through reducibility gas it is equal from
Sub- state can preferably improve the quality of semiconductor substrate compared to reducibility gas is only passed through.
In embodiments of the present invention, can by external plasma generating apparatus be based on reducibility gas generate etc. from
Daughter, and then the plasma is inputted into annealing chamber to form the plasma state atmosphere of the reducibility gas.
Further, first step annealing and the second step annealing are carried out in annealing device, in the first step annealing
Before, the preparation method of the silicon wafer can also include: to be passed through inert gas into the annealing device to form indifferent gas
Atmosphere, and the annealing device is carried out to be warming up to the initial temperature；Atmosphere processing is carried out to the annealing device, with from described
Inert atmosphere is changed into the plasma state atmosphere of the reducibility gas.
Above-mentioned each step is illustrated below with reference to Fig. 3.Fig. 3 be in the embodiment of the present invention a kind of annealing temperature with moving back
The curve graph of fiery duration variation.
As shown in figure 3, stage A is passed through inert gas into the annealing device for indicating to form inert atmosphere, and
The annealing device is carried out to be warming up to the initial temperature.
Specifically, the inert gas can be selected from argon (Ar) gas, helium (He) gas, neon (Ne) gas, krypton (Kr) gas and xenon
(Xe) gas.The initial temperature (the corresponding annealing temperature of a point in as Fig. 3) can be 400 DEG C to 700 DEG C.
Preferably, the inert gas can be argon gas, and the initial temperature can be 600 DEG C.
Further, warm-up time can be set to 30min.
In embodiments of the present invention, before the first step annealing, by be passed through into the annealing device inert gas with
Inert atmosphere is formed, can be avoided existing in annealing device using the air and oxygen in inert gas discharge annealing device
Air has an impact sequential reduction reaction, and when reducibility gas is hydrogen, avoids causing to endanger due to oxyhydrogen reaction
Production security is improved in danger.
In embodiments of the present invention, when being passed through inert gas, the annealing device is carried out to be warming up to the starting temperature
Degree helps to reduce production cost, improves production efficiency.Specifically, reducibility gas is easier to silicon wafer under the high temperature conditions
The oxide layer on surface and the oxide film of interior void are restored, therefore it is unfavorable to be passed through reducibility gas under cryogenic
In control production cost.
Further, at a point, the preparation method of the silicon wafer further includes carrying out atmosphere processing to the annealing device,
The step of plasma state atmosphere to be changed into the reducibility gas from the inert atmosphere.
In embodiments of the present invention, by being passed through the plasma of reducibility gas, to form reduction in annealing device
The plasma state atmosphere of property gas, helps to realize and goes back to the oxide layer of silicon chip surface and the oxide film of interior void
It is former.
Preferably, hydrogen (H can be used2) it is used as reducibility gas, to form the plasma state atmosphere of reducibility gas.
Specifically, since the by-product that hydrogen is formed is H2O is easy to be evaporated discharge by modes such as high temperature, and does not influence silicon wafer
Quality.
It should be pointed out that other reducibility gas appropriate, such as carbon monoxide (CO) are also an option that, in the present invention
In embodiment, for specific reducibility gas selection with no restriction.
Stage B is for indicating the first step annealing.Specifically, under the plasma state atmosphere of reducibility gas, to silicon wafer
Carry out the first step annealing, during first step annealing, annealing temperature rises to the first preset temperature from initial temperature.
In specific implementation, the plasma state atmosphere of the reducibility gas be include to be generated based on reducibility gas
The atmosphere of plasma.
The forming step of the plasma state atmosphere of the reducibility gas may include: to be generated based on the reducibility gas
Then plasma is passed through inert gas and the plasma into the annealing device, to form the reproducibility gas
The plasma state atmosphere of body, wherein the plasma state atmosphere of the reducibility gas be include inert gas and it is described it is equal from
The atmosphere of the mixture of daughter；Alternatively, generating plasma based on the reducibility gas, then lead into the annealing device
Enter the plasma, and the inert gas being discharged in the annealing device, with formed the reducibility gas it is equal from
Sub- state atmosphere, wherein the plasma state atmosphere of the reducibility gas is the atmosphere for only including the plasma.
Specifically, can continue to be passed through reducibility gas into annealing device on the basis of stage A is passed through inert gas
Plasma, with formed include inert gas and the plasma mixture atmosphere；It can also be passed through in stage A
On the basis of inert gas, it is passed through the plasma of reducibility gas in Xiang Suoshu annealing device, and inert gas is discharged, with shape
At the atmosphere for only including the plasma.
Wherein, the step of inert gas is discharged can be discharged using air pump, be replaced in annealing device quickly with reaching
The effect of gas.
Further, first preset temperature (the corresponding annealing temperature of b point in as Fig. 3) can be for 850 DEG C extremely
1200℃。
Stage C is for indicating the second step annealing.Specifically, under the plasma state atmosphere of reducibility gas, to described
Silicon wafer carries out the second step annealing, and during second step annealing, annealing temperature remains first preset temperature.
Specifically, the inner wall of Crystal Originated Particle defect (namely empty type microdefect) forms oxide film after being oxidized,
It can preferably be reduced in a reducing atmosphere and be decomposed into interstitial oxygen concentration and be diffused into outside silicon wafer；When exceeding certain temperature,
The atom of silicon chip surface spontaneously can be diffused into the low place of energy from the high place of energy, i.e., flow to from " protrusion " on surface
In " pit " on surface, surface is made to become smooth, reduces the microroughness on surface, and then since interstitial silicon atoms are filled to crystalline substance
In cavity caused by body primary partical defect, even disappear so that Crystal Originated Particle defect is reduced.
In specific implementation, first preset temperature should not be arranged too low, otherwise be difficult to go back oxide film
Original is decomposed；First preset temperature should not be arranged excessively high, otherwise will affect silicon wafer quality, and then influence to be formed partly leads
Body device.
As a unrestricted example, the first preset temperature (b point and corresponding annealing of c point in as Fig. 3
Temperature) it can be 850 DEG C to 1200 DEG C.Preferably, first preset temperature can be 1050 DEG C to 1150 DEG C.
It should be pointed out that in embodiments of the present invention, due to including the plasma generated based on reducibility gas
Reducibility gas plasma state atmosphere have stronger reproducibility, facilitate in lower reduction temperature, shorter reduction
Realize better reduction effect under duration, thus first preset temperature can be set it is lower, to reduce production cost,
Improve production efficiency.
In specific implementation, the anneal duration of second step annealing should not be arranged too short, otherwise be difficult to make to aoxidize
Film is reduced decomposition；The anneal duration of second step annealing should not be arranged too long, otherwise will affect silicon wafer quality, into
And influence the semiconductor devices formed.
As a unrestricted example, the anneal duration of second step annealing be can be set to 20 minutes to 90 points
Clock.Preferably, the anneal duration of second step annealing can be set to 40 minutes to 60 minutes.
It should be pointed out that in embodiments of the present invention, due to including the plasma generated based on reducibility gas
Reducibility gas plasma state atmosphere have stronger reproducibility, facilitate in lower reduction temperature, shorter reduction
Realize better reduction effect under duration, thus the anneal duration of second step annealing can be set it is shorter, to reduce
Production cost improves production efficiency.
In embodiments of the present invention, by carrying out second to the silicon wafer under the plasma state atmosphere of reducibility gas
Step annealing, during second step annealing, annealing temperature remains first preset temperature, not only can be to silicon wafer table
The oxide layer in face carries out reduction reaction, can also the oxide film in the cavity to silicon wafer inside certain depth restore it is anti-
It answers, so as to more effectively reduce the empty type microdefect in the silicon wafer, and the lattice defect in silicon wafer is carried out more
It is effective to repair.
Further, at c point, the preparation method of the silicon wafer further includes being passed through indifferent gas into the annealing device
Body, and the plasma in the annealing device is discharged, the step of to form inert atmosphere.
It in embodiments of the present invention, further include forming inert atmosphere before carrying out third step annealing to the silicon wafer
Step, can be to avoid in subsequent taking-up silicon wafer, and since reducibility gas encounters, explosion occurs for the oxygen in air or generation is dangerous
Gas (such as CO2Or superheated vapor), the personal safety of operator is had an impact, to help to improve production safety
Property.
Wherein, the step of plasma is discharged can be discharged using air pump, be replaced in annealing device quickly with reaching
The effect of gas.
Stage D is for indicating third step annealing.Specifically, third step annealing is carried out to the silicon wafer, in the third
During step annealing, annealing temperature drops to the second preset temperature from first preset temperature.
Specifically, second preset temperature (the corresponding annealing temperature of d point in as Fig. 3) can be 400 DEG C to 700
℃.Preferably, second preset temperature can be 500 DEG C to 600 DEG C.
In embodiments of the present invention, by carrying out third step annealing, the temperature in annealing device can be reduced, thus rear
When continuous taking-up silicon wafer, the danger generated due to high temperature to operator is reduced, to improve production security.
In embodiments of the present invention, by carrying out second to the silicon wafer under the plasma state atmosphere of reducibility gas
Step annealing, during second step annealing, annealing temperature remains first preset temperature, not only can be to silicon wafer table
The oxide layer in face carries out reduction reaction, can also the oxide film in the cavity to silicon wafer inside certain depth restore it is anti-
It answers, so as to efficiently reduce the empty type microdefect in the silicon wafer, and is more had to the lattice defect in silicon wafer
The reparation of effect improves the quality of silicon wafer so that the mist for reducing silicon chip surface is all worth.Further, compared to only include reduction
Property gas reducing atmosphere, due to include based on reducibility gas generate plasma reducibility gas plasma state
Atmosphere has stronger reproducibility, helps to realize preferably reduction effect under lower reduction temperature, shorter reduction duration
Fruit improves production efficiency to help to reduce production cost.Further, it does not need to increase extra process, reduce
Production efficiency is improved while production cost, is suitble to large-scale production.
It is the curve graph that another annealing temperature changes with anneal duration in the embodiment of the present invention referring to Fig. 4, Fig. 4.
In stage B shown in Fig. 4 namely the first step annealing may include multiple annealing stages, such as stage B1 and stage
B2, the heating rate of posterior annealing stage are less than the heating rate of first annealing stage namely the heating curve of stage B2
Slope lower than stage B1 heating curve slope.
Specifically, be warming up to medium temperature (i.e. e in Fig. 4 to the annealing device using the first heating speed
The corresponding annealing temperature of point), then the annealing device is carried out using the second heating rate to be warming up to the described first default temperature
It spends (the corresponding annealing temperature of b point in as Fig. 4), wherein the first heating speed is greater than second heating rate.
In specific implementation, heating rate is slower, and the temperature at silicon chip edge and center is closer, reducibility gas and oxidation
Also more uniform, silicon chip edge (Wafer Edge) and the silicon wafer center (Wafer that the chemical reaction of layer and oxide film carries out
Center resistance uniformity) is also better, helps to improve the quality of silicon wafer.
As a unrestricted example, it is 4 DEG C/min to 6 DEG C/min that the first heating speed, which can be set, excellent
It is selected as 5 DEG C/min；It is 2 DEG C/min to 4 DEG C/min, preferably 3 DEG C/min that second heating rate, which can be set,.
In embodiments of the present invention, first step annealing includes multiple annealing stages, the heating of posterior annealing stage
Speed is less than the heating rate of first annealing stage, can be by improving heating rate in low-temperature space, to reach default as early as possible
Temperature reduces heating rate in high-temperature region, to improve the temperature consistency of silicon chip edge Yu silicon wafer center, to improve in silicon wafer
The consistency of the reduction reaction at edge and silicon wafer center.
In specific implementation, more detailed contents in relation to stage A, stage C and stage D referring to figure 3. in stage
A, the description of stage C and stage D are executed, and details are not described herein again.
It is that a kind of silicon wafer is bent from a surface to the corresponding resistivity of internal different depth in the embodiment of the present invention referring to Fig. 5, Fig. 5
Line chart.
As shown, silicon wafer is after the preparation method using the embodiment of the present invention, the distance away from silicon chip surface is by closely extremely
Far, resistivity has preferable consistency, and away from the closer region of silicon chip surface, resistivity is higher than silicon in the prior art
Piece helps to improve the quality in the source and drain doping area being subsequently formed so that insulating properties is preferable.
It should be pointed out that the curve graph tests silicon wafer after annealing using appearance-voltage method (C-V method), having
It, can also be using silicon wafer different depth after spreading resistance method (SRP method) test annealing, to obtain resistivity curve during body is implemented
Figure.
Referring to Fig. 6, Fig. 6 is a kind of structural schematic diagram of the preparation facilities of silicon wafer in the embodiment of the present invention.
The preparation facilities of the silicon wafer may include: plasma generating apparatus 120, for being generated based on reducibility gas
Plasma；Annealing device, the annealing device may include: annealing chamber 100；Wafer susceptor 110, the wafer susceptor
110 are located in the annealing chamber 100, and for placing wafer；Plasma intake line 122 is used for the anneal chamber
The input plasma in room 100.
Wherein, the plasma generating apparatus 120 can be external device, and the plasma generated passes through described etc.
Gas ions intake line 122 is transmitted to the annealing chamber 100, to form reducibility gas in the annealing chamber 100
Plasma state atmosphere.
Further, the preparation facilities of the silicon wafer can also include: inert gas input pipe road 132, be used for institute
It states in annealing chamber 100 and inputs inert gas；Gas export line 142, it is described etc. for being exported out of described annealing chamber 100
Gas ions and/or the inert gas；The pump housing 150, the pump housing 150 can connect with the gas export line 142, be used for
The plasma and/or the inert gas are extracted out of described annealing chamber 100.
Wherein, the pump housing 150 can be cold pump or mechanical pump.
In the present invention is implemented, by the way that the pump housing 150 is arranged, help preferably to extract out of described annealing chamber 100
The plasma and/or the inert gas, to improve the degree of purity of substance in the annealing chamber 100.
In embodiments of the present invention, by the way that the preparation facilities of the silicon wafer is arranged, may be implemented reducibility gas etc.
Under ionic state atmosphere, the second step annealing is carried out to the silicon wafer, thus thin to the oxidation in the cavity of silicon wafer inside certain depth
Film carries out reduction reaction, so as to efficiently reduce the empty type microdefect in the silicon wafer, and to the lattice in silicon wafer
Defect is more effectively repaired, so that the mist for reducing silicon chip surface is all worth, improves the quality of silicon wafer.
Principle, specific implementation and the beneficial effect of preparation facilities about the silicon wafer please refer to above and Fig. 2 to Fig. 5 is shown
The preparation method about silicon wafer associated description, details are not described herein again.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (13)
1. a kind of preparation method of silicon wafer characterized by comprising
Under the plasma state atmosphere of reducibility gas, the first step annealing is carried out to silicon wafer, during first step annealing,
Annealing temperature rises to the first preset temperature from initial temperature；
Under the plasma state atmosphere of reducibility gas, the second step annealing, the mistake of second step annealing are carried out to the silicon wafer
Cheng Zhong, annealing temperature remain first preset temperature；
Wherein, the plasma state atmosphere of the reducibility gas is the gas for including the plasma generated based on reducibility gas
Atmosphere.
2. the preparation method of silicon wafer according to claim 1, which is characterized in that first step annealing and the second step annealing
It is to be carried out in annealing device, before the first step annealing, further includes:
Inert gas is passed through into the annealing device to form inert atmosphere, and described in being warming up to the annealing device
Initial temperature；
Atmosphere processing is carried out to the annealing device, to be changed into the plasma state of the reducibility gas from the inert atmosphere
Atmosphere.
3. the preparation method of silicon wafer according to claim 1, which is characterized in that after second step annealing, also wrap
It includes:
Third step annealing is carried out to the silicon wafer, in the third step annealing process, annealing temperature is default warm from described first
Degree drops to the second preset temperature.
4. the preparation method of silicon wafer according to claim 3, which is characterized in that second preset temperature be 400 DEG C extremely
700℃。
5. the preparation method of silicon wafer according to claim 3, which is characterized in that first step annealing, the second step annealing
With third step annealing carried out in annealing device, carry out second step annealing and carry out the third step annealing it
Between, further includes:
It is passed through inert gas into the annealing device, and the plasma in the annealing device is discharged, it is lazy to be formed
Property atmosphere.
6. the preparation method of silicon wafer according to claim 1, which is characterized in that first step annealing and the second step annealing
It is to be carried out in annealing device, the forming step of the plasma state atmosphere of the reducibility gas includes:
Plasma is generated based on the reducibility gas, inert gas and described etc. is then passed through into the annealing device
Gas ions, to form the plasma state atmosphere of the reducibility gas, wherein the plasma state atmosphere of the reducibility gas is
It include the atmosphere of the mixture of inert gas and the plasma；
Alternatively,
Plasma is generated based on the reducibility gas, the plasma is then passed through into the annealing device,
And the inert gas in the annealing device is discharged, to form the plasma state atmosphere of the reducibility gas, wherein described to go back
The plasma state atmosphere of originality gas is the atmosphere for only including the plasma.
7. the preparation method of silicon wafer according to claim 1, which is characterized in that the reducibility gas is hydrogen.
8. the preparation method of silicon wafer according to claim 1, which is characterized in that first preset temperature be 850 DEG C extremely
1200℃。
9. the preparation method of silicon wafer according to claim 1, which is characterized in that the initial temperature is 400 DEG C to 700
℃。
10. the preparation method of silicon wafer according to claim 1, which is characterized in that first step annealing includes multiple moves back
Fiery stage, the heating rate of posterior annealing stage are less than the heating rate of first annealing stage.
11. the preparation method of silicon wafer according to claim 1, which is characterized in that the anneal duration of second step annealing
It is 20 minutes to 90 minutes.
12. a kind of preparation facilities of silicon wafer characterized by comprising
Plasma generating apparatus, for generating plasma based on reducibility gas；
Annealing device, the annealing device include:
Annealing chamber；
Wafer susceptor, the wafer susceptor are located in the anneal chamber room, and for placing wafer；
Plasma intake line, for inputting the plasma into the anneal chamber room.
13. the preparation facilities of silicon wafer according to claim 12, which is characterized in that further include:
Inert gas input pipe road, for inputting inert gas into the anneal chamber room；
Gas export line, for exporting the plasma and/or the inert gas out of described anneal chamber room；
The pump housing, the pump housing are connect with the gas export line, for extracting the plasma out of described anneal chamber room
Body and/or the inert gas.
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| US20030089967A1 (en) * | 2001-11-12 | 2003-05-15 | Young-Hee Mun | Silicon wafer and fabricating method therefor |
| CN101829485A (en) * | 2010-04-30 | 2010-09-15 | 武汉工程大学 | Method for desorbing sulfur dioxide in industrial exhaust gas utilizing barometric pressure microwave jet plasma technology |
| CN103820862A (en) * | 2012-11-16 | 2014-05-28 | 有研半导体材料股份有限公司 | Method for preparing high-temperature annealing silicon wafer |
| CN105745740A (en) * | 2013-09-17 | 2016-07-06 | 应用材料公司 | Methods for stabilizing an interface post etch to minimize queue time issues before next processing step |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20030089967A1 (en) * | 2001-11-12 | 2003-05-15 | Young-Hee Mun | Silicon wafer and fabricating method therefor |
| CN101829485A (en) * | 2010-04-30 | 2010-09-15 | 武汉工程大学 | Method for desorbing sulfur dioxide in industrial exhaust gas utilizing barometric pressure microwave jet plasma technology |
| CN103820862A (en) * | 2012-11-16 | 2014-05-28 | 有研半导体材料股份有限公司 | Method for preparing high-temperature annealing silicon wafer |
| CN105745740A (en) * | 2013-09-17 | 2016-07-06 | 应用材料公司 | Methods for stabilizing an interface post etch to minimize queue time issues before next processing step |
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