CN109166799A - The preparation method of silicon wafer - Google Patents
The preparation method of silicon wafer Download PDFInfo
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- CN109166799A CN109166799A CN201811032687.1A CN201811032687A CN109166799A CN 109166799 A CN109166799 A CN 109166799A CN 201811032687 A CN201811032687 A CN 201811032687A CN 109166799 A CN109166799 A CN 109166799A
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 128
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 127
- 239000010703 silicon Substances 0.000 title claims abstract description 127
- 238000002360 preparation method Methods 0.000 title claims abstract description 29
- 238000000137 annealing Methods 0.000 claims abstract description 174
- 239000007789 gas Substances 0.000 claims description 57
- 239000011261 inert gas Substances 0.000 claims description 26
- 238000010438 heat treatment Methods 0.000 claims description 23
- 238000000034 method Methods 0.000 claims description 14
- 230000008569 process Effects 0.000 claims description 9
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 8
- 238000010792 warming Methods 0.000 claims description 7
- UGFAIRIUMAVXCW-UHFFFAOYSA-N Carbon monoxide Chemical compound [O+]#[C-] UGFAIRIUMAVXCW-UHFFFAOYSA-N 0.000 claims description 5
- 229910002091 carbon monoxide Inorganic materials 0.000 claims description 5
- 239000001257 hydrogen Substances 0.000 claims description 5
- 229910052739 hydrogen Inorganic materials 0.000 claims description 5
- 229910052786 argon Inorganic materials 0.000 claims description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 claims description 3
- 239000001307 helium Substances 0.000 claims description 3
- 229910052734 helium Inorganic materials 0.000 claims description 3
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 claims description 3
- 229910052743 krypton Inorganic materials 0.000 claims description 3
- DNNSSWSSYDEUBZ-UHFFFAOYSA-N krypton atom Chemical compound [Kr] DNNSSWSSYDEUBZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052754 neon Inorganic materials 0.000 claims description 3
- GKAOGPIIYCISHV-UHFFFAOYSA-N neon atom Chemical compound [Ne] GKAOGPIIYCISHV-UHFFFAOYSA-N 0.000 claims description 3
- 229910052724 xenon Inorganic materials 0.000 claims description 3
- FHNFHKCVQCLJFQ-UHFFFAOYSA-N xenon atom Chemical compound [Xe] FHNFHKCVQCLJFQ-UHFFFAOYSA-N 0.000 claims description 3
- 235000012431 wafers Nutrition 0.000 claims 15
- 230000007547 defect Effects 0.000 abstract description 11
- 239000003595 mist Substances 0.000 abstract description 6
- 238000006722 reduction reaction Methods 0.000 description 13
- 239000010408 film Substances 0.000 description 11
- 238000004519 manufacturing process Methods 0.000 description 11
- 239000013078 crystal Substances 0.000 description 9
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 3
- 238000007254 oxidation reaction Methods 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 239000002245 particle Substances 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical group [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 239000006227 byproduct Substances 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000004140 cleaning Methods 0.000 description 2
- 239000000356 contaminant Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 150000002431 hydrogen Chemical class 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- 238000004220 aggregation Methods 0.000 description 1
- 230000002776 aggregation Effects 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 238000000354 decomposition reaction Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000407 epitaxy Methods 0.000 description 1
- 238000004880 explosion Methods 0.000 description 1
- 239000008246 gaseous mixture Substances 0.000 description 1
- 238000000227 grinding Methods 0.000 description 1
- 238000011031 large-scale manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000008439 repair process Effects 0.000 description 1
- 238000004857 zone melting Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
- H01L21/3247—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering for altering the shape, e.g. smoothing the surface
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Crystals, And After-Treatments Of Crystals (AREA)
Abstract
A kind of preparation method of silicon wafer, the preparation method of the silicon wafer include: to carry out the first step annealing to silicon wafer under reducing atmosphere, and during first step annealing, annealing temperature rises to the first preset temperature from initial temperature；The second step annealing is carried out to the silicon wafer under the reducing atmosphere, during second step annealing, annealing temperature remains first preset temperature；Wherein, the reducing atmosphere is the atmosphere for including reducibility gas.The empty type microdefect in the silicon wafer can be effectively reduced in the present invention program, and is more effectively repaired to the lattice defect in silicon wafer, so that the mist for reducing silicon chip surface is all worth, improves the quality of silicon wafer.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors more particularly to a kind of preparation methods of silicon wafer.
Background technique
In prior art, silicon single crystal ingot usually is obtained using vertical pulling method or zone-melting process, then to the silicon single crystal ingot
The techniques such as wire cutting, grinding, polishing, cleaning are carried out, to obtain silicon wafer.
However during growing crystal, since the aggregation in vacancy will form empty type microdefect, i.e. crystal primary sound grain
Sub- defect is easily reduced the integrality (Gate Oxide Integrity, GOI) of MOS device gate oxide, is furthermore easy changing
Learn the mist degree for leading to silicon chip surface in mechanical polishing (Chemical Mechanical Polishing, CMP) technical process
(Haze) value is higher.
In the prior art, it generallys use extension (Epitaxy, EPI) layer process and grows one layer on the surface of the silicon wafer
The epitaxial film of identical crystal orientation, to reduce the empty type microdefect and reduce the haze value of silicon chip surface, however EPI technique volume
A large amount of processing steps are increased outside, reduce production efficiency and seriously increase cost.
Summary of the invention
The technical problem to be solved by the present invention is to provide a kind of preparation methods of silicon wafer, can be effectively reduced in the silicon wafer
Empty type microdefect, and the lattice defect in silicon wafer is more effectively repaired, to reduce the mist of silicon chip surface all
Value, improves the quality of silicon wafer.
In order to solve the above technical problems, the embodiment of the present invention provides a kind of preparation method of silicon wafer, comprising: in reducing atmosphere
Under the first step annealing is carried out to silicon wafer, during first step annealing, it is pre- that annealing temperature from initial temperature rises to first
If temperature；The second step annealing is carried out to the silicon wafer under the reducing atmosphere, during second step annealing, annealing temperature
Degree remains first preset temperature；Wherein, the reducing atmosphere is the atmosphere for including reducibility gas.
Optionally, first step annealing and the second step annealing are carried out in annealing device, the first step annealing it
Before, the preparation method of the silicon wafer further include: be passed through inert gas into the annealing device to form inert atmosphere, and to institute
Annealing device is stated to carry out being warming up to the initial temperature；Atmosphere processing is carried out to the annealing device, with from the inert atmosphere
It is changed into the reducing atmosphere.
Optionally, after second step annealing, the preparation method of the silicon wafer further include: the is carried out to the silicon wafer
Three-step annealing, in the third step annealing process, annealing temperature drops to the second preset temperature from first preset temperature.
Optionally, second preset temperature is 500 DEG C to 700 DEG C.
Optionally, first step annealing, the second step annealing and third step annealing are carried out in annealing device, into
Between row second step annealing and the progress third step annealing, the preparation method of the silicon wafer further include: to the annealing
The reducibility gas for being passed through inert gas in equipment, and being discharged in the annealing device, to form inert atmosphere.
Optionally, first step annealing and the second step annealing are carried out in annealing device, the reducing atmosphere
Forming step includes: that inert gas and reducibility gas are passed through into the annealing device, to form the reducing atmosphere,
In, the reducing atmosphere be include inert gas and reducibility gas mixed gas atmosphere；Alternatively, being set to the annealing
The standby interior inert gas for being passed through the reducibility gas, and being discharged in the annealing device, to form the reducing atmosphere,
In, the reducing atmosphere is the atmosphere for only including the reducibility gas.
Optionally, the inert gas is selected from argon gas, helium, neon, Krypton and xenon.
Optionally, the reducibility gas is selected from: hydrogen and carbon monoxide.
Optionally, first preset temperature is 1000 DEG C to 1200 DEG C.
Optionally, the initial temperature is 500 DEG C to 700 DEG C.
Optionally, first step annealing includes multiple annealing stages, and the heating rate of posterior annealing stage is less than
The heating rate of first annealing stage.
Optionally, the anneal duration of second step annealing is 30 minutes to 90 minutes.
Compared with prior art, the technical solution of the embodiment of the present invention has the advantages that
In embodiments of the present invention, the first step annealing, the mistake of first step annealing are carried out to silicon wafer under reducing atmosphere
Cheng Zhong, annealing temperature rise to the first preset temperature from initial temperature；Second is carried out to the silicon wafer under the reducing atmosphere
Step annealing, during second step annealing, annealing temperature remains first preset temperature；Wherein, the also Primordial Qi
Atmosphere is the atmosphere for including reducibility gas.Using the above scheme, by under reducing atmosphere, to institute under the reducing atmosphere
It states silicon wafer and carries out the second step annealing, during second step annealing, annealing temperature remains first preset temperature, no
Only reduction reaction can be carried out to the oxide layer of silicon chip surface, can also oxidation in the cavity to silicon wafer inside certain depth it is thin
Film carries out reduction reaction, so as to efficiently reduce the empty type microdefect in the silicon wafer, and to the lattice in silicon wafer
Defect is more effectively repaired, so that the mist for reducing silicon chip surface is all worth, improves the quality of silicon wafer.
Further, before carrying out third step annealing to the silicon wafer, further include the steps that forming inert atmosphere, can keep away
Exempt from influence of the reducing atmosphere to operator, improves production security.
Further, first step annealing includes multiple annealing stages, and the heating rate of posterior annealing stage is less than
The heating rate of first annealing stage, can be by improving heating rate in low-temperature space, to reach preset temperature as early as possible, in high temperature
Area reduces heating rate, to improve the temperature consistency of silicon chip edge Yu silicon wafer center, to improve in silicon chip edge and silicon wafer
The consistency of the reduction reaction at center.
Detailed description of the invention
Fig. 1 be in the prior art a kind of silicon wafer from a surface to the corresponding resistivity curve figure of internal different depth；
Fig. 2 is a kind of flow chart of the preparation method of silicon wafer in the embodiment of the present invention；
Fig. 3 is a kind of curve graph that annealing temperature changes with anneal duration in the embodiment of the present invention；
Fig. 4 is the curve graph that another annealing temperature changes with anneal duration in the embodiment of the present invention；
Fig. 5 be in the embodiment of the present invention a kind of silicon wafer from a surface to the corresponding resistivity curve figure of internal different depth.
Specific embodiment
In the technology of existing growth crystal, the haze value of oxide layer easy to form and silicon chip surface is higher.
Specifically, silicon wafer cleaning storing process in, surface oxide layer easy to form, so in annealing oxide layer hold
It easily adsorbs annealing device (such as furnace body) or closes on the impurity (such as boron atom) of silicon wafer.And then the impurity (such as boron is former
Son) it penetrates readily through oxide layer and then is diffused into silicon chip surface region, lead to the reduction of silicon chip surface resistance value.
Fig. 1 be in the prior art a kind of silicon wafer from a surface to the corresponding resistivity curve figure of internal different depth.
As shown in Figure 1, the distance away from silicon chip surface is closer, being influenced by the impurity that oxide layer is adsorbed, resistivity is lower,
Resistivity is inconsistent in from silicon chip surface to the preset range of inside, and lower resistivity causes insulating properties to reduce, and easy pair
The source and drain doping area being subsequently formed has an impact.
The present inventor has found after study, in the prior art, is not only easy to form oxide layer in silicon chip surface,
And then adsorbing contaminant, further also it is micro- scarce to form a large amount of empty types inside a certain range of silicon wafer apart from silicon chip surface
It falls into, i.e. Crystal Originated Particle defect, is also oxidized easily in the cavity type microdefect, and then form very thin oxide film
And adsorbing contaminant further results in silicon chip surface resistance value since the oxide film in empty type microdefect is difficult to remove
Reduction and the higher problem of haze value.
In embodiments of the present invention, the first step annealing, the mistake of first step annealing are carried out to silicon wafer under reducing atmosphere
Cheng Zhong, annealing temperature rise to the first preset temperature from initial temperature；Second is carried out to the silicon wafer under the reducing atmosphere
Step annealing, during second step annealing, annealing temperature remains first preset temperature；Wherein, the also Primordial Qi
Atmosphere is the atmosphere for including reducibility gas.Using the above scheme, by under reducing atmosphere, to institute under the reducing atmosphere
It states silicon wafer and carries out the second step annealing, during second step annealing, annealing temperature remains first preset temperature, no
Only reduction reaction can be carried out to the oxide layer of silicon chip surface, can also oxidation in the cavity to silicon wafer inside certain depth it is thin
Film carries out reduction reaction, so as to more effectively reduce the empty type microdefect in the silicon wafer, and to the crystalline substance in silicon wafer
Lattice defect is more effectively repaired, so that the mist for reducing silicon chip surface is all worth, improves the quality of silicon wafer.
It is understandable to enable above-mentioned purpose of the invention, feature and beneficial effect to become apparent, with reference to the accompanying drawing to this
The specific embodiment of invention is described in detail.
Referring to Fig. 2, Fig. 2 is a kind of flow chart of the preparation method of silicon wafer in the embodiment of the present invention.The preparation of the silicon wafer
Method may include step S21 and step S22:
Step S21: carrying out the first step annealing to silicon wafer under reducing atmosphere, during first step annealing, annealing
Temperature rises to the first preset temperature from initial temperature；
Step S22: the second step annealing, the process of second step annealing are carried out to the silicon wafer under the reducing atmosphere
In, annealing temperature remains first preset temperature；
Wherein, the reducing atmosphere is the atmosphere for including reducibility gas.
Further, first step annealing and the second step annealing are carried out in annealing device, in the first step annealing
Before, the preparation method of the silicon wafer can also include: to be passed through inert gas into the annealing device to form indifferent gas
Atmosphere, and the annealing device is carried out to be warming up to the initial temperature；Atmosphere processing is carried out to the annealing device, with from described
Inert atmosphere is changed into the reducing atmosphere.
Above-mentioned each step is illustrated below with reference to Fig. 3.Fig. 3 be in the embodiment of the present invention a kind of annealing temperature with moving back
The curve graph of fiery duration variation.
As shown in figure 3, stage A is passed through inert gas into the annealing device for indicating to form inert atmosphere, and
The annealing device is carried out to be warming up to the initial temperature.
Specifically, the inert gas can be selected from argon (Ar) gas, helium (He) gas, neon (Ne) gas, krypton (Kr) gas and xenon
(Xe) gas.The initial temperature (the corresponding annealing temperature of a point in as Fig. 3) can be 500 DEG C to 700 DEG C.
Preferably, the inert gas can be argon gas, and the initial temperature can be 600 DEG C.
Further, warm-up time can be set to 30min.
In embodiments of the present invention, before the first step annealing, by be passed through into the annealing device inert gas with
Inert atmosphere is formed, can be avoided existing in annealing device using the air and oxygen in inert gas discharge annealing device
Air has an impact sequential reduction reaction, and when reducibility gas is hydrogen, avoids causing to endanger due to oxyhydrogen reaction
Production security is improved in danger.
In embodiments of the present invention, when being passed through inert gas, the annealing device is carried out to be warming up to the starting temperature
Degree helps to reduce production cost, improves production efficiency.Specifically, reducibility gas is easier to silicon wafer under the high temperature conditions
The oxide layer on surface and the oxide film of interior void are restored, therefore it is unfavorable to be passed through reducibility gas under cryogenic
In control production cost.
Further, at a point, the preparation method of the silicon wafer further includes carrying out atmosphere processing to the annealing device,
With the step of being changed into the reducing atmosphere from the inert atmosphere.
In embodiments of the present invention, by being passed through reducibility gas, to form reducing atmosphere in annealing device, facilitate
Realization restores the oxide layer of silicon chip surface and the oxide film of interior void.
Further, the reducibility gas can be selected from: hydrogen (H) gas and carbon monoxide (CO).
In specific implementation, using hydrogen as reducibility gas, the by-product of formation is H2O is easy through high temperature etc.
Mode is evaporated discharge, and does not influence the quality of silicon wafer；Using CO as reducibility gas, the by-product of formation is CO2, it is easy
It is discharged and does not influence the quality of silicon wafer.
It should be pointed out that other reducibility gas appropriate are also an option that, in embodiments of the present invention, for specific
Reducibility gas selection with no restriction.
Stage B is for indicating the first step annealing.Specifically, carrying out the first step annealing, institute to silicon wafer under reducing atmosphere
During stating the first step annealing, annealing temperature rises to the first preset temperature from initial temperature.
In specific implementation, the reducing atmosphere can be the atmosphere for including reducibility gas.
The forming step of the reducing atmosphere may include: that inert gas and reproducibility are passed through into the annealing device
Gas, to form the reducing atmosphere, wherein the reducing atmosphere is the gaseous mixture for including inert gas and reducibility gas
The atmosphere of body；Alternatively, the indifferent gas for being passed through the reducibility gas into the annealing device, and being discharged in the annealing device
Body, to form the reducing atmosphere, wherein the reducing atmosphere is the atmosphere for only including the reducibility gas.
Specifically, can continue to be passed through reproducibility gas into annealing device on the basis of stage A is passed through inert gas
Body includes the atmosphere of the mixed gas of inert gas and reducibility gas with formation；Inert gas can also be passed through in stage A
On the basis of, it is passed through reducibility gas into the annealing device, and inert gas is discharged, only includes the reduction to be formed
The atmosphere of property gas.
Wherein, the step of inert gas is discharged can be discharged using air pump, be replaced in annealing device quickly with reaching
The effect of gas.
Further, first preset temperature (the corresponding annealing temperature of b point in as Fig. 3) can be for 1000 DEG C extremely
1200℃。
Stage C is for indicating the second step annealing.Specifically, carrying out second step to the silicon wafer under the reducing atmosphere
It anneals, during second step annealing, annealing temperature remains first preset temperature.
Specifically, the inner wall of Crystal Originated Particle defect (namely empty type microdefect) forms oxide film after being oxidized,
It can preferably be reduced in a reducing atmosphere and be decomposed into interstitial oxygen concentration and be diffused into outside silicon wafer；When exceeding certain temperature,
The atom of silicon chip surface spontaneously can be diffused into the low place of energy from the high place of energy, i.e., flow to from " protrusion " on surface
In " pit " on surface, surface is made to become smooth, reduces the microroughness on surface, and then since interstitial silicon atoms are filled to crystalline substance
In cavity caused by body primary partical defect, even disappear so that Crystal Originated Particle defect is reduced.
In specific implementation, first preset temperature should not be arranged too low, otherwise be difficult to go back oxide film
Original is decomposed；First preset temperature should not be arranged excessively high, otherwise will affect silicon wafer quality, and then influence to be formed partly leads
Body device.
As a unrestricted example, the first preset temperature (b point and corresponding annealing of c point in as Fig. 3
Temperature) it can be 1000 DEG C to 1200 DEG C.Preferably, first preset temperature can be 1100 DEG C to 1150 DEG C.
In specific implementation, the anneal duration of second step annealing should not be arranged too short, otherwise be difficult to make to aoxidize
Film is reduced decomposition；The anneal duration of second step annealing should not be arranged too long, otherwise will affect silicon wafer quality, into
And influence the semiconductor devices formed.
As a unrestricted example, the anneal duration of second step annealing be can be set to 30 minutes to 90 points
Clock.Preferably, the anneal duration of second step annealing can be set to 50 minutes to 60 minutes.
In embodiments of the present invention, by under reducing atmosphere, carrying out second to the silicon wafer under the reducing atmosphere
Step annealing, during second step annealing, annealing temperature remains first preset temperature, not only can be to silicon wafer table
The oxide layer in face carries out reduction reaction, can also the oxide film in the cavity to silicon wafer inside certain depth restore it is anti-
It answers, so as to more effectively reduce the empty type microdefect in the silicon wafer, and the lattice defect in silicon wafer is carried out more
It is effective to repair.
Further, at c point, the preparation method of the silicon wafer further includes being passed through indifferent gas into the annealing device
Body, and the reducibility gas being discharged in the annealing device, the step of to form inert atmosphere.
It in embodiments of the present invention, further include forming inert atmosphere before carrying out third step annealing to the silicon wafer
Step, can be to avoid in subsequent taking-up silicon wafer, and since reducibility gas encounters, explosion occurs for the oxygen in air or generation is dangerous
Gas (such as CO2Or superheated vapor), the personal safety of operator is had an impact, to help to improve production safety
Property.
Wherein, the step of reducibility gas is discharged can be discharged using air pump, be replaced in annealing device quickly with reaching
Gas effect.
Stage D is for indicating third step annealing.Specifically, in the third step annealing process, annealing temperature is from institute
It states the first preset temperature and drops to the second preset temperature.
Specifically, second preset temperature (the corresponding annealing temperature of d point in as Fig. 3) can be 500 DEG C to 700
℃.Preferably, second preset temperature can be 600 DEG C.
In embodiments of the present invention, by carrying out third step annealing, the temperature in annealing device can be reduced, thus rear
When continuous taking-up silicon wafer, the danger generated due to high temperature to operator is reduced, to improve production security.
In embodiments of the present invention, not only reduction reaction can be carried out to the oxide layer of silicon chip surface, it can also be to silicon wafer
Oxide film in the cavity of internal certain depth carries out reduction reaction, so as to more effectively reduce the sky in the silicon wafer
Hole type microdefect, and the lattice defect in silicon wafer is more effectively repaired, so that the mist for reducing silicon chip surface is all worth, mention
The quality of high silicon wafer.Further, it does not need to increase extra process, improves production efficiency while reducing production cost,
It is suitble to large-scale production.
It is the curve graph that another annealing temperature changes with anneal duration in the embodiment of the present invention referring to Fig. 4, Fig. 4.
In stage B shown in Fig. 4 namely the first step annealing may include multiple annealing stages, such as stage B1 and stage
B2, the heating rate of posterior annealing stage are less than the heating rate of first annealing stage namely the heating curve of stage B2
Slope lower than stage B1 heating curve slope.
Specifically, be warming up to medium temperature (i.e. e in Fig. 4 to the annealing device using the first heating speed
The corresponding annealing temperature of point), then the annealing device is carried out using the second heating rate to be warming up to the described first default temperature
It spends (the corresponding annealing temperature of b point in as Fig. 4), wherein the first heating speed is greater than second heating rate.
In specific implementation, heating rate is slower, and the temperature at silicon chip edge and center is closer, reducibility gas and oxidation
Also more uniform, silicon chip edge (Wafer Edge) and the silicon wafer center (Wafer that the chemical reaction of layer and oxide film carries out
Center resistance uniformity) is also better, helps to improve the quality of silicon wafer.
As a unrestricted example, it is 4 DEG C/min to 6 DEG C/min that the first heating speed, which can be set, excellent
It is selected as 5 DEG C/min；It is 2 DEG C/min to 4 DEG C/min, preferably 3 DEG C/min that second heating rate, which can be set,.
In embodiments of the present invention, first step annealing includes multiple annealing stages, the heating of posterior annealing stage
Speed is less than the heating rate of first annealing stage, can be by improving heating rate in low-temperature space, to reach default as early as possible
Temperature reduces heating rate in high-temperature region, to improve the temperature consistency of silicon chip edge Yu silicon wafer center, to improve in silicon wafer
The consistency of the reduction reaction at edge and silicon wafer center.
In specific implementation, more detailed contents in relation to stage A, stage C and stage D referring to figure 3. in stage
A, the description of stage C and stage D are executed, and details are not described herein again.
It is that a kind of silicon wafer is bent from a surface to the corresponding resistivity of internal different depth in the embodiment of the present invention referring to Fig. 5, Fig. 5
Line chart.
Silicon wafer as shown in Figure 5 is after the preparation method using the embodiment of the present invention, and the distance away from silicon chip surface is by close
To remote, resistivity has preferable consistency, and away from the closer region of silicon chip surface, resistivity is higher than silicon in the prior art
Piece helps to improve the quality in the source and drain doping area being subsequently formed so that insulating properties is preferable.
Further, in a specific embodiment, silicon wafer surface haze value compared to the prior art after annealing
Average value reduces 52.6%, and peak value reduces 70.7%.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.
Claims (12)
1. a kind of preparation method of silicon wafer characterized by comprising
The first step annealing is carried out to silicon wafer under reducing atmosphere, during first step annealing, annealing temperature is from starting temperature
Degree rises to the first preset temperature；
The second step annealing, during second step annealing, annealing temperature are carried out to the silicon wafer under the reducing atmosphere
Remain first preset temperature；
Wherein, the reducing atmosphere is the atmosphere for including reducibility gas.
2. the preparation method of silicon wafer according to claim 1, which is characterized in that first step annealing and the second step annealing
It is to be carried out in annealing device, before the first step annealing, further includes:
Inert gas is passed through into the annealing device to form inert atmosphere, and described in being warming up to the annealing device
Initial temperature；
Atmosphere processing is carried out to the annealing device, to be changed into the reducing atmosphere from the inert atmosphere.
3. the preparation method of silicon wafer according to claim 1, which is characterized in that after second step annealing, also wrap
It includes:
Third step annealing is carried out to the silicon wafer, in the third step annealing process, annealing temperature is default warm from described first
Degree drops to the second preset temperature.
4. the preparation method of silicon wafer according to claim 3, which is characterized in that second preset temperature be 500 DEG C extremely
700℃。
5. the preparation method of silicon wafer according to claim 3, which is characterized in that first step annealing, the second step annealing
With third step annealing carried out in annealing device, carry out second step annealing and carry out the third step annealing it
Between, further includes:
The reducibility gas for being passed through inert gas into the annealing device, and being discharged in the annealing device, to form inertia
Atmosphere.
6. the preparation method of silicon wafer according to claim 1, which is characterized in that first step annealing and the second step annealing
It is to be carried out in annealing device, the forming step of the reducing atmosphere includes:
It is passed through inert gas and reducibility gas, into the annealing device to form the reducing atmosphere, wherein described to go back
Primordial Qi atmosphere be include inert gas and reducibility gas mixed gas atmosphere；
Alternatively,
The inert gas for being passed through the reducibility gas into the annealing device, and being discharged in the annealing device, to be formed
The reducing atmosphere, wherein the reducing atmosphere is the atmosphere for only including the reducibility gas.
7. according to claim 2,5 or the preparation method of 6 described in any item silicon wafers, which is characterized in that the inert gas choosing
From argon gas, helium, neon, Krypton and xenon.
8. the preparation method of silicon wafer according to claim 1, which is characterized in that the reducibility gas is selected from: hydrogen with
And carbon monoxide.
9. the preparation method of silicon wafer according to claim 1, which is characterized in that first preset temperature be 1000 DEG C extremely
1200℃。
10. the preparation method of silicon wafer according to claim 1, which is characterized in that the initial temperature is 500 DEG C to 700
℃。
11. the preparation method of silicon wafer according to claim 1, which is characterized in that first step annealing includes multiple moves back
Fiery stage, the heating rate of posterior annealing stage are less than the heating rate of first annealing stage.
12. the preparation method of silicon wafer according to claim 1, which is characterized in that the anneal duration of second step annealing
It is 30 minutes to 90 minutes.
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN113061991A (en) * | 2021-03-23 | 2021-07-02 | 韩华新能源（启东）有限公司 | Preparation method for improving pyramid texture surface uniformity of monocrystalline silicon wafer and solar cell |
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| US20030089967A1 (en) * | 2001-11-12 | 2003-05-15 | Young-Hee Mun | Silicon wafer and fabricating method therefor |
| US20060027161A1 (en) * | 2004-02-09 | 2006-02-09 | Sumco Corporation | Method for heat-treating silicon wafer and silicon wafer |
| CN1838388A (en) * | 2005-03-21 | 2006-09-27 | 北京有色金属研究总院 | Rapid thermal process for silicon sheet capable of obtaining denuded zone and product thereof |
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| US20030089967A1 (en) * | 2001-11-12 | 2003-05-15 | Young-Hee Mun | Silicon wafer and fabricating method therefor |
| US20060027161A1 (en) * | 2004-02-09 | 2006-02-09 | Sumco Corporation | Method for heat-treating silicon wafer and silicon wafer |
| CN1838388A (en) * | 2005-03-21 | 2006-09-27 | 北京有色金属研究总院 | Rapid thermal process for silicon sheet capable of obtaining denuded zone and product thereof |
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