CN109445855A - A kind of bridge-set integrated for multi-path low speed peripheral hardware - Google Patents
A kind of bridge-set integrated for multi-path low speed peripheral hardware Download PDFInfo
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- CN109445855A CN109445855A CN201811276109.2A CN201811276109A CN109445855A CN 109445855 A CN109445855 A CN 109445855A CN 201811276109 A CN201811276109 A CN 201811276109A CN 109445855 A CN109445855 A CN 109445855A
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
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Abstract
The invention belongs to digital circuit Front-end Design technical fields, and in particular to a kind of applied to the bridge-set integrated for multi-path low speed peripheral hardware for enclosing extension low-speed peripheral outside the processor.Present invention can assure that carrying out reliable and stable data transmitting from higher speed processor external expansion interface to low-speed peripheral.Compared with the scheme for using discrete device to build, the present invention can greatly reduction circuit plate suqare, achieve the purpose that reduce cost, while also providing convenience for logic debugging and use.The present invention can easily provide user in application process and extend setting, facilitate and increase or reduce logic according to actual use situation using stock number, have good adaptability.In addition, the expansible peripheral unit in the present invention can also cascade use, two-level address mapping relations are constructed, the design less for address space also has stronger adaptability.In the case where bandwidth and FPGA resource allow, it is possible to provide realize cross clock domain synchronization process between a processor Peripheral Interface and any multi-path low speed peripheral apparatus.
Description
Technical field
The invention belongs to digital circuit Front-end Design technical fields, and in particular to one kind is applied to enclose extension outside the processor
The bridge-set of low-speed peripheral integrated for multi-path low speed peripheral hardware.
Background technique
In industrial control field, the low-speed communications interface such as serial ports and CAN is common order and data pipeline.One
In a machine system, it will usually multi-channel serial port occur and CAN is integrated on a host node or relay node.These controls
System is generally used in built-in field, is installed in the chassis using the mode of line card.Line card size is smaller, uses traditional string
When mouth control chip and CAN interface control chip are realized, it may appear that the situation of board area deficiency.By enclosing collection outside the processor
At the fpga chip that monolithic capacity is suitable for, multi-channel serial port logic and CAN control logic and bridging logic are integrated into FPGA core
In piece, the area of serial ports and CAN line card can be greatly reduced.
In general, the clock frequency between the external expansion interface of processor and external low-speed device is different from, and locate
The rate of reason device external expansion interface is generally greater than external apparatus interface, about the 2~3 of external apparatus interface logic working rate
Times.At this point, the case where there are cross clock domains between low-speed device outside multi-channel serial port logical AND, if suitable bridge cannot be used
Binding structure will lead to the larger or synchronization failure of logical resource occupancy and cause capability error.
Summary of the invention
(1) technical problems to be solved
The present invention proposes a kind of bridge-set integrated for multi-path low speed peripheral hardware, to solve to carry out multi-channel serial port logical AND
The stationary problem of cross clock domain behavior between external low-speed device.
(2) technical solution
In order to solve the above-mentioned technical problem, the present invention proposes a kind of bridge-set integrated for multi-path low speed peripheral hardware, should
Bridge-set includes synchronous bridge-jointing unit and expansible Peripheral Interface unit；Wherein, synchronous bridge-jointing unit is bidirectional interface unit,
One side interface realizes the connection between processor external expansion interface, and another side interface is realized and expansible Peripheral Interface unit
Between connection；The request of access external equipment is issued by processor, and synchronous bridge-jointing unit quick clock domain side receives access
Request, and request is synchronized to Slow Clock domain side；The signal of different clock-domains two sides is by asking inside synchronous bridge-jointing unit
It asks, sample, feeding back the mode shaken hands, realizing same from high-speed interfaces to low-speed interfaces transmission data and the cross clock domain of control signal
Walk function；Expansible Peripheral Interface unit be bidirectional interface unit, a side interface realize with the connection between synchronous bridge-jointing unit,
Realize the connection with multi-path low speed peripheral apparatus in the other side.
Further, the address between synchronous bridge-jointing unit and expansible Peripheral Interface unit, data/address bus use 32
The discrete mode of width realizes that data input is exported with data to be realized using discrete mode.
Further, has flow control back-pressure signal between synchronous bridge-jointing unit and expansible Peripheral Interface unit, flow control is anti-
It presses signal to be used for the data processing situation to processor side feedback current peripheral, sends the necessary moment of data, control in input
The transmission behavior of processor, guarantee the buffer area of low-speed peripheral not will be dealt with device frequent transmission request be full of, cause to overflow.
Further, when synchronous bridge-jointing unit connect Peripheral Interface of the side using extension with processor external expansion interface
Clock works, and the working frequency of Peripheral Interface clock should be the 1/2 or 1/3 of processor external expansion interface clock frequency.
Further, expansible Peripheral Interface unit completes configuration by macrodefinition parameter mode, and at most connection 232 outer
Portion extends low-speed device.
Further, expansible Peripheral Interface unit has register array, for collecting and storing external extension low speed
The interrupt status of equipment, and the interruption is reported into processor.
(3) beneficial effect
The bridge-set proposed by the present invention integrated for multi-path low speed peripheral hardware, it can be ensured that outside higher speed processor
Expansion interface carries out reliable and stable data transmitting to low-speed peripheral.Compared with the scheme for using discrete device to build, this
Invention can greatly reduction circuit plate suqare, achieve the purpose that reduce cost, while also providing just for logic debugging and use
Benefit.The present invention can easily provide in application process user extend setting, facilitate according to actual use situation increase or
It reduces logic and uses stock number, there is good adaptability.In addition, the expansible peripheral unit in the present invention, which can also cascade, to be made
With construction two-level address mapping relations, the design less for address space also has stronger adaptability.It is provided in bandwidth and FPGA
In the case that source allows, it is possible to provide realize cross clock domain between a processor Peripheral Interface and any multi-path low speed peripheral apparatus
Synchronization process.
Detailed description of the invention
Fig. 1 is bridge-set of embodiment of the present invention configuration diagram；
Fig. 2 is bridge-set of embodiment of the present invention joint detail schematic diagram.
Specific embodiment
To keep the purpose of the present invention, content and advantage clearer, with reference to the accompanying drawings and examples, to tool of the invention
Body embodiment is described in further detail.
The present embodiment proposes the bridge of a kind of integrated six road serial ports and four tunnel CAN controllers integrated for multi-path low speed peripheral hardware
Connection device, framework are as shown in Figure 1.The bridge-set includes synchronous bridge-jointing unit and expansible Peripheral Interface unit.Wherein, together
Step bridge-jointing unit is bidirectional interface unit, and a side interface realizes the connection between processor external expansion interface；It is another to flank
The cause for gossip now connection between expansible Peripheral Interface.Synchronous extended mode can be used in processor, uses appointing within 100MHz
Clock of anticipating is realized with synchronous bridge-jointing unit to be interconnected.The request of access external equipment is issued by processor, and synchronous bridge-jointing unit is quick
Clock domain side receives access request, and request is synchronized to Slow Clock domain side.For Slow Clock domain side, also divide
The case where being distributed for multiple clock, can be used synchronous bridge-jointing unit and does second level division.
Joint detail between synchronous bridge-jointing unit and expansible Peripheral Interface unit, as shown in Figure 2.Wherein, same to fore-and-aft gangway
It connects unit interface and has high bandwidth and flux controllable feature.Address, data/address bus are realized using the discrete mode of 32 bit widths, are counted
It is exported according to input with data and realizes that parallel 32 bidirectional data paths ensure that the maximization of bandwidth of operation using discrete mode.
Interface has flow control back-pressure signal, and the data processing situation of current peripheral can be fed back to processor side, sends data in input
The necessary moment provides flow control back-pressure signal, the transmission behavior of control processor, it is ensured that the reliability of the peripheral hardware course of work guarantees
The frequent transmission request that the buffer area of low-speed peripheral not will be dealt with device is full of, and causes to overflow.The other side of synchronous bridge-jointing unit
It is worked using the Peripheral Interface clock of extension, the present embodiment specifies the working frequency of Peripheral Interface clock to should be processor
1/2 of external expansion interface clock frequency or 1/3 or so, phase is without particular/special requirement.Inside synchronous bridge-jointing unit, when different
The signal of clock domain two sides realizes the synchronization process of cross clock domain signal in such a way that request, sampling, feedback are shaken hands, in the present invention
In the example of description, it should be accomplished that synchronous with the control cross clock domain of signal from high-speed interfaces to low-speed interfaces transmission data
Function.
In terms of framework angle, expansible Peripheral Interface unit is also bidirectional interface unit, and a side interface is realized and same fore-and-aft gangway
The connection with multi-path low speed peripheral apparatus is realized in connection between order member, the other side.Expansible Peripheral Interface part passes through macro
Defined parameters mode is completed to configure, and in the case where setting extended address permission outside the processor, can at most connect 232 low-speed peripherals
Equipment.By the expansible Peripheral Interface unit of the present invention of macrodefinition switchgear distribution, any position in 32 bit address can define
As the starting point of peripheral unit chip select address section, it may specify any width in 32 bit address width as decoding width.In addition,
Expansible Peripheral Interface unit is also equipped with register array, for collecting and storing the interrupt status of external extension low-speed device,
And the interruption is reported into processor.Processor can inquire the specific register number of reporting interruption by register access mode,
And corresponding processing is taken to act.
The above is only a preferred embodiment of the present invention, it is noted that for the ordinary skill people of the art
For member, without departing from the technical principles of the invention, several improvement and deformations can also be made, these improvement and deformations
Also it should be regarded as protection scope of the present invention.
Claims (6)
1. a kind of bridge-set integrated for multi-path low speed peripheral hardware, which is characterized in that the bridge-set includes synchronous bridge joint
Unit and expansible Peripheral Interface unit；Wherein,
The synchronous bridge-jointing unit is bidirectional interface unit, and a side interface realizes the company between processor external expansion interface
It connects, another side interface realizes the connection between the expansible Peripheral Interface unit；The request of external equipment is accessed by handling
Device issues, and the synchronous bridge-jointing unit quick clock domain side receives access request, and request is synchronized to Slow Clock domain one
Side；The signal of different clock-domains two sides is realized in such a way that request, sampling, feedback are shaken hands inside the synchronous bridge-jointing unit
From the cross clock domain synchronizing function of high-speed interfaces to low-speed interfaces transmission data and control signal；
The expansible Peripheral Interface unit be bidirectional interface unit, a side interface realize between the synchronous bridge-jointing unit
The connection with multi-path low speed peripheral apparatus is realized in connection, the other side.
2. bridge-set as described in claim 1, which is characterized in that the synchronous bridge-jointing unit connects with the expansible peripheral hardware
Address, data/address bus between mouth unit realize that data input is with data output using discrete using the discrete mode of 32 bit widths
Mode is realized.
3. bridge-set as described in claim 1, which is characterized in that the synchronous bridge-jointing unit connects with the expansible peripheral hardware
Has flow control back-pressure signal between mouth unit, the flow control back-pressure signal is used for at the data of processor side feedback current peripheral
Reason situation sends the necessary moment of data in input, and the transmission behavior of control processor guarantees that the buffer area of low-speed peripheral will not
It is full of by the frequent transmission request of processor, causes to overflow.
4. bridge-set as described in claim 1, which is characterized in that expand outside the synchronous bridge-jointing unit and the processor
Exhibition interface connection side is worked using the Peripheral Interface clock of extension, and the working frequency of the Peripheral Interface clock should be place
Manage the 1/2 or 1/3 of device external expansion interface clock frequency.
5. bridge-set as described in claim 1, which is characterized in that the expansible Peripheral Interface unit is joined by macrodefinition
Number mode is completed to configure, at most connection 232 external extension low-speed devices.
6. bridge-set as described in claim 1, which is characterized in that the expansible Peripheral Interface unit has register battle array
The interruption for collecting and storing the interrupt status of external extension low-speed device, and is reported processor by column.
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| CN201811276109.2A CN109445855B (en) | 2018-10-30 | 2018-10-30 | Bridging device for multi-path low-speed peripheral integration |
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| CN201811276109.2A CN109445855B (en) | 2018-10-30 | 2018-10-30 | Bridging device for multi-path low-speed peripheral integration |
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